FAILED: patch "[PATCH] crypto: qat - fix firmware loading failure for GEN6 devices" failed to apply to 7.0-stable tree

PATCH New [email protected] 2 participants 3 messages May 3 – May 5

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Stable branch Crypto API QAT driver

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[email protected]

author maintainer

2026-05-03 11:44 UTC #0 lore raw

The patch below does not apply to the 7.0-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

To reproduce the conflict and resubmit, you may use the following commands:

git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-7.0.y
git checkout FETCH_HEAD
git cherry-pick -x e7dcb722bb75bb3f3992f580a8728a794732fd7a
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2026050339-tumble-sponge-5d2f@gregkh' --subject-prefix 'PATCH 7.0.y' HEAD^..

Possible dependencies:

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From e7dcb722bb75bb3f3992f580a8728a794732fd7a Mon Sep 17 00:00:00 2001
From: Suman Kumar Chakraborty <[email protected]>
Date: Thu, 5 Mar 2026 08:58:59 +0000
Subject: [PATCH] crypto: qat - fix firmware loading failure for GEN6 devices
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

QAT GEN6 hardware requires a minimum 3 us delay during the acceleration engine reset sequence to ensure the hardware fully settles. Without this delay, the firmware load may fail intermittently.

Add a delay after placing the AE into reset and before clearing the reset, matching the hardware requirements and ensuring stable firmware loading. Earlier generations remain unaffected.

Fixes 17fd7514ae68 ("crypto: qat - add qat_6xxx driver")

Signed-off-by Suman Kumar Chakraborty <[email protected]>

Cc [email protected]

Reviewed-by Giovanni Cabiddu <[email protected]>

Reviewed-by Andy Shevchenko <[email protected]>

Signed-off-by Herbert Xu <[email protected]>

drivers/crypto/intel/qat/qat_common/adf_accel_engine.c +7 -0

index f9f1018a2823..09d4f547e082 100644
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
 /* Copyright(c) 2014 - 2020 Intel Corporation */
+#include <linux/delay.h>
 #include <linux/firmware.h>
 #include <linux/pci.h>
 #include "adf_cfg.h"

@@ -162,8 +163,14 @@ int adf_ae_stop(struct adf_accel_dev *accel_dev)
 static int adf_ae_reset(struct adf_accel_dev *accel_dev, int ae)
 {
 	struct adf_fw_loader_data *loader_data = accel_dev->fw_loader;
+	unsigned long reset_delay;
 
 	qat_hal_reset(loader_data->fw_loader);
+
+	reset_delay = loader_data->fw_loader->chip_info->reset_delay_us;
+	if (reset_delay)
+		fsleep(reset_delay);
+
 	if (qat_hal_clr_reset(loader_data->fw_loader))
 		return -EFAULT;

drivers/crypto/intel/qat/qat_common/icp_qat_fw_loader_handle.h +1 -0

index 6887930c7995..e74cafa95f1c 100644
@@ -27,6 +27,7 @@ struct icp_qat_fw_loader_chip_info {
 	int mmp_sram_size;
 	bool nn;
 	bool lm2lm3;
+	u16 reset_delay_us;
 	u32 lm_size;
 	u32 icp_rst_csr;
 	u32 icp_rst_mask;

drivers/crypto/intel/qat/qat_common/qat_hal.c +4 -1

index 0f5a2690690a..1c3d1311f1c7 100644
@@ -20,6 +20,7 @@
 #define RST_CSR_QAT_LSB			20
 #define RST_CSR_AE_LSB			0
 #define MC_TIMESTAMP_ENABLE		(0x1 << 7)
+#define MIN_RESET_DELAY_US		3
 
 #define IGNORE_W1C_MASK ((~(1 << CE_BREAKPOINT_BITPOS)) & \
 	(~(1 << CE_CNTL_STORE_PARITY_ERROR_BITPOS)) & \

@@ -713,8 +714,10 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->wakeup_event_val = 0x80000000;
 		handle->chip_info->fw_auth = true;
 		handle->chip_info->css_3k = true;
-		if (handle->pci_dev->device == PCI_DEVICE_ID_INTEL_QAT_6XXX)
+		if (handle->pci_dev->device == PCI_DEVICE_ID_INTEL_QAT_6XXX) {
 			handle->chip_info->dual_sign = true;
+			handle->chip_info->reset_delay_us = MIN_RESET_DELAY_US;
+		}
 		handle->chip_info->tgroup_share_ustore = true;
 		handle->chip_info->fcu_ctl_csr = FCU_CONTROL_4XXX;
 		handle->chip_info->fcu_sts_csr = FCU_STATUS_4XXX;

Sasha Levin

maintainer

2026-05-05 10:17 UTC #1 lore raw

PATCH 1/2 crypto: qat - fix indentation of macros in qat_hal.c

From: Suman Kumar Chakraborty <[email protected]>

[ Upstream commit 4963b39e3a3feed07fbf4d5cc2b5df8498888285 ]

The macros in qat_hal.c were using a mixture of tabs and spaces. Update all macro indentation to use tabs consistently, matching the predominant style.

This does not introduce any functional change.

Signed-off-by Suman Kumar Chakraborty <[email protected]>

Reviewed-by Giovanni Cabiddu <[email protected]>

Signed-off-by Herbert Xu <[email protected]>

Stable-dep-of: e7dcb722bb75 ("crypto: qat - fix firmware loading failure for GEN6 devices")

Signed-off-by Sasha Levin <[email protected]>

---
 drivers/crypto/intel/qat/qat_common/qat_hal.c | 22 +++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)

drivers/crypto/intel/qat/qat_common/qat_hal.c +11 ~~-11~~

index 7a6ba6f22e3e8..0f5a2690690a1 100644
@@ -9,17 +9,17 @@
 #include "icp_qat_hal.h"
 #include "icp_qat_uclo.h"
 
-#define BAD_REGADDR	       0xffff
-#define MAX_RETRY_TIMES	   10000
-#define INIT_CTX_ARB_VALUE	0x0
-#define INIT_CTX_ENABLE_VALUE     0x0
-#define INIT_PC_VALUE	     0x0
-#define INIT_WAKEUP_EVENTS_VALUE  0x1
-#define INIT_SIG_EVENTS_VALUE     0x1
-#define INIT_CCENABLE_VALUE       0x2000
-#define RST_CSR_QAT_LSB	   20
-#define RST_CSR_AE_LSB		  0
-#define MC_TIMESTAMP_ENABLE       (0x1 << 7)
+#define BAD_REGADDR			0xffff
+#define MAX_RETRY_TIMES			10000
+#define INIT_CTX_ARB_VALUE		0x0
+#define INIT_CTX_ENABLE_VALUE		0x0
+#define INIT_PC_VALUE			0x0
+#define INIT_WAKEUP_EVENTS_VALUE	0x1
+#define INIT_SIG_EVENTS_VALUE		0x1
+#define INIT_CCENABLE_VALUE		0x2000
+#define RST_CSR_QAT_LSB			20
+#define RST_CSR_AE_LSB			0
+#define MC_TIMESTAMP_ENABLE		(0x1 << 7)
 
 #define IGNORE_W1C_MASK ((~(1 << CE_BREAKPOINT_BITPOS)) & \
 	(~(1 << CE_CNTL_STORE_PARITY_ERROR_BITPOS)) & \

Signature · 1 line

2.53.0

Sasha Levin

maintainer

2026-05-05 10:17 UTC #2 lore raw

PATCH 2/2 crypto: qat - fix firmware loading failure for GEN6 devices

From: Suman Kumar Chakraborty <[email protected]>

[ Upstream commit e7dcb722bb75bb3f3992f580a8728a794732fd7a ]

QAT GEN6 hardware requires a minimum 3 us delay during the acceleration engine reset sequence to ensure the hardware fully settles. Without this delay, the firmware load may fail intermittently.

Add a delay after placing the AE into reset and before clearing the reset, matching the hardware requirements and ensuring stable firmware loading. Earlier generations remain unaffected.

Fixes 17fd7514ae68 ("crypto: qat - add qat_6xxx driver")

Signed-off-by Suman Kumar Chakraborty <[email protected]>

Cc [email protected]

Reviewed-by Giovanni Cabiddu <[email protected]>

Reviewed-by Andy Shevchenko <[email protected]>

Signed-off-by Herbert Xu <[email protected]>

Signed-off-by Sasha Levin <[email protected]>

---
 drivers/crypto/intel/qat/qat_common/adf_accel_engine.c     | 7 +++++++
 .../crypto/intel/qat/qat_common/icp_qat_fw_loader_handle.h | 1 +
 drivers/crypto/intel/qat/qat_common/qat_hal.c              | 5 ++++-
 3 files changed, 12 insertions(+), 1 deletion(-)

drivers/crypto/intel/qat/qat_common/adf_accel_engine.c +7 -0

index f9f1018a28236..09d4f547e082c 100644
@@ -1,5 +1,6 @@
 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
 /* Copyright(c) 2014 - 2020 Intel Corporation */
+#include <linux/delay.h>
 #include <linux/firmware.h>
 #include <linux/pci.h>
 #include "adf_cfg.h"

@@ -162,8 +163,14 @@ int adf_ae_stop(struct adf_accel_dev *accel_dev)
 static int adf_ae_reset(struct adf_accel_dev *accel_dev, int ae)
 {
 	struct adf_fw_loader_data *loader_data = accel_dev->fw_loader;
+	unsigned long reset_delay;
 
 	qat_hal_reset(loader_data->fw_loader);
+
+	reset_delay = loader_data->fw_loader->chip_info->reset_delay_us;
+	if (reset_delay)
+		fsleep(reset_delay);
+
 	if (qat_hal_clr_reset(loader_data->fw_loader))
 		return -EFAULT;

drivers/crypto/intel/qat/qat_common/icp_qat_fw_loader_handle.h +1 -0

index 6887930c7995e..e74cafa95f1cc 100644
@@ -27,6 +27,7 @@ struct icp_qat_fw_loader_chip_info {
 	int mmp_sram_size;
 	bool nn;
 	bool lm2lm3;
+	u16 reset_delay_us;
 	u32 lm_size;
 	u32 icp_rst_csr;
 	u32 icp_rst_mask;

drivers/crypto/intel/qat/qat_common/qat_hal.c +4 -1

index 0f5a2690690a1..1c3d1311f1c7a 100644
@@ -20,6 +20,7 @@
 #define RST_CSR_QAT_LSB			20
 #define RST_CSR_AE_LSB			0
 #define MC_TIMESTAMP_ENABLE		(0x1 << 7)
+#define MIN_RESET_DELAY_US		3
 
 #define IGNORE_W1C_MASK ((~(1 << CE_BREAKPOINT_BITPOS)) & \
 	(~(1 << CE_CNTL_STORE_PARITY_ERROR_BITPOS)) & \

@@ -713,8 +714,10 @@ static int qat_hal_chip_init(struct icp_qat_fw_loader_handle *handle,
 		handle->chip_info->wakeup_event_val = 0x80000000;
 		handle->chip_info->fw_auth = true;
 		handle->chip_info->css_3k = true;
-		if (handle->pci_dev->device == PCI_DEVICE_ID_INTEL_QAT_6XXX)
+		if (handle->pci_dev->device == PCI_DEVICE_ID_INTEL_QAT_6XXX) {
 			handle->chip_info->dual_sign = true;
+			handle->chip_info->reset_delay_us = MIN_RESET_DELAY_US;
+		}
 		handle->chip_info->tgroup_share_ustore = true;
 		handle->chip_info->fcu_ctl_csr = FCU_CONTROL_4XXX;
 		handle->chip_info->fcu_sts_csr = FCU_STATUS_4XXX;

Signature · 1 line

2.53.0