dt-bindings: misc: Add binding for Xilinx AXI-Stream FIFO
Subsystems (2)
PATCH v2 1/1 dt-bindings: misc: Add binding for Xilinx AXI-Stream FIFO
Add a YAML schema for the Xilinx AXI-Stream FIFO IP core (PG080). The binding documents the three supported compatible strings and all vendor-specific properties that the axis-fifo driver reads from the device tree.
This resolves the following checkpatch.pl warnings in drivers/staging/axis-fifo/axis-fifo.c:
WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.1" appears un-documented
WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.2" appears un-documented
WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.3" appears un-documented
---
Changes in v2:
- Delete drivers/staging/axis-fifo/axis-fifo.txt as part of the conversion (was missing from v1)
- Add all Vivado-generated properties to the schema so that real hardware DT nodes pass validation with additionalProperties: false
- Update example to match a realistic Vivado-generated DT node including all properties
.../bindings/misc/xlnx,axi-fifo-mm-s.yaml | 265 ++++++++++++++++++ MAINTAINERS | 6 + drivers/staging/axis-fifo/axis-fifo.txt | 96 ------- 3 files changed, 271 insertions(+), 96 deletions(-) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml delete mode 100644 drivers/staging/axis-fifo/axis-fifo.txt
Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml new file +265 -0
@@ -0,0 +1,265 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/misc/xlnx,axi-fifo-mm-s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx AXI-Stream FIFO + +maintainers: + - Jacob Feder <[email protected]> + +description: + The Xilinx AXI-Stream FIFO (PG080) provides a memory-mapped interface to + an AXI-Stream FIFO IP core. It allows a processor to transmit and receive + AXI-Stream packets via simple MMIO register reads and writes. + +properties: + compatible: + enum: + - xlnx,axi-fifo-mm-s-4.1 + - xlnx,axi-fifo-mm-s-4.2 + - xlnx,axi-fifo-mm-s-4.3 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + maxItems: 1 + + xlnx,axi-str-rxd-protocol: + $ref: /schemas/types.yaml#/definitions/string + description: + AXI-Stream receive data protocol type. This property is generated by + Vivado and is not used by the driver. + + xlnx,axi-str-rxd-tdata-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Width of the receive AXI-Stream data bus in bits. Currently only 32 + is supported. + const: 32 + + xlnx,axi-str-txc-protocol: + $ref: /schemas/types.yaml#/definitions/string + description: + AXI-Stream transmit control protocol type. This property is generated + by Vivado and is not used by the driver. + + xlnx,axi-str-txc-tdata-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Width of the transmit control AXI-Stream data bus in bits. This + property is generated by Vivado and is not used by the driver. + + xlnx,axi-str-txd-protocol: + $ref: /schemas/types.yaml#/definitions/string + description: + AXI-Stream transmit data protocol type. This property is generated by + Vivado and is not used by the driver. + + xlnx,axi-str-txd-tdata-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Width of the transmit AXI-Stream data bus in bits. Currently only 32 + is supported. + const: 32 + + xlnx,axis-tdest-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + AXI-Stream TDEST signal width in bits. This property is generated by + Vivado and is not used by the driver. + + xlnx,axis-tid-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + AXI-Stream TID signal width in bits. This property is generated by + Vivado and is not used by the driver. + + xlnx,axis-tuser-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + AXI-Stream TUSER signal width in bits. This property is generated by + Vivado and is not used by the driver. + + xlnx,data-interface-type: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Data interface type. This property is generated by Vivado and is not + used by the driver. + + xlnx,has-axis-tdest: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Indicates if the AXI-Stream TDEST signal is present. Cut-through mode + is not supported by the driver; this value must be 0. + const: 0 + + xlnx,has-axis-tid: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Indicates if the AXI-Stream TID signal is present. Cut-through mode + is not supported by the driver; this value must be 0. + const: 0 + + xlnx,has-axis-tkeep: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Indicates if the AXI-Stream TKEEP signal is present. This feature is + not supported by the driver; this value must be 0. + const: 0 + + xlnx,has-axis-tstrb: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Indicates if the AXI-Stream TSTRB signal is present. This feature is + not supported by the driver; this value must be 0. + const: 0 + + xlnx,has-axis-tuser: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Indicates if the AXI-Stream TUSER signal is present. This feature is + not supported by the driver; this value must be 0. + const: 0 + + xlnx,rx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Depth of the receive FIFO in words. + + xlnx,rx-fifo-pe-threshold: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Receive FIFO programmable empty interrupt threshold in words. This + property is generated by Vivado and is not used by the driver. + + xlnx,rx-fifo-pf-threshold: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Receive FIFO programmable full interrupt threshold in words. This + property is generated by Vivado and is not used by the driver. + + xlnx,s-axi-id-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + AXI4 ID signal width in bits. This property is generated by Vivado + and is not used by the driver. + + xlnx,s-axi4-data-width: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + AXI4 data bus width in bits. This property is generated by Vivado and + is not used by the driver. + + xlnx,select-xpm: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Selects Xilinx Parameterized Macro (XPM) memory primitives. This + property is generated by Vivado and is not used by the driver. + + xlnx,tx-fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Depth of the transmit FIFO in words. + + xlnx,tx-fifo-pe-threshold: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Transmit FIFO programmable empty interrupt threshold in words. This + property is generated by Vivado and is not used by the driver. + + xlnx,tx-fifo-pf-threshold: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Transmit FIFO programmable full interrupt threshold in words. This + property is generated by Vivado and is not used by the driver. + + xlnx,use-rx-cut-through: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Enables receive cut-through mode. Cut-through mode is not supported + by the driver; this value must be 0. + const: 0 + + xlnx,use-rx-data: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Set to 1 if the receive data FIFO is enabled, 0 otherwise. + enum: [0, 1] + + xlnx,use-tx-ctrl: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Enables the transmit control FIFO. This feature is not supported by + the driver; this value must be 0. + const: 0 + + xlnx,use-tx-cut-through: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Enables transmit cut-through mode. Cut-through mode is not supported + by the driver; this value must be 0. + const: 0 + + xlnx,use-tx-data: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Set to 1 if the transmit data FIFO is enabled, 0 otherwise. + enum: [0, 1] + +required: + - compatible + - reg + - interrupts + - xlnx,axi-str-rxd-tdata-width + - xlnx,axi-str-txd-tdata-width + - xlnx,rx-fifo-depth + - xlnx,tx-fifo-depth + - xlnx,use-rx-data + - xlnx,use-tx-data + +additionalProperties: false + +examples: + - | + axi_fifo: fifo@43c00000 { + compatible = "xlnx,axi-fifo-mm-s-4.1"; + reg = <0x43c00000 0x10000>; + interrupt-parent = <&intc>; + interrupt-names = "interrupt"; + interrupts = <0 29 4>; + xlnx,axi-str-rxd-protocol = "XIL_AXI_STREAM_ETH_DATA"; + xlnx,axi-str-rxd-tdata-width = <32>; + xlnx,axi-str-txc-protocol = "XIL_AXI_STREAM_ETH_CTRL"; + xlnx,axi-str-txc-tdata-width = <32>; + xlnx,axi-str-txd-protocol = "XIL_AXI_STREAM_ETH_DATA"; + xlnx,axi-str-txd-tdata-width = <32>; + xlnx,axis-tdest-width = <4>; + xlnx,axis-tid-width = <4>; + xlnx,axis-tuser-width = <4>; + xlnx,data-interface-type = <0>; + xlnx,has-axis-tdest = <0>; + xlnx,has-axis-tid = <0>; + xlnx,has-axis-tkeep = <0>; + xlnx,has-axis-tstrb = <0>; + xlnx,has-axis-tuser = <0>; + xlnx,rx-fifo-depth = <0x200>; + xlnx,rx-fifo-pe-threshold = <2>; + xlnx,rx-fifo-pf-threshold = <0x1fb>; + xlnx,s-axi-id-width = <4>; + xlnx,s-axi4-data-width = <32>; + xlnx,select-xpm = <0>; + xlnx,tx-fifo-depth = <0x8000>; + xlnx,tx-fifo-pe-threshold = <0x200>; + xlnx,tx-fifo-pf-threshold = <0x7ffb>; + xlnx,use-rx-cut-through = <0>; + xlnx,use-rx-data = <0>; + xlnx,use-tx-ctrl = <0>; + xlnx,use-tx-cut-through = <0>; + xlnx,use-tx-data = <1>; + };
MAINTAINERS +6 -0
@@ -29130,6 +29130,12 @@ S: Maintained F: Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml F: drivers/net/ethernet/xilinx/xilinx_axienet* +XILINX AXI-STREAM FIFO DRIVER +M: Jacob Feder <[email protected]> +S: Maintained +F: Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml +F: drivers/staging/axis-fifo/ + XILINX CAN DRIVER M: Appana Durga Kedareswara rao <[email protected]> L: [email protected]
drivers/staging/axis-fifo/axis-fifo.txt deleted +0 -96
96 lines not on this page · raw message
Signature · 1 line
2.52.0
Greg KH
maintainerQuoted 21 lines · Pramod Maurya
Add a YAML schema for the Xilinx AXI-Stream FIFO IP core (PG080). The binding documents the three supported compatible strings and all vendor-specific properties that the axis-fifo driver reads from the device tree.
This resolves the following checkpatch.pl warnings in
drivers/staging/axis-fifo/axis-fifo.c:
WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.1" appears un-documented
WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.2" appears un-documented
WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.3" appears un-documentedSigned-off-by Pramod Maurya <[email protected]>---
Changes in v2:
- Deletedrivers/staging/axis-fifo/axis-fifo.txtas part of the conversion (was missing from v1)
- Add all Vivado-generated properties to the schema so that real hardware DT nodes pass validation with additionalProperties: false
- Update example to match a realistic Vivado-generated DT node including all properties
Quoted 5 lines
.../bindings/misc/xlnx,axi-fifo-mm-s.yaml | 265 ++++++++++++++++++ MAINTAINERS | 6 + drivers/staging/axis-fifo/axis-fifo.txt | 96 ------- 3 files changed, 271 insertions(+), 96 deletions(-) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
No, staging drivers need to be self-contained. When/if the axis-fifo driver moves out of drivers/staging/ this can happen, but not until then.
You can convert this to yaml in-place if you want, AND you can test that the conversion is correct. Do you have this hardware to test this with?
thanks,
greg k-h
Quoted 28 lines · Greg KH
Quoted 21 lines · Pramod Maurya
Add a YAML schema for the Xilinx AXI-Stream FIFO IP core (PG080). The binding documents the three supported compatible strings and all vendor-specific properties that the axis-fifo driver reads from the device tree.
This resolves the following checkpatch.pl warnings in
drivers/staging/axis-fifo/axis-fifo.c:
WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.1" appears un-documented
WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.2" appears un-documented
WARNING: DT compatible string "xlnx,axi-fifo-mm-s-4.3" appears un-documentedSigned-off-by Pramod Maurya <[email protected]>---
Changes in v2:
- Deletedrivers/staging/axis-fifo/axis-fifo.txtas part of the conversion (was missing from v1)
- Add all Vivado-generated properties to the schema so that real hardware DT nodes pass validation with additionalProperties: false
- Update example to match a realistic Vivado-generated DT node including all propertiesQuoted 5 lines
.../bindings/misc/xlnx,axi-fifo-mm-s.yaml | 265 ++++++++++++++++++ MAINTAINERS | 6 + drivers/staging/axis-fifo/axis-fifo.txt | 96 ------- 3 files changed, 271 insertions(+), 96 deletions(-) create mode 100644 Documentation/devicetree/bindings/misc/xlnx,axi-fifo-mm-s.yaml
Quoted 6 lines
No, staging drivers need to be self-contained. When/if the axis-fifo driver moves out of
drivers/staging/this can happen, but not until then.You can convert this to yaml in-place if you want, AND you can test that the conversion is correct. Do you have this hardware to test this with?
Copy-pasting from v1...
| Someone else submitted this conversion (which it is, despite you not | removing the old file), and the commentary I provided for that patch | applies here too: | https://lore.kernel.org/all/20260227-unboxed-customary-7ce6eda1858c@spud/
I suspect that this could be a dma-engine and any patch doing a conversion needs to justify why it is not.
pw-bot: changes-requested