arm64: qcom: add Ayaneo Pocket DS gaming console

From: Teguh Sobirin <[email protected]>

Document the Qualcomm QCS8550 based Ayaneo Pocket DS gaming console.

Co-developed-by Alexandre Hamamdjian <[email protected]>

Signed-off-by Alexandre Hamamdjian <[email protected]>

Signed-off-by Teguh Sobirin <[email protected]>

The DT was adapted by myself to fit the upstream standards and one bug was fixed too.

From: Alexandre Hamamdjian <[email protected]>

Add labels for the cpuss, cpu and gpuss thermal zones so board files can extend them with trip points and cooling maps through the &label override syntax, instead of redeclaring the zones by path.

Signed-off-by Alexandre Hamamdjian <[email protected]>

---
  arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 +++++++++++++-------------
  1 file changed, 13 insertions(+), 13 deletions(-)

arch/arm64/boot/dts/qcom/sm8550.dtsi +12 -12

index 912525e9bca6..a9c678fc9cb2 100644
@@ -5764,7 +5764,7 @@ reset-mon-config {
  			};
  		};
 
-		cpuss0-thermal {
+		cpuss0_thermal: cpuss0-thermal {
  			thermal-sensors = <&tsens0 1>;
 
  			trips {

@@ -5782,7 +5782,7 @@ reset-mon-config {
  			};
  		};
 
-		cpuss1-thermal {
+		cpuss1_thermal: cpuss1-thermal {
  			thermal-sensors = <&tsens0 2>;
 
  			trips {

@@ -5800,7 +5800,7 @@ reset-mon-config {
  			};
  		};
 
-		cpuss2-thermal {
+		cpuss2_thermal: cpuss2-thermal {
  			thermal-sensors = <&tsens0 3>;
 
  			trips {

@@ -5818,7 +5818,7 @@ reset-mon-config {
  			};
  		};
 
-		cpuss3-thermal {
+		cpuss3_thermal: cpuss3-thermal {
  			thermal-sensors = <&tsens0 4>;
 
  			trips {

@@ -6028,7 +6028,7 @@ cpu6_bottom_crit: cpu-critical {
  			};
  		};
 
-		cpu7-top-thermal {
+		cpu7_top_thermal: cpu7-top-thermal {
  			thermal-sensors = <&tsens0 13>;
 
  			trips {

@@ -6536,7 +6536,7 @@ reset-mon-config {
  			};
  		};
 
-		gpuss-0-thermal {
+		gpuss0_thermal: gpuss-0-thermal {
  			polling-delay-passive = <10>;
 
  			thermal-sensors = <&tsens2 1>;

@@ -6569,7 +6569,7 @@ trip-point2 {
  			};
  		};
 
-		gpuss-1-thermal {
+		gpuss1_thermal: gpuss-1-thermal {
  			polling-delay-passive = <10>;
 
  			thermal-sensors = <&tsens2 2>;

@@ -6602,7 +6602,7 @@ trip-point2 {
  			};
  		};
 
-		gpuss-2-thermal {
+		gpuss2_thermal: gpuss-2-thermal {
  			polling-delay-passive = <10>;
 
  			thermal-sensors = <&tsens2 3>;

@@ -6635,7 +6635,7 @@ trip-point2 {
  			};
  		};
 
-		gpuss-3-thermal {
+		gpuss3_thermal: gpuss-3-thermal {
  			polling-delay-passive = <10>;
 
  			thermal-sensors = <&tsens2 4>;

@@ -6668,7 +6668,7 @@ trip-point2 {
  			};
  		};
 
-		gpuss-4-thermal {
+		gpuss4_thermal: gpuss-4-thermal {
  			polling-delay-passive = <10>;
 
  			thermal-sensors = <&tsens2 5>;

@@ -6701,7 +6701,7 @@ trip-point2 {
  			};
  		};
 
-		gpuss-5-thermal {
+		gpuss5_thermal: gpuss-5-thermal {
  			polling-delay-passive = <10>;
 
  			thermal-sensors = <&tsens2 6>;

@@ -6734,7 +6734,7 @@ trip-point2 {
  			};
  		};
 
-		gpuss-6-thermal {
+		gpuss6_thermal: gpuss-6-thermal {
  			polling-delay-passive = <10>;
 
  			thermal-sensors = <&tsens2 7>;

Add labels for the cpuss, cpu and gpuss thermal zones so board files can extend them with trip points and cooling maps through the &label override syntax, instead of redeclaring the zones by path.

Thank you for your contribution! Sashiko AI review found 10 potential issue(s) to consider:
- [Medium] Missing DisplayPort AUX (SBU) Routing in Type-C connector.
- [Medium] Missing thermal cooling-maps and incorrect trip point types.
- [Medium] Invalid DAPM widget in audio-routing.
- [Medium] Missing pinctrl-1 property in pwm_fan node.
- [Medium] Improper Audio Amplifier Initialization via pinctrl.
- [Low] Downstream device tree property rocknix-u-boot-dt-id included in root node.
- [Low] Missing compatible string in panel@0 node.
- [Low] Unreferenced volume_up_n pinctrl state, missing Volume Up button.
- [Low] Extraneous orientation-gpios property in pmic-glink.
- [Low] Deprecated gpio property used in fixed regulators.
--

commit 22f111b3d5157012d6f5d9d466cfb26e61ed3b56
Author: Teguh Sobirin <[email protected]>

arm64: dts: qcom: add basic devicetree for Ayaneo Pocket DS gaming console

Add initial Device Tree for the Ayaneo Pocket DS gaming console based on the Qualcomm QCS8550 platform.

Quoted 6 lines

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +1 -0

new file mode 100644
@@ -0,0 +1,1861 @@
+// SPDX-License-Identifier: BSD-3-Clause

[ ... ]

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts line 36

Quoted 4 lines

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +4 -0

+/ {
+	model = "AYANEO Pocket DS";
+	compatible = "ayaneo,pocketds", "qcom,qcs8550", "qcom,sm8550";
+	rocknix-u-boot-dt-id = "u-boot-pocket-ds";

Is this downstream U-Boot property intended for upstream submission? It does not appear to be documented in the upstream DT bindings.

Quoted 3 lines

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +2 -0

+
+	aliases {

[ ... ]

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts line 55

Quoted 8 lines

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +8 -0

+	tca6424_vcc: regulator-tca6424-vcc {
+		compatible = "regulator-fixed";
+		regulator-name = "tca6424_vcc";
+
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpio = <&tlmm 168 GPIO_ACTIVE_HIGH>;

This isn't a bug, but could we use gpios here instead of the deprecated gpio property? This also applies to vdd_ts and vdd_fan_5v0 later in the file.

Quoted 3 lines

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +2 -0

+		enable-active-high;
+		regulator-boot-on;

[ ... ]

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts line 75

Quoted 5 lines

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +5 -0

+	pmic-glink {
+		compatible = "qcom,sm8550-pmic-glink", "qcom,pmic-glink";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		orientation-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;

Does the qcom,pmic-glink driver read orientation-gpios?

The driver appears to rely on IPC with the firmware to determine Type-C orientation, which would make this property unused here.

Quoted 25 lines

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +24 -0

+
+		connector@0 {
+			compatible = "usb-c-connector";
+			reg = <0>;
+			power-role = "dual";
+			data-role = "dual";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+
+					pmic_glink_hs_in: endpoint {
+						remote-endpoint = <&usb_1_dwc3_hs>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+
+					pmic_glink_ss_in: endpoint {
+						remote-endpoint = <&redriver_ss_out>;

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts line 61

Quoted 4 lines

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +4 -0

+					};
+				};
+			};
+		};

The commit message states DisplayPort is muxed over the USB-C connector, but port@2 (SBU) is missing. Is SBU routing needed here for the DP AUX channel (link training and EDID) to ensure DisplayPort Alt Mode functions correctly?

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts line 199

Quoted 8 lines

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +7 -0

+	sound {
+		compatible = "qcom,sm8550-sndcard", "qcom,sm8450-sndcard";
+		model = "SM8550-APS";
+		audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT",
+				"SpkrRight IN", "WSA_SPK2 OUT",
+				"VA DMIC0", "vdd-micb",
+				"VA DMIC1", "vdd-micb";

Is vdd-micb a valid DAPM widget name here?

It looks like the regulator supply name for the VA macro. Will DAPM fail to parse this route and leave the digital microphones' bias voltage disabled?

[ ... ]

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts line 317

Quoted 5 lines

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +5 -0

+	pwm_fan: pwm-fan {
+		compatible = "pwm-fan";
+
+		pinctrl-0 = <&fan_pwm_active>, <&fan_int>;
+		pinctrl-names = "default", "sleep";

Are we missing pinctrl-1 here?

Since pinctrl-names defines a sleep state, won't the PM core fail when attempting to look up pinctrl-1 during transitions?

[ ... ]

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts line 396

Quoted 9 lines

+&cpuss0_thermal {

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +8 -0

+	polling-delay = <200>;
+
+	trips {
+		cpuss0_fan0: trip-point2 {
+			temperature = <40000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};

Should the trip point type be active instead of passive since these are intended for a fan?

Also, are the cooling-maps omitted intentionally across the thermal zones? Without them, the kernel thermal framework cannot bind these trip points to the pwm_fan cooling device.

[ ... ]

Quoted 1 line

+&pm8550_gpios {

[ ... ]

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts line 1204

Quoted 7 lines

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +7 -0

+	volume_up_n: volume-up-n-state {
+		pins = "gpio6";
+		function = "normal";
+		power-source = <1>;
+		bias-pull-up;
+		input-enable;
+	};

This pinctrl state is defined but does not appear to be referenced anywhere. Are we missing a gpio-keys device node to instantiate the Volume Up button?

[ ... ]

Quoted 1 line

+&tlmm {

[ ... ]

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts line 1464

Quoted 7 lines

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +7 -0

+	spkr_1_sd_n_active: spkr-1-sd-n-active-state {
+		pins = "gpio7";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-high;
+	};

Will setting output-high statically configure the active-low speaker shutdown pins to drive high at boot?

This might prematurely power up the amplifiers before the audio framework is initialized, potentially causing an audible pop noise.

[ ... ]

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts line 1671

Quoted 13 lines

+&mdss_dsi0 {

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +12 -0

+	vdda-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+
+	display_panel: panel@0 {
+		reg = <0>;
+
+		pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>;
+		pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>;
+		pinctrl-names = "default", "sleep";
+	};
+};

Does this panel node need a compatible string?

Even if panel support is being added later, leaving a child node on an enabled DSI host incomplete violates the DT schema and will likely cause the DSI core to fail when parsing child devices.

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +8 -0

+		compatible = "regulator-fixed";
+		regulator-name = "vdd_fan_5v0";
+
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+
+		gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
+		enable-active-high;

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +986 -0

+		compatible = "regulator-fixed";
+
+		regulator-name = "upd720201_avdd33";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		vin-supply = <&vph_pwr>;
+
+		pinctrl-0 = <&upd720201_avdd33>;
+		pinctrl-names = "default";
+	};
+
+	upd720201_vdd10_reg: upd720201-vdd10-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "upd720201_vdd10";
+		regulator-min-microvolt = <1050000>;
+		regulator-max-microvolt = <1050000>;
+
+		gpios = <&tlmm 13 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		vin-supply = <&vph_pwr>;
+
+		pinctrl-0 = <&upd720201_vdd10>;
+		pinctrl-names = "default";
+	};
+
+	upd720201_vdd33_reg: upd720201-vdd33-regulator {
+		compatible = "regulator-fixed";
+
+		regulator-name = "upd720201_vdd33";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+
+		gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+
+		vin-supply = <&vph_pwr>;
+
+		pinctrl-0 = <&upd720201_vdd33>;
+		pinctrl-names = "default";
+	};
+
+	pwm_fan: pwm-fan {
+		compatible = "pwm-fan";
+
+		pinctrl-0 = <&fan_pwm_active>, <&fan_int>;
+		pinctrl-names = "default", "sleep";
+
+		fan-supply = <&vdd_fan_5v0>;
+		pwms = <&pm8550_pwm 3 40000>;
+		interrupt-parent = <&tlmm>;
+		interrupts = <64 IRQ_TYPE_EDGE_FALLING>;
+
+		#cooling-cells = <2>;
+		cooling-levels = <0 30 45 60 70 90 120 150>;
+	};
+
+	wcn7850-pmu {
+		compatible = "qcom,wcn7850-pmu";
+
+		pinctrl-0 = <&wlan_en>, <&bt_default>, <&pmk8550_sleep_clk>;
+		pinctrl-names = "default";
+
+		wlan-enable-gpios = <&tlmm 80 GPIO_ACTIVE_HIGH>;
+		bt-enable-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
+
+		vdd-supply = <&vreg_s5g_0p85>;
+		vddio-supply = <&vreg_l15b_1p8>;
+		vddaon-supply = <&vreg_s2g_0p85>;
+		vdddig-supply = <&vreg_s4e_0p95>;
+		vddrfa1p2-supply = <&vreg_s4g_1p25>;
+		vddrfa1p8-supply = <&vreg_s6g_1p86>;
+
+		regulators {
+			vreg_pmu_rfa_cmn: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn";
+			};
+
+			vreg_pmu_aon_0p59: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p59";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p85: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p85";
+			};
+
+			vreg_pmu_btcmx_0p85: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p85";
+			};
+
+			vreg_pmu_rfa_0p8: ldo5 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo6 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p8: ldo7 {
+				regulator-name = "vreg_pmu_rfa_1p8";
+			};
+
+			vreg_pmu_pcie_0p9: ldo8 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_pcie_1p8: ldo9 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+		};
+	};
+};
+
+&cpuss0_thermal {
+	polling-delay = <200>;
+
+	trips {
+		cpuss0_fan0: trip-point2 {
+			temperature = <40000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss0_fan1: trip-point3 {
+			temperature = <50000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss0_fan2: trip-point4 {
+			temperature = <60000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss0_fan3: trip-point5 {
+			temperature = <65000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss0_fan4: trip-point6 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss0_fan5: trip-point7 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss0_fan6: trip-point8 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&cpuss1_thermal {
+	polling-delay = <200>;
+
+	trips {
+		cpuss1_fan0: trip-point2 {
+			temperature = <40000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss1_fan1: trip-point3 {
+			temperature = <50000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss1_fan2: trip-point4 {
+			temperature = <60000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss1_fan3: trip-point5 {
+			temperature = <65000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss1_fan4: trip-point6 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss1_fan5: trip-point7 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss1_fan6: trip-point8 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&cpuss2_thermal {
+	polling-delay = <200>;
+
+	trips {
+		cpuss2_fan0: trip-point2 {
+			temperature = <40000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss2_fan1: trip-point3 {
+			temperature = <50000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss2_fan2: trip-point4 {
+			temperature = <60000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss2_fan3: trip-point5 {
+			temperature = <65000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss2_fan4: trip-point6 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss2_fan5: trip-point7 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss2_fan6: trip-point8 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&cpuss3_thermal {
+	polling-delay = <200>;
+
+	trips {
+		cpuss3_fan0: trip-point2 {
+			temperature = <40000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss3_fan1: trip-point3 {
+			temperature = <50000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss3_fan2: trip-point4 {
+			temperature = <60000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss3_fan3: trip-point5 {
+			temperature = <65000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss3_fan4: trip-point6 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss3_fan5: trip-point7 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpuss3_fan6: trip-point8 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&cpu7_top_thermal {
+	polling-delay = <200>;
+
+	trips {
+		cpu7_top_fan0: trip-point2 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpu7_top_fan1: trip-point3 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		cpu7_top_fan2: trip-point4 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpuss0_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss0_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss0_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss0_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpuss1_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss1_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss1_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss1_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpuss2_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss2_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss2_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss2_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpuss3_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss3_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss3_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss3_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpuss4_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss4_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss4_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss4_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpuss5_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss5_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss5_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss5_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpuss6_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss6_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss6_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss6_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+&gpuss7_thermal {
+	polling-delay = <200>;
+
+	trips {
+		gpuss7_fan0: trip-point3 {
+			temperature = <70000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss7_fan1: trip-point4 {
+			temperature = <75000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+
+		gpuss7_fan2: trip-point5 {
+			temperature = <80000>;
+			hysteresis = <3000>;
+			type = "passive";
+		};
+	};
+};
+
+/* DMIC 01 23 */
+&lpass_vamacro {
+	pinctrl-0 = <&dmic01_default>, <&dmic23_default>;
+	pinctrl-names = "default";
+	vdd-micb-supply = <&vreg_l10b_1p8>;
+	qcom,dmic-sample-rate = <4800000>;
+};
+
+&apps_rsc {
+	regulators-0 {
+		compatible = "qcom,pm8550-rpmh-regulators";
+		qcom,pmic-id = "b";
+
+		vdd-bob1-supply = <&vph_pwr>;
+		vdd-bob2-supply = <&vph_pwr>;
+		vdd-l1-l4-l10-supply = <&vreg_s6g_1p86>;
+		vdd-l2-l13-l14-supply = <&vreg_bob1>;
+		vdd-l3-supply = <&vreg_s4g_1p25>;
+		vdd-l5-l16-supply = <&vreg_bob1>;
+		vdd-l6-l7-supply = <&vreg_bob1>;
+		vdd-l8-l9-supply = <&vreg_bob1>;
+		vdd-l11-supply = <&vreg_s4g_1p25>;
+		vdd-l12-supply = <&vreg_s6g_1p86>;
+		vdd-l15-supply = <&vreg_s6g_1p86>;
+		vdd-l17-supply = <&vreg_bob2>;
+
+		vreg_bob1: bob1 {
+			regulator-name = "vreg_bob1";
+			regulator-min-microvolt = <3296000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_bob2: bob2 {
+			regulator-name = "vreg_bob2";
+			regulator-min-microvolt = <2720000>;
+			regulator-max-microvolt = <3960000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2b_3p0: ldo2 {
+			regulator-name = "vreg_l2b_3p0";
+			regulator-min-microvolt = <3008000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l5b_3p1: ldo5 {
+			regulator-name = "vreg_l5b_3p1";
+			regulator-min-microvolt = <3104000>;
+			regulator-max-microvolt = <3104000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l6b_1p8: ldo6 {
+			regulator-name = "vreg_l6b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l7b_1p8: ldo7 {
+			regulator-name = "vreg_l7b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l8b_1p8: ldo8 {
+			regulator-name = "vreg_l8b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l9b_2p9: ldo9 {
+			regulator-name = "vreg_l9b_2p9";
+			regulator-min-microvolt = <2960000>;
+			regulator-max-microvolt = <3008000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l10b_1p8: ldo10 {
+			regulator-name = "vreg_l10b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l11b_1p2: ldo11 {
+			regulator-name = "vreg_l11b_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l12b_1p8: ldo12 {
+			regulator-name = "vreg_l12b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l13b_3p0: ldo13 {
+			regulator-name = "vreg_l13b_3p0";
+			regulator-min-microvolt = <3000000>;
+			regulator-max-microvolt = <3000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l14b_3p2: ldo14 {
+			regulator-name = "vreg_l14b_3p2";
+			regulator-min-microvolt = <3200000>;
+			regulator-max-microvolt = <3200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l15b_1p8: ldo15 {
+			regulator-name = "vreg_l15b_1p8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l16b_2p8: ldo16 {
+			regulator-name = "vreg_l16b_2p8";
+			regulator-min-microvolt = <2800000>;
+			regulator-max-microvolt = <2800000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l17b_2p5: ldo17 {
+			regulator-name = "vreg_l17b_2p5";
+			regulator-min-microvolt = <2504000>;
+			regulator-max-microvolt = <2504000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-1 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+		qcom,pmic-id = "c";
+
+		vdd-l1-supply = <&vreg_s4g_1p25>;
+		vdd-l2-supply = <&vreg_s4e_0p95>;
+		vdd-l3-supply = <&vreg_s4e_0p95>;
+
+		vreg_l3c_0p9: ldo3 {
+			regulator-name = "vreg_l3c_0p9";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-2 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+		qcom,pmic-id = "d";
+
+		vdd-l1-supply = <&vreg_s4e_0p95>;
+		vdd-l2-supply = <&vreg_s4e_0p95>;
+		vdd-l3-supply = <&vreg_s4e_0p95>;
+
+		vreg_l1d_0p88: ldo1 {
+			regulator-name = "vreg_l1d_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <920000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-3 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+		qcom,pmic-id = "e";
+
+		vdd-l1-supply = <&vreg_s4e_0p95>;
+		vdd-l2-supply = <&vreg_s4e_0p95>;
+		vdd-l3-supply = <&vreg_s4g_1p25>;
+		vdd-s4-supply = <&vph_pwr>;
+		vdd-s5-supply = <&vph_pwr>;
+
+		vreg_s4e_0p95: smps4 {
+			regulator-name = "vreg_s4e_0p95";
+			regulator-min-microvolt = <904000>;
+			regulator-max-microvolt = <984000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s5e_1p08: smps5 {
+			regulator-name = "vreg_s5e_1p08";
+			regulator-min-microvolt = <1010000>;
+			regulator-max-microvolt = <1120000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1e_0p88: ldo1 {
+			regulator-name = "vreg_l1e_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <880000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2e_0p9: ldo2 {
+			regulator-name = "vreg_l2e_0p9";
+			regulator-min-microvolt = <904000>;
+			regulator-max-microvolt = <970000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3e_1p2: ldo3 {
+			regulator-name = "vreg_l3e_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-4 {
+		compatible = "qcom,pm8550ve-rpmh-regulators";
+		qcom,pmic-id = "f";
+
+		vdd-l1-supply = <&vreg_s4e_0p95>;
+		vdd-l2-supply = <&vreg_s4e_0p95>;
+		vdd-l3-supply = <&vreg_s4e_0p95>;
+		vdd-s4-supply = <&vph_pwr>;
+
+		vreg_s4f_0p5: smps4 {
+			regulator-name = "vreg_s4f_0p5";
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <700000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1f_0p9: ldo1 {
+			regulator-name = "vreg_l1f_0p9";
+			regulator-min-microvolt = <912000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l2f_0p88: ldo2 {
+			regulator-name = "vreg_l2f_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3f_0p88: ldo3 {
+			regulator-name = "vreg_l3f_0p88";
+			regulator-min-microvolt = <880000>;
+			regulator-max-microvolt = <912000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+
+	regulators-5 {
+		compatible = "qcom,pm8550vs-rpmh-regulators";
+		qcom,pmic-id = "g";
+		vdd-l1-supply = <&vreg_s4g_1p25>;
+		vdd-l2-supply = <&vreg_s4g_1p25>;
+		vdd-l3-supply = <&vreg_s4g_1p25>;
+		vdd-s1-supply = <&vph_pwr>;
+		vdd-s2-supply = <&vph_pwr>;
+		vdd-s3-supply = <&vph_pwr>;
+		vdd-s4-supply = <&vph_pwr>;
+		vdd-s5-supply = <&vph_pwr>;
+		vdd-s6-supply = <&vph_pwr>;
+
+		vreg_s1g_1p25: smps1 {
+			regulator-name = "vreg_s1g_1p25";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1300000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s2g_0p85: smps2 {
+			regulator-name = "vreg_s2g_0p85";
+			regulator-min-microvolt = <800000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s3g_0p8: smps3 {
+			regulator-name = "vreg_s3g_0p8";
+			regulator-min-microvolt = <300000>;
+			regulator-max-microvolt = <1004000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s4g_1p25: smps4 {
+			regulator-name = "vreg_s4g_1p25";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1352000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s5g_0p85: smps5 {
+			regulator-name = "vreg_s5g_0p85";
+			regulator-min-microvolt = <500000>;
+			regulator-max-microvolt = <1004000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_s6g_1p86: smps6 {
+			regulator-name = "vreg_s6g_1p86";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l1g_1p2: ldo1 {
+			regulator-name = "vreg_l1g_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+
+		vreg_l3g_1p2: ldo3 {
+			regulator-name = "vreg_l3g_1p2";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+			regulator-allow-set-load;
+			regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM
+						   RPMH_REGULATOR_MODE_HPM>;
+		};
+	};
+};
+
+&pm8550_gpios {
+	sdc2_card_det_n: sdc2-card-det-n-state {
+		pins = "gpio12";
+		function = "normal";
+		input-enable;
+		output-disable;
+		bias-pull-up;
+		power-source = <1>;
+	};
+
+	volume_up_n: volume-up-n-state {
+		pins = "gpio6";
+		function = "normal";
+		power-source = <1>;
+		bias-pull-up;
+		input-enable;
+	};
+
+	fan_pwm_active: fan-pwm-active-state {
+		pins = "gpio9";
+		function = "func1";
+		output-low;
+		bias-disable;
+		power-source = <0>;
+		qcom,drive-strength = <3>; /* PMIC_GPIO_STRENGTH_LOW */
+	};
+};
+
+&pmk8550_gpios {
+	pmk8550_sleep_clk: sleep-clk-state {
+		pins = "gpio3";
+		function = "func1";
+		input-disable;
+		output-enable;
+		bias-disable;
+		power-source = <0>;
+	};
+};
+
+&pm8550b_eusb2_repeater {
+	vdd18-supply = <&vreg_l15b_1p8>;
+	vdd3-supply = <&vreg_l5b_3p1>;
+};
+
+&pon_pwrkey {
+	status = "okay";
+};
+
+&pon_resin {
+	linux,code = <KEY_VOLUMEDOWN>;
+
+	status = "okay";
+};
+
+&pmk8550_rtc {
+	nvmem-cells = <&rtc_offset>;
+	nvmem-cell-names = "offset";
+};
+
+&pmk8550_sdam_2 {
+	rtc_offset: rtc-offset@bc {
+		reg = <0xbc 0x4>;
+	};
+};

arch/arm64/boot/dts/qcom/qcs8550-ayaneo-pocketds.dts new file +520 -0

+		clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+		clock-names = "se";
+		pinctrl-0 = <&qup_uart11_default>;
+		pinctrl-names = "default";
+		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
+		interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+				 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+				<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+				 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+		interconnect-names = "qup-core", "qup-config";
+		operating-points-v2 = <&qup_opp_table_100mhz>;
+		power-domains = <&rpmhpd RPMHPD_CX>;
+
+		status = "okay";
+	};
+};
+
+&remoteproc_adsp {
+	firmware-name = "qcom/sm8550/ayaneo/adsp.mdt",
+			"qcom/sm8550/ayaneo/adsp_dtb.mdt";
+
+	status = "okay";
+};
+
+&sdhc_2 {
+	cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
+	pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
+	pinctrl-names = "default", "sleep";
+	vmmc-supply = <&vreg_l9b_2p9>;
+	vqmmc-supply = <&vreg_l8b_1p8>;
+	no-sdio;
+	no-mmc;
+
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
+
+	qcom,dll-config = <0x0007442c>;
+	sdhci-caps-mask = <0x3 0x0>;
+
+	status = "okay";
+};
+
+&sleep_clk {
+	clock-frequency = <32764>;
+};
+
+&swr0 {
+	status = "okay";
+
+	spk_amp_l: speaker@0,0 {
+		compatible = "sdw20217020400";
+		reg = <0 0>;
+
+		pinctrl-0 = <&spkr_1_sd_n_active>;
+		pinctrl-names = "default";
+
+		powerdown-gpios = <&tlmm 7 GPIO_ACTIVE_LOW>;
+
+		vdd-1p8-supply = <&vreg_l10b_1p8>;
+		vdd-io-supply = <&vreg_l10b_1p8>;
+
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrLeft";
+		qcom,port-mapping = <1 2 3 7 10 13>;
+	};
+
+	spk_amp_r: speaker@0,1 {
+		compatible = "sdw20217020400";
+		reg = <0 1>;
+
+		pinctrl-0 = <&spkr_2_sd_n_active>;
+		pinctrl-names = "default";
+
+		powerdown-gpios = <&tlmm 12 GPIO_ACTIVE_LOW>;
+
+		vdd-1p8-supply = <&vreg_l10b_1p8>;
+		vdd-io-supply = <&vreg_l10b_1p8>;
+
+		#sound-dai-cells = <0>;
+		sound-name-prefix = "SpkrRight";
+		qcom,port-mapping = <4 5 6 7 11 13>;
+	};
+};
+
+&tlmm {
+	gpio-reserved-ranges = <32 4>;
+
+	bt_default: bt-default-state {
+		bt-en-pins {
+			pins = "gpio81";
+			function = "gpio";
+			drive-strength = <16>;
+			bias-disable;
+		};
+
+		sw-ctrl-pins {
+			pins = "gpio82";
+			function = "gpio";
+			bias-pull-down;
+		};
+	};
+
+	fan_pwr_active: fan-pwr-active-state {
+		pins = "gpio31";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-low;
+	};
+
+	fan_int: fan-int-state {
+		pins = "gpio64";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-up;
+	};
+
+	upd720201_avdd33: upd720201-avdd33-state {
+		pins = "gpio10";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	upd720201_vdd10: upd720201-vdd10-state {
+		pins = "gpio13";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	upd720201_vdd33: upd720201-vdd33-state {
+		pins = "gpio18";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	gamepad_pwr_en: gamepad-pwr-en-active-state {
+		pins = "gpio52";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-disable;
+		output-high;
+	};
+
+	qup_uart11_default: qup-uart11-default-state {
+		/* TX, RX */
+		pins = "gpio70", "gpio71";
+		function = "qup2_se3";
+		drive-strength = <2>;
+		bias-disable;
+	};
+
+	sde_dsi_active: sde-dsi-active-state {
+		pins = "gpio133";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+		output-high;
+	};
+
+	sde_dsi_suspend: sde-dsi-suspend-state {
+		pins = "gpio133";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	sde_te_active: sde-te-active-state {
+		pins = "gpio86";
+		function = "mdp_vsync";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	sde_te_suspend: sde-te-suspend-state {
+		pins = "gpio86";
+		function = "mdp_vsync";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	wlan_en: wlan-en-state {
+		pins = "gpio80";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-down;
+	};
+
+	spkr_1_sd_n_active: spkr-1-sd-n-active-state {
+		pins = "gpio7";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-high;
+	};
+
+	spkr_2_sd_n_active: spkr-2-sd-n-active-state {
+		pins = "gpio12";
+		function = "gpio";
+		drive-strength = <16>;
+		bias-disable;
+		output-high;
+	};
+
+	panel_pwr_active: panel-pwr-active-state {
+		pins = "gpio152", "gpio153";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+		output-high;
+	};
+
+	sde_dsi1_active: sde-dsi1-active-state {
+		pins = "gpio137";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+		output-high;
+	};
+
+	sde_dsi1_suspend: sde-dsi1-suspend-state {
+		pins = "gpio137";
+		function = "gpio";
+		drive-strength = <2>;
+		bias-pull-down;
+	};
+
+	ts_rst_default: ts-rst-default-state {
+		pins = "gpio24";
+		function = "gpio";
+		bias-pull-up;
+		drive-strength = <8>;
+	};
+
+	ts_rst_sleep: ts-rst-sleep-state {
+		pins = "gpio24";
+		function = "gpio";
+		bias-pull-down;
+		drive-strength = <2>;
+	};
+
+	ts_int_default: ts-int-default-state {
+		pins = "gpio25";
+		function = "gpio";
+		bias-pull-up;
+		drive-strength = <8>;
+	};
+
+	ts_int_sleep: ts-int-sleep-state {
+		pins = "gpio25";
+		function = "gpio";
+		bias-pull-down;
+		drive-strength = <2>;
+	};
+
+	ts2_irq: ts2-irq-state {
+		pins = "gpio39";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-disable;
+	};
+
+	ts2_reset: ts2-reset-state {
+		pins = "gpio38";
+		function = "gpio";
+		drive-strength = <8>;
+		bias-pull-down;
+	};
+};
+
+&pm8550_pwm {
+	status = "okay";
+};
+
+&xo_board {
+	clock-frequency = <76800000>;
+};
+
+&gpi_dma1 {
+	status = "okay";
+};
+
+&gpi_dma2 {
+	status = "okay";
+};
+
+&gpu {
+	status = "okay";
+};
+
+&gpu_zap_shader {
+	firmware-name = "qcom/sm8550/a740_zap.mbn";
+};
+
+&gpu_opp_table {
+	opp-719000000 {
+		opp-hz = /bits/ 64 <719000000>;
+		opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+		opp-peak-kBps = <10687500>; // Level 7
+		qcom,opp-acd-level = <0x882e5ffd>;
+	};
+
+	opp-746000000 {
+		opp-hz = /bits/ 64 <746000000>;
+		opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+		opp-peak-kBps = <10687500>; // Level 7
+		qcom,opp-acd-level = <0x882e5ffd>;
+	};
+
+	opp-794000000 {
+		opp-hz = /bits/ 64 <794000000>;
+		opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+		opp-peak-kBps = <14398438>; // Level 8
+		qcom,opp-acd-level = <0xa82d5ffd>;
+	};
+
+	opp-827000000 {
+		opp-hz = /bits/ 64 <827000000>;
+		opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+		opp-peak-kBps = <16500000>; // Level 9
+		qcom,opp-acd-level = <0xa82d5ffd>;
+	};
+
+	opp-860000000 {
+		opp-hz = /bits/ 64 <860000000>;
+		opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+		opp-peak-kBps = <16500000>; // Level 9
+		qcom,opp-acd-level = <0x882d5ffd>;
+	};
+
+	opp-1000000000 {
+		opp-hz = /bits/ 64 <1000000000>;
+		opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
+		opp-peak-kBps = <16500000>; // Level 9
+		qcom,opp-acd-level = <0x882d5ffd>;
+	};
+};
+
+&i2c_master_hub_0 {
+	status = "okay";
+};
+
+&i2c_hub_2 {
+	status = "okay";
+
+	typec-retimer@1c {
+		compatible = "onnn,nb7vpq904m";
+		reg = <0x1c>;
+		vcc-supply = <&vreg_l15b_1p8>;
+
+		retimer-switch;
+		orientation-switch;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				redriver_ss_out: endpoint {
+					remote-endpoint = <&pmic_glink_ss_in>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				redriver_ss_in: endpoint {
+					data-lanes = <3 2 1 0>;
+					remote-endpoint = <&usb_dp_qmpphy_out>;
+				};
+			};
+		};
+	};
+};
+
+&mdss {
+	status = "okay";
+};
+
+&mdss_dp0 {
+	status = "okay";
+};
+
+&mdss_dp0_out {
+	data-lanes = <0 1 2 3>;
+};
+
+&mdss_dsi0 {
+	vdda-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+
+	display_panel: panel@0 {
+		reg = <0>;
+
+		pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>;
+		pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>;
+		pinctrl-names = "default", "sleep";
+	};
+};
+
+&mdss_dsi0_phy {
+	vdds-supply = <&vreg_l1e_0p88>;
+
+	status = "okay";
+};
+
+&pcie0 {
+	wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
+	perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
+
+	max-link-speed = <3>;
+
+	pinctrl-0 = <&pcie0_default_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+};
+
+&pcie1 {
+	wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+	perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+
+	pinctrl-0 = <&pcie1_default_state>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	pcie@0 {
+		/* Renesas μPD720201 PCIe USB3.0 HOST CONTROLLER */
+		usb-controller@0 {
+			compatible = "pci1912,0014";
+			reg = <0x10000 0x0 0x0 0x0 0x0>;
+
+			avdd33-supply = <&upd720201_avdd33_reg>;
+			vdd10-supply = <&upd720201_vdd10_reg>;
+			vdd33-supply = <&upd720201_vdd33_reg>;
+
+			pinctrl-0 = <&gamepad_pwr_en>;
+			pinctrl-names = "default";
+		};
+	};
+};
+
+&pcie1_phy {
+	vdda-phy-supply = <&vreg_l3c_0p9>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+	vdda-qref-supply = <&vreg_l1e_0p88>;
+
+	status = "okay";
+};
+
+&ufs_mem_hc {
+	reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
+
+	vcc-supply = <&vreg_l17b_2p5>;
+	vcc-max-microamp = <1300000>;
+	vccq-supply = <&vreg_l1g_1p2>;
+	vccq-max-microamp = <1200000>;
+	vdd-hba-supply = <&vreg_l3g_1p2>;
+
+	status = "okay";
+};
+
+&ufs_mem_phy {
+	vdda-phy-supply = <&vreg_l1d_0p88>;
+	vdda-pll-supply = <&vreg_l3e_1p2>;
+
+	status = "okay";
+};
+
+&usb_1 {
+	status = "okay";
+};
+
+&usb_1_dwc3_hs {
+	remote-endpoint = <&pmic_glink_hs_in>;
+};
+
+&usb_1_hsphy {
+	vdd-supply = <&vreg_l1e_0p88>;
+	vdda12-supply = <&vreg_l3e_1p2>;
+
+	phys = <&pm8550b_eusb2_repeater>;
+
+	status = "okay";
+};
+
+&usb_dp_qmpphy {
+	vdda-phy-supply = <&vreg_l3e_1p2>;
+	vdda-pll-supply = <&vreg_l3f_0p88>;
+
+	status = "okay";
+};
+
+&usb_dp_qmpphy_out {
+	remote-endpoint = <&redriver_ss_in>;
+};
+
+&uart7 {
+	status = "okay";
+};
+
+&uart14 {
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn7850-bt";
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddwlcx-supply = <&vreg_pmu_wlcx_0p8>;

I will fix the naming scheme and blank line for the next revision.

Quoted 1 line

Why isn't this part of the SoC?

I was suggested to look at similar devicetree (ayaneo-pocket-s2) which is doing the same defining in the exact same way the SoC regulators, labeled thermal nodes, pmu etc..
I am open to staying consistent but would like the same consistency to be set or questioned for others the same way.

Quoted 2 lines

Looks like random ordering...

I can reorder if you have advice or documentation on better ordering