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arm64: dts: socfpga: agilex5: popuplate reset property for I3C and NAND

PATCH New Dinh Nguyen 2 participants 2 messages May 27 Device tree bindings

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Dinh Nguyen

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PATCH 1/1 arm64: dts: socfpga: agilex5: popuplate reset property for I3C and NAND

The I3C and NAND nodes are missing the reset property that is needed to bring the IP out of reset.

Signed-off-by Dinh Nguyen <[email protected]>
---
 arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 3 +++
 1 file changed, 3 insertions(+)
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +3 -0
index b06c6d5d60eed..7d7b3b4706cb5 100644
@@ -244,6 +244,7 @@ i3c0: i3c@10da0000 {
 			reg = <0x10da0000 0x1000>;
 			#address-cells = <3>;
 			#size-cells = <0>;
+			resets = <&rst I3C0_RESET>;
 			interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
 			status = "disabled";

@@ -255,6 +256,7 @@ i3c1: i3c@10da1000 {
 			reg = <0x10da1000 0x1000>;
 			#address-cells = <3>;
 			#size-cells = <0>;
+			resets = <&rst I3C1_RESET>;
 			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
 			status = "disabled";

@@ -313,6 +315,7 @@ nand: nand-controller@10b80000 {
 			cdns,board-delay-ps = <4830>;
 			iommus = <&smmu 4>;
 			dma-coherent;
+			resets = <&rst NAND_RESET>;
 			status = "disabled";
 		};
Signature · 1 line
2.42.0.411.g813d9a9188
AI review
#1 lore raw
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider: - [High] Missing `reset-names` property causes the `dw-i3c-master` driver to silently fail to deassert the…

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Missing reset-names property causes the dw-i3c-master driver to silently fail to deassert the I3C resets.
- [Medium] The Cadence NAND driver lacks reset subsystem integration, rendering the new resets property ineffective.
- [Medium] Adding the resets property violates the snps,dw-i3c-master and cdns,hp-nfc DT bindings, causing dtbs_check validation errors. --

commit 8dcedebea5fbdeab502fe0008a7be9fe724b28a3
Author: Dinh Nguyen <[email protected]>

arm64: dts: socfpga: agilex5: popuplate reset property for I3C and NAND

This commit adds the resets property to the I3C and NAND nodes for Agilex5. The goal is to provide the necessary properties to bring the IP blocks out of reset.

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi i3c0: i3c@10da0000 { · line 247

Quoted 9 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +1 -0
index 02e62d954e949..7fc75b439925c 100644
@@ -244,6 +244,7 @@ i3c0: i3c@10da0000 {
 			reg = <0x10da0000 0x1000>;
 			#address-cells = <3>;
 			#size-cells = <0>;
+			resets = <&rst I3C0_RESET>;

[Severity: Medium]
Will this cause dtbs_check validation errors?

The resets property is currently undefined in the dt-binding schema for the Synopsys DesignWare I3C master:

Documentation/devicetree/bindings/i3c/snps,dw-i3c-master.yaml

Since the schema enforces unevaluatedProperties: false, adding this property without updating the YAML binding will result in compilation warnings.

[Severity: High]
Does the dw-i3c-master driver require a corresponding reset-names property to function correctly?

Looking at the driver implementation, it explicitly requests the reset line by name:

drivers/i3c/master/dw-i3c-master.c:

    devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev,
                                                         "core_rst");

If reset-names = "core_rst" is missing from the device tree node, the lookup fails. Because the driver uses the optional API variant, it silently returns NULL, and the IP block will not be brought out of reset.

[ ... ]

arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi nand: nand-controller@10b80000 { · line 318

Quoted 5 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +1 -0
@@ -313,6 +315,7 @@ nand: nand-controller@10b80000 {
 			cdns,board-delay-ps = <4830>;
 			iommus = <&smmu 4>;
 			dma-coherent;
+			resets = <&rst NAND_RESET>;

[Severity: Medium]
Is this property supported by the Cadence NAND dt-bindings?

Similar to the I3C master, the cdns,hp-nfc YAML schema enforces
unevaluatedProperties: false but does not define a resets property.

Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml

[Severity: Medium]
Does the Cadence NAND driver actually consume this reset property?

The driver code does not currently appear to contain any logic to acquire or deassert a reset control:

drivers/mtd/nand/raw/cadence-nand-controller.c

Since it never calls a function like devm_reset_control_get(), the NAND IP will remain in reset until the driver implementation is updated.

Quoted 2 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +0 -0
 			status = "disabled";
 		};
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1