FAILED: patch "[PATCH] drm/i915/psr: Apply Intel DPCD workaround when SDP on prior" failed to apply to 6.12-stable tree
[email protected]
maintainerThe patch below does not apply to the 6.12-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.12.y
git checkout FETCH_HEAD
git cherry-pick -x 4703049f768fc1c1caac754134118bee1a3af189
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2026052816-harvest-stinking-041d@gregkh' --subject-prefix 'PATCH 6.12.y' HEAD^..
Possible dependencies:
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 4703049f768fc1c1caac754134118bee1a3af189 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jouni=20H=C3=B6gander?= <[email protected]>
Date: Fri, 15 May 2026 12:57:55 +0300
Subject: [PATCH] drm/i915/psr: Apply Intel DPCD workaround when SDP on prior
line used
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
There is Intel specific workaround DPCD address containing workaround for case where SDP is on prior line. Apply this workaround according to values in the offset.
drivers/gpu/drm/i915/display/intel_psr.c +31 -4
@@ -1365,9 +1365,35 @@ static bool psr2_granularity_check(struct intel_crtc_state *crtc_state,return true; } -static bool _compute_psr2_sdp_prior_scanline_indication (struct intel_dp *intel_dp, -struct intel_crtc_state *crtc_state) +static bool apply_scanline_indication_wa (struct intel_crtc_state *crtc_state, +struct intel_connector *connector) { +struct intel_dp *intel_dp =intel_attached_dp (connector); +u8 early_scanline_support = connector->dp.psr_caps.intel_wa_dpcd & +INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_EARLYSCANLINE_SDP_SUPPORT_MASK ; + +if (intel_dp->edp_dpcd[0 ] >=DP_EDP_15 ) +return true; + +switch (early_scanline_support) { +case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_FALL_BACK_TO_PSR1 : + crtc_state->req_psr2_sdp_prior_scanline = false; +return false; +case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_WITH_EARLY_SCANLINE : +return true; +case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_WITHOUT_EARLY_SCANLINE : + crtc_state->req_psr2_sdp_prior_scanline = false; +return true; +default : +MISSING_CASE (early_scanline_support); +return false; + } +} + +static bool _compute_psr2_sdp_prior_scanline_indication (struct intel_crtc_state *crtc_state, +struct intel_connector *connector) +{ +struct intel_dp *intel_dp =intel_attached_dp (connector);struct intel_display *display =to_intel_display (intel_dp);const struct drm_display_mode *adjusted_mode = &crtc_state->uapi.adjusted_mode;u32 hblank_total, hblank_ns, req_ns;
@@ -1386,7 +1412,8 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dreturn false; crtc_state->req_psr2_sdp_prior_scanline = true; -return true; + +return apply_scanline_indication_wa (crtc_state, connector); } static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp,
@@ -1667,7 +1694,7 @@ static bool intel_sel_update_config_valid(struct intel_crtc_state *crtc_state, conn_state)) goto unsupported; -if (!_compute_psr2_sdp_prior_scanline_indication (intel_dp, crtc_state)) { +if (!_compute_psr2_sdp_prior_scanline_indication (crtc_state, connector)) {drm_dbg_kms (display->drm,"Selective update not enabled, SDP indication do not fit in hblank\n" ); goto unsupported;
PATCH 1/4 drm/i915/psr: Add defininitions for INTEL_WA_REGISTER_CAPS DPCD register
commit fbceb39b536e40c2f7cc47ab42037bb7c2b7ced9 upstream.
EDP specification says:
"If either VSC SDP is unable to be transmitted 100 ns before the SU region, the Source device may optionally transmit the VSC SDP during the prior video scan line’s HBlank period There is a Intel specific drm dp register currently containing bits related how TCON can support PSR2 with SDP on prior line."
Unfortunately many panels are having problems in implementing this. So there is a custom Intel specific DPCD register (INTEL_WA_REGISTER_CAPS) to figure out if this is properly implemented on a panel or if panel doesn't require that 100 ns delay before the SU region. Here are the definitions in this custom DPCD address:
0 = Panel doesn't support SDP on prior line
1 = Panel supports SDP on prior line
2 = Panel doesn't have 100ns requirement
3 = Reserved
Add definitions for this new register and it's values into new header intel_dpcd.h.
v2: add INTEL_DPCD_ prefix to definitions
Bspec: 74741
--- drivers/gpu/drm/i915/display/intel_dpcd.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 drivers/gpu/drm/i915/display/intel_dpcd.h
drivers/gpu/drm/i915/display/intel_dpcd.h new file +15 -0
@@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +/* +* Copyright © 2026 Intel Corporation +*/ + +#ifndef __INTEL_DPCD_H__ +#define __INTEL_DPCD_H__ + +#define INTEL_DPCD_INTEL_WA_REGISTER_CAPS 0x3f0 +# define INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_EARLYSCANLINE_SDP_SUPPORT_MASK REG_GENMASK(1, 0) +# define INTEL_DPCD_INTEL_WA_REGISTER_CAPS_FALL_BACK_TO_PSR1 0 +# define INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_WITH_EARLY_SCANLINE 1 +# define INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_WITHOUT_EARLY_SCANLINE 2 + +#endif /* __INTEL_DPCD_H__ */
Signature · 1 line
2.43.0
PATCH 2/4 drm/i915/psr: Read Intel DPCD workaround register
commit f30bece421a4ae34359254e1dc2a187a42b6af9b upstream.
Read Intel DPCD workaround register and store it into intel_connector->dp.psr_caps. psr_caps was chosen as currently it contains only PSR workaround for PSR2 SDP on prior scanline implementation.
--- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++++ 2 files changed, 8 insertions(+)
drivers/gpu/drm/i915/display/intel_display_types.h +1 -0
@@ -1773,6 +1773,7 @@ struct intel_dp {u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE ];u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT ][DP_LTTPR_PHY_CAP_SIZE ];u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE ]; +u8 intel_wa_dpcd;/* source rates */ int num_source_rates;const int *source_rates;
drivers/gpu/drm/i915/display/intel_psr.c +7 -0
@@ -35,6 +35,7 @@#include "intel_de.h" #include "intel_display_types.h" #include "intel_dp.h" +#include "intel_dpcd.h" #include "intel_dp_aux.h" #include "intel_frontbuffer.h" #include "intel_hdmi.h"
@@ -665,6 +666,12 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp)drm_dbg_kms (display->drm,"PSR2 %ssupported\n" , intel_dp->psr.sink_psr2_support ?"" :"not " ); } + +if (intel_dp->psr.sink_psr2_support) +drm_dp_dpcd_read (&intel_dp->aux, +INTEL_DPCD_INTEL_WA_REGISTER_CAPS , + &intel_dp->intel_wa_dpcd, +sizeof (intel_dp->intel_wa_dpcd)); }void intel_psr_init_dpcd (struct intel_dp *intel_dp)
Signature · 1 line
2.43.0
PATCH 3/4 drm/dp: Add eDP 1.5 bit definition
In reply to Jouni HöganderFrom: Suraj Kandpal <[email protected]>
commit 5dfc37a6b77bf6beedbd30d70184b54e1a08ccac upstream.
Add the eDP revision bit value for 1.5.
Spec: eDPv1.5 Table 16-5
--- include/drm/display/drm_dp.h | 1 + 1 file changed, 1 insertion(+)
include/drm/display/drm_dp.h +1 -0
@@ -997,6 +997,7 @@# define DP_EDP_14 0x03# define DP_EDP_14a 0x04/* eDP 1.4a */ # define DP_EDP_14b 0x05/* eDP 1.4b */ +# define DP_EDP_15 0x06/* eDP 1.5 */ #define DP_EDP_GENERAL_CAP_1 0x701# define DP_EDP_TCON_BACKLIGHT_ADJUSTMENT_CAP (1 << 0)
Signature · 1 line
2.43.0
PATCH 4/4 drm/i915/psr: Apply Intel DPCD workaround when SDP on prior line used
In reply to Jouni Högandercommit 4703049f768fc1c1caac754134118bee1a3af189 upstream.
There is Intel specific workaround DPCD address containing workaround for case where SDP is on prior line. Apply this workaround according to values in the offset.
--- drivers/gpu/drm/i915/display/intel_psr.c | 27 +++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-)
drivers/gpu/drm/i915/display/intel_psr.c +26 -1
@@ -1303,6 +1303,30 @@ static bool psr2_granularity_check(struct intel_dp *intel_dp,return true; } +static bool apply_scanline_indication_wa (struct intel_dp *intel_dp, +struct intel_crtc_state *crtc_state) +{ +u8 early_scanline_support = intel_dp->intel_wa_dpcd & +INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_EARLYSCANLINE_SDP_SUPPORT_MASK ; + +if (intel_dp->edp_dpcd[0 ] >=DP_EDP_15 ) +return true; + +switch (early_scanline_support) { +case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_FALL_BACK_TO_PSR1 : + crtc_state->req_psr2_sdp_prior_scanline = false; +return false; +case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_WITH_EARLY_SCANLINE : +return true; +case INTEL_DPCD_INTEL_WA_REGISTER_CAPS_PSR2_WITHOUT_EARLY_SCANLINE : + crtc_state->req_psr2_sdp_prior_scanline = false; +return true; +default : +MISSING_CASE (early_scanline_support); +return false; + } +} +static bool _compute_psr2_sdp_prior_scanline_indication (struct intel_dp *intel_dp,struct intel_crtc_state *crtc_state) {
@@ -1324,7 +1348,8 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_dreturn false; crtc_state->req_psr2_sdp_prior_scanline = true; -return true; + +return apply_scanline_indication_wa (intel_dp, crtc_state); } static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp,
Signature · 1 line
2.43.0