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clk: add support for Airoha AN7583 clock

PATCH Superseded Christian Marangi 3 participants 8 messages May 28 – Jun 8

Subsystems (3)
Device tree bindings Common clk Reset controller framework

v5 of 12 Superseded Latest is v12 →

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Christian Marangi

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#0 lore raw

v5 cover clk: add support for Airoha AN7583 clock

This small series introduce some cleanup and support for clock and reset of Airoha AN7583.

The implementation is similar to EN7581 but AN7583 introduce new reset and more clock divisor support.

Changes v5:
- Rebase on top of linux-next
- Drop even more patch to reduce patch delta
- Make chip-scu specific to AN7583

Changes v4:
- Add review tag for DT patch
- Fix clock patch to use en7581-chip-scu compatible
- Drop PCIE SCU SSR write

Changes v3:
- Drop .set_rate patch (will be proposed later)
- Drop chip-scu binding and related patch

Link https://lore.kernel.org/all/[email protected] open here

Changes v2:
- Add .set_rate support
- Rework DT to EN7581 implementation (clock driver is parent)
- Add additional cleanup patch
- Merge binding with schema patch
- Add chip_scu phandle

Christian Marangi (3):
dt-bindings: clock: airoha: Document support for AN7583 clock
clk: en7523: generalize register clocks function
clk: en7523: add support for Airoha AN7583 clock

 .../bindings/clock/airoha,en7523-scu.yaml     |  18 ++
 drivers/clk/clk-en7523.c                      | 239 +++++++++++++++++-
 include/dt-bindings/clock/en7523-clk.h        |   3 +
 .../dt-bindings/reset/airoha,an7583-reset.h   |  62 +++++
 4 files changed, 320 insertions(+), 2 deletions(-)
 create mode 100644 include/dt-bindings/reset/airoha,an7583-reset.h
Signature · 1 line
2.53.0
author
#1 lore raw

PATCH v5 1/3 dt-bindings: clock: airoha: Document support for AN7583 clock

Document support for Airoha AN7583 clock. This is based on the EN7523 clock schema with the new requirement of the "airoha,chip-scu".

Add additional binding for additional clock and reset lines.

Signed-off-by Christian Marangi <[email protected]>
---
 .../bindings/clock/airoha,en7523-scu.yaml     | 18 ++++++
 include/dt-bindings/clock/en7523-clk.h        |  3 +
 .../dt-bindings/reset/airoha,an7583-reset.h   | 62 +++++++++++++++++++
 3 files changed, 83 insertions(+)
 create mode 100644 include/dt-bindings/reset/airoha,an7583-reset.h
Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +18 -0
index eb24a5687639..6c3c88798515 100644
@@ -30,6 +30,7 @@ properties:
   compatible:
     items:
       - enum:
+          - airoha,an7583-scu
           - airoha,en7523-scu
           - airoha,en7581-scu
           - econet,en751221-scu

@@ -50,12 +51,29 @@ properties:
     description: ID of the controller reset line
     const: 1
 
+  airoha,chip-scu:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle to Chip SCU
+
 required:
   - compatible
   - reg
   - '#clock-cells'
 
 allOf:
+  - if:
+      properties:
+        compatible:
+          const: airoha,an7583-scu
+
+    then:
+      required:
+        - airoha,chip-scu
+
+    else:
+      properties:
+        airoha,chip-scu: false
+
   - if:
       properties:
         compatible:
include/dt-bindings/clock/en7523-clk.h +3 -0
index edfa64045f52..0fbbcb7b1b25 100644
@@ -14,4 +14,7 @@
 
 #define EN7581_CLK_EMMC		8
 
+#define AN7583_CLK_MDIO0	9
+#define AN7583_CLK_MDIO1	10
+
 #endif /* _DT_BINDINGS_CLOCK_AIROHA_EN7523_H_ */
include/dt-bindings/reset/airoha,an7583-reset.h new file +62 -0

62 lines not on this page · raw message

Signature · 1 line
2.53.0
AI review
#2 lore raw

Re: [PATCH v5 1/3] dt-bindings: clock: airoha: Document support for AN7583 clock

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [Medium] The new compatible string 'airoha,an7583-scu' is missing from the conditional `if-then` blocks…

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] The new compatible string 'airoha,an7583-scu' is missing from the conditional if-then blocks defining reg constraints.
- [Low] Inconsistent naming and formatting for the MDIO reset definitions.
--

commit 9e967d083029b29362d6e7b62c4a330c47bee22b
Author: Christian Marangi <[email protected]>

dt-bindings: clock: airoha: Document support for AN7583 clock

This commit documents support for the Airoha AN7583 clock based on the EN7523 clock schema, adding the "airoha,chip-scu" requirement. It also adds an additional binding for extra clock and reset lines.

Quoted 4 lines
Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +0 -0
index eb24a5687639e..6c3c887985153 100644

[ ... ]

Quoted 20 lines
Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +10 -0
@@ -50,12 +51,29 @@ properties:
     description: ID of the controller reset line
     const: 1
 
+  airoha,chip-scu:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle to Chip SCU
+
 required:
   - compatible
   - reg
   - '#clock-cells'
 
 allOf:
+  - if:
+      properties:
+        compatible:
+          const: airoha,an7583-scu
+
+    then:

Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml properties: · line 79

Quoted 10 lines
Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +7 -0
+      required:
+        - airoha,chip-scu
+
+    else:
+      properties:
+        airoha,chip-scu: false
+
   - if:
       properties:
         compatible:

[Severity: Medium]
Since the AN7583 shares the same register layout as the EN7581, shouldn't "airoha,an7583-scu" also be added to the if-then conditional block further down that enforces maxItems: 1 for the reg property?

Omitting it leaves the reg property unconstrained for this new hardware generation, which bypasses validation constraints.

Quoted 6 lines
include/dt-bindings/reset/airoha,an7583-reset.h new file +0 -0
new file mode 100644
index 0000000000000..7ff07986f8ba2
@@ -0,0 +1,62 @@

[ ... ]

include/dt-bindings/reset/airoha,an7583-reset.h line 35

Quoted 6 lines
include/dt-bindings/reset/airoha,an7583-reset.h new file +6 -0
+#define AN7583_TDMA_RST			19
+#define AN7583_EMMC_RST			20
+#define AN7583_SOE_RST			21
+#define AN7583_XFP_MAC_RST		22
+#define AN7583_MDIO0                    23
+#define AN7583_MDIO1                    24

[Severity: Low]
Are the _RST suffixes intentionally omitted from AN7583_MDIO0 and AN7583_MDIO1?

They seem to be missing the suffix used by all other reset constants in this file, which might cause ambiguity with the matching clock macros.

Could these also be updated to use tabs instead of spaces for value alignment to match the rest of the file?

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1
#3 lore raw

Re: [PATCH v5 1/3] dt-bindings: clock: airoha: Document support for AN7583 clock

In reply to Christian Marangi
Quoted 26 lines · Christian Marangi

Document support for Airoha AN7583 clock. This is based on the EN7523 clock schema with the new requirement of the "airoha,chip-scu".

Add additional binding for additional clock and reset lines.

Signed-off-by Christian Marangi <[email protected]>
---
 .../bindings/clock/airoha,en7523-scu.yaml     | 18 ++++++
 include/dt-bindings/clock/en7523-clk.h        |  3 +
 .../dt-bindings/reset/airoha,an7583-reset.h   | 62 +++++++++++++++++++
 3 files changed, 83 insertions(+)
 create mode 100644 include/dt-bindings/reset/airoha,an7583-reset.h
Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +1 -0
index eb24a5687639..6c3c88798515 100644
@@ -30,6 +30,7 @@ properties:
   compatible:
     items:
       - enum:
+          - airoha,an7583-scu
           - airoha,en7523-scu
           - airoha,en7581-scu
           - econet,en751221-scu

Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml properties: · line 56

Quoted 6 lines
Documentation/devicetree/bindings/clock/airoha,en7523-scu.yaml +3 -0
@@ -50,12 +51,29 @@ properties:
     description: ID of the controller reset line
     const: 1
 
+  airoha,chip-scu:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description: phandle to Chip SCU

Here you explain for what purpose this device needs to reference SCU. This is SCU, so I don't understand why SCU needs phandle to Chip SCU...

Best regards,
Krzysztof

author
#4 lore raw

PATCH v5 2/3 clk: en7523: generalize register clocks function

In reply to Christian Marangi

Airoha AN7583 SoC will use the same logic used by Airoha EN7581 SoC to register clocks. Generalize it to register clocks defined in soc_data.

Add the clocks definition in EN7581 SoC to support this new implementation.

Signed-off-by Christian Marangi <[email protected]>
---
 drivers/clk/clk-en7523.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)
drivers/clk/clk-en7523.c +7 -2
index 1ab0e2eca5d3..087ff4568124 100644
@@ -115,6 +115,7 @@ struct en_rst_data {
 
 struct en_clk_soc_data {
 	u32 num_clocks;
+	const struct en_clk_desc *base_clks;
 	const struct clk_ops pcie_ops;
 	int (*hw_init)(struct platform_device *pdev,
 		       struct clk_hw_onecell_data *clk_data);

@@ -711,12 +712,15 @@ static int en7523_clk_hw_init(struct platform_device *pdev,
 static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
 				   struct regmap *map, void __iomem *base)
 {
+	const struct en_clk_soc_data *soc_data;
 	struct clk_hw *hw;
 	u32 rate;
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) {
-		const struct en_clk_desc *desc = &en7581_base_clks[i];
+	soc_data = device_get_match_data(dev);
+
+	for (i = 0; i < soc_data->num_clocks - 1; i++) {
+		const struct en_clk_desc *desc = &soc_data->base_clks[i];
 		u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg;
 		int err;
 

@@ -991,6 +995,7 @@ static const struct en_clk_soc_data en7523_data = {
 };
 
 static const struct en_clk_soc_data en7581_data = {
+	.base_clks = en7581_base_clks,
 	/* We increment num_clocks by 1 to account for additional PCIe clock */
 	.num_clocks = ARRAY_SIZE(en7581_base_clks) + 1,
 	.pcie_ops = {
Signature · 1 line
2.53.0
AI review
#5 lore raw

Re: [PATCH v5 2/3] clk: en7523: generalize register clocks function

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:

Pre-existing issues:
- [High] The PCIe clock backing structure is allocated with devm_kzalloc() but registered with non-managed clk_hw_register(), leading to a UAF if probe fails. --

commit 8b129b6c8b9f7c7f67a06021102b7f5673eead5f
Author: Christian Marangi <[email protected]>

clk: en7523: generalize register clocks function

This commit generalizes the clock registration logic used by the Airoha EN7581 SoC to also support the AN7583 SoC. It updates the implementation to register clocks defined in the new soc_data structures.

Quoted 4 lines
drivers/clk/clk-en7523.c +0 -0
index 1ab0e2eca5d32..087ff4568124f 100644

[ ... ]

drivers/clk/clk-en7523.c static int en7523_clk_hw_init(struct platform_device *pdev, · line 714

Quoted 4 lines
drivers/clk/clk-en7523.c +0 -0
@@ -711,12 +712,15 @@ static int en7523_clk_hw_init(struct platform_device *pdev,
 static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_data *clk_data,
 				   struct regmap *map, void __iomem *base)
 {

[Severity: High]
This isn't a bug introduced by this patch, but looking at en7523_register_pcie_clk() which is called at the end of this function, it appears the clock backing structure is allocated with devm_kzalloc() but registered with the non-managed clk_hw_register().

If probe fails later, the driver core will automatically unwind devm resources and free the structure. However, because the clock was not registered with devm_clk_hw_register(), CCF is never notified to unregister the clock and retains dangling pointers to it.

Could this lead to a use-after-free if the CCF is subsequently accessed, for example by reading clk_summary? Should en7523_register_pcie_clk() be updated to use devm_clk_hw_register() instead?

Quoted 13 lines
drivers/clk/clk-en7523.c +5 -2
+	const struct en_clk_soc_data *soc_data;
 	struct clk_hw *hw;
 	u32 rate;
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(en7581_base_clks); i++) {
-		const struct en_clk_desc *desc = &en7581_base_clks[i];
+	soc_data = device_get_match_data(dev);
+
+	for (i = 0; i < soc_data->num_clocks - 1; i++) {
+		const struct en_clk_desc *desc = &soc_data->base_clks[i];
 		u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg;
 		int err;
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
author
#6 lore raw

PATCH v5 3/3 clk: en7523: add support for Airoha AN7583 clock

In reply to Christian Marangi

Add support for Airoha AN7583 clock and reset.

Airoha AN7583 SoC have the same register address of EN7581 but implement different bits and additional base clocks. Also reset are different with the introduction of 2 dedicated MDIO line and drop of some reset lines.

Signed-off-by Christian Marangi <[email protected]>
---
 drivers/clk/clk-en7523.c | 230 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 230 insertions(+)
drivers/clk/clk-en7523.c +230 -0
index 087ff4568124..217d5d5f932d 100644
@@ -10,6 +10,7 @@
 #include <linux/regmap.h>
 #include <linux/reset-controller.h>
 #include <dt-bindings/clock/en7523-clk.h>
+#include <dt-bindings/reset/airoha,an7583-reset.h>
 #include <dt-bindings/reset/airoha,en7523-reset.h>
 #include <dt-bindings/reset/airoha,en7581-reset.h>
 #include <dt-bindings/clock/econet,en751221-scu.h>

@@ -134,6 +135,14 @@ static const u32 crypto_base[] = { 540000000, 480000000 };
 static const u32 emmc7581_base[] = { 200000000, 150000000 };
 /* EN751221 */
 static const u32 gsw751221_base[] = { 500000000, 250000000, 400000000, 200000000 };
+/* AN7583 */
+static const u32 gsw7583_base[] = { 540672000, 270336000, 400000000, 200000000 };
+static const u32 emi7583_base[] = { 540672000, 480000000, 400000000, 300000000 };
+static const u32 bus7583_base[] = { 600000000, 540672000, 480000000, 400000000 };
+static const u32 spi7583_base[] = { 400000000, 12500000 };
+static const u32 npu7583_base[] = { 666000000, 800000000, 720000000, 600000000 };
+static const u32 crypto7583_base[] = { 540672000, 400000000 };
+static const u32 emmc7583_base[] = { 150000000, 200000000 };
 
 static const struct en_clk_desc en7523_base_clks[] = {
 	{

@@ -336,6 +345,138 @@ static const struct en_clk_desc en7581_base_clks[] = {
 	}
 };
 
+static const struct en_clk_desc an7583_base_clks[] = {
+	{
+		.id = EN7523_CLK_GSW,
+		.name = "gsw",
+
+		.base_reg = REG_GSW_CLK_DIV_SEL,
+		.base_bits = 2,
+		.base_shift = 8,
+		.base_values = gsw7583_base,
+		.n_base_values = ARRAY_SIZE(gsw7583_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	}, {
+		.id = EN7523_CLK_EMI,
+		.name = "emi",
+
+		.base_reg = REG_EMI_CLK_DIV_SEL,
+		.base_bits = 2,
+		.base_shift = 8,
+		.base_values = emi7583_base,
+		.n_base_values = ARRAY_SIZE(emi7583_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	}, {
+		.id = EN7523_CLK_BUS,
+		.name = "bus",
+
+		.base_reg = REG_BUS_CLK_DIV_SEL,
+		.base_bits = 2,
+		.base_shift = 8,
+		.base_values = bus7583_base,
+		.n_base_values = ARRAY_SIZE(bus7583_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	}, {
+		.id = EN7523_CLK_SLIC,
+		.name = "slic",
+
+		.base_reg = REG_SPI_CLK_FREQ_SEL,
+		.base_bits = 1,
+		.base_shift = 1,
+		.base_values = slic_base,
+		.n_base_values = ARRAY_SIZE(slic_base),
+
+		.div_reg = REG_SPI_CLK_DIV_SEL,
+		.div_bits = 5,
+		.div_shift = 24,
+		.div_val0 = 20,
+		.div_step = 2,
+	}, {
+		.id = EN7523_CLK_SPI,
+		.name = "spi",
+
+		.base_reg = REG_SPI_CLK_FREQ_SEL,
+		.base_bits = 1,
+		.base_shift = 0,
+		.base_values = spi7583_base,
+		.n_base_values = ARRAY_SIZE(spi7583_base),
+
+		.div_reg = REG_SPI_CLK_DIV_SEL,
+		.div_bits = 5,
+		.div_shift = 8,
+		.div_val0 = 40,
+		.div_step = 2,
+	}, {
+		.id = EN7523_CLK_NPU,
+		.name = "npu",
+
+		.base_reg = REG_NPU_CLK_DIV_SEL,
+		.base_bits = 2,
+		.base_shift = 9,
+		.base_values = npu7583_base,
+		.n_base_values = ARRAY_SIZE(npu7583_base),
+
+		.div_bits = 3,
+		.div_shift = 0,
+		.div_step = 1,
+		.div_offset = 1,
+	}, {
+		.id = EN7523_CLK_CRYPTO,
+		.name = "crypto",
+
+		.base_reg = REG_CRYPTO_CLKSRC2,
+		.base_bits = 1,
+		.base_shift = 0,
+		.base_values = crypto7583_base,
+		.n_base_values = ARRAY_SIZE(crypto7583_base),
+	}, {
+		.id = EN7581_CLK_EMMC,
+		.name = "emmc",
+
+		.base_reg = REG_CRYPTO_CLKSRC2,
+		.base_bits = 1,
+		.base_shift = 13,
+		.base_values = emmc7583_base,
+		.n_base_values = ARRAY_SIZE(emmc7583_base),
+	}, {
+		.id = AN7583_CLK_MDIO0,
+		.name = "mdio0",
+
+		.base_reg = REG_CRYPTO_CLKSRC2,
+
+		.base_value = 25000000,
+
+		.div_bits = 4,
+		.div_shift = 15,
+		.div_step = 1,
+		.div_offset = 1,
+	}, {
+		.id = AN7583_CLK_MDIO1,
+		.name = "mdio1",
+
+		.base_reg = REG_CRYPTO_CLKSRC2,
+
+		.base_value = 25000000,
+
+		.div_bits = 4,
+		.div_shift = 19,
+		.div_step = 1,
+		.div_offset = 1,
+	}
+};
+
 static const u16 en7581_rst_ofs[] = {
 	REG_RST_CTRL2,
 	REG_RST_CTRL1,

@@ -505,6 +646,60 @@ static const u16 en751221_rst_map[] = {
 	[EN751221_USB_PHY_P1_RST]	= 3 * RST_NR_PER_BANK + 7,
 };
 
+static const u16 an7583_rst_map[] = {
+	/* RST_CTRL2 */
+	[AN7583_XPON_PHY_RST]		= 0,
+	[AN7583_GPON_OLT_RST]		= 1,
+	[AN7583_CPU_TIMER2_RST]		= 2,
+	[AN7583_HSUART_RST]		= 3,
+	[AN7583_UART4_RST]		= 4,
+	[AN7583_UART5_RST]		= 5,
+	[AN7583_I2C2_RST]		= 6,
+	[AN7583_XSI_MAC_RST]		= 7,
+	[AN7583_XSI_PHY_RST]		= 8,
+	[AN7583_NPU_RST]		= 9,
+	[AN7583_TRNG_MSTART_RST]	= 12,
+	[AN7583_DUAL_HSI0_RST]		= 13,
+	[AN7583_DUAL_HSI1_RST]		= 14,
+	[AN7583_DUAL_HSI0_MAC_RST]	= 16,
+	[AN7583_DUAL_HSI1_MAC_RST]	= 17,
+	[AN7583_XPON_XFI_RST]		= 18,
+	[AN7583_WDMA_RST]		= 19,
+	[AN7583_WOE0_RST]		= 20,
+	[AN7583_HSDMA_RST]		= 22,
+	[AN7583_TDMA_RST]		= 24,
+	[AN7583_EMMC_RST]		= 25,
+	[AN7583_SOE_RST]		= 26,
+	[AN7583_XFP_MAC_RST]		= 28,
+	[AN7583_MDIO0]			= 30,
+	[AN7583_MDIO1]			= 31,
+	/* RST_CTRL1 */
+	[AN7583_PCM1_ZSI_ISI_RST]	= RST_NR_PER_BANK + 0,
+	[AN7583_FE_PDMA_RST]		= RST_NR_PER_BANK + 1,
+	[AN7583_FE_QDMA_RST]		= RST_NR_PER_BANK + 2,
+	[AN7583_PCM_SPIWP_RST]		= RST_NR_PER_BANK + 4,
+	[AN7583_CRYPTO_RST]		= RST_NR_PER_BANK + 6,
+	[AN7583_TIMER_RST]		= RST_NR_PER_BANK + 8,
+	[AN7583_PCM1_RST]		= RST_NR_PER_BANK + 11,
+	[AN7583_UART_RST]		= RST_NR_PER_BANK + 12,
+	[AN7583_GPIO_RST]		= RST_NR_PER_BANK + 13,
+	[AN7583_GDMA_RST]		= RST_NR_PER_BANK + 14,
+	[AN7583_I2C_MASTER_RST]		= RST_NR_PER_BANK + 16,
+	[AN7583_PCM2_ZSI_ISI_RST]	= RST_NR_PER_BANK + 17,
+	[AN7583_SFC_RST]		= RST_NR_PER_BANK + 18,
+	[AN7583_UART2_RST]		= RST_NR_PER_BANK + 19,
+	[AN7583_GDMP_RST]		= RST_NR_PER_BANK + 20,
+	[AN7583_FE_RST]			= RST_NR_PER_BANK + 21,
+	[AN7583_USB_HOST_P0_RST]	= RST_NR_PER_BANK + 22,
+	[AN7583_GSW_RST]		= RST_NR_PER_BANK + 23,
+	[AN7583_SFC2_PCM_RST]		= RST_NR_PER_BANK + 25,
+	[AN7583_PCIE0_RST]		= RST_NR_PER_BANK + 26,
+	[AN7583_PCIE1_RST]		= RST_NR_PER_BANK + 27,
+	[AN7583_CPU_TIMER_RST]		= RST_NR_PER_BANK + 28,
+	[AN7583_PCIE_HB_RST]		= RST_NR_PER_BANK + 29,
+	[AN7583_XPON_MAC_RST]		= RST_NR_PER_BANK + 31,
+};
+
 static int en7581_reset_register(struct device *dev, void __iomem *base,
 				 const u16 *rst_map, int nr_resets,
 				 const u16 *rst_reg_ofs);

@@ -862,6 +1057,28 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
 				     en7581_rst_ofs);
 }
 
+static int an7583_clk_hw_init(struct platform_device *pdev,
+			      struct clk_hw_onecell_data *clk_data)
+{
+	struct device *dev = &pdev->dev;
+	struct regmap *map;
+	void __iomem *base;
+
+	map = syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,chip-scu");
+	if (IS_ERR(map))
+		return PTR_ERR(map);
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	en7581_register_clocks(dev, clk_data, map, base);
+
+	return en7581_reset_register(dev, base, an7583_rst_map,
+				     ARRAY_SIZE(an7583_rst_map),
+				     en7581_rst_ofs);
+}
+
 static enum en_hir get_hw_id(void __iomem *np_base)
 {
 	u32 val = FIELD_GET(REG_HIR_MASK, readl(np_base + REG_HIR));

@@ -1006,6 +1223,18 @@ static const struct en_clk_soc_data en7581_data = {
 	.hw_init = en7581_clk_hw_init,
 };
 
+static const struct en_clk_soc_data an7583_data = {
+	.base_clks = an7583_base_clks,
+	/* We increment num_clocks by 1 to account for additional PCIe clock */
+	.num_clocks = ARRAY_SIZE(an7583_base_clks) + 1,
+	.pcie_ops = {
+		.is_enabled = en7581_pci_is_enabled,
+		.enable = en7581_pci_enable,
+		.disable = en7581_pci_disable,
+	},
+	.hw_init = an7583_clk_hw_init,
+};
+
 static const struct en_clk_soc_data en751221_data = {
 	.num_clocks = EN751221_MAX_CLKS,
 	.pcie_ops = {

@@ -1019,6 +1248,7 @@ static const struct en_clk_soc_data en751221_data = {
 static const struct of_device_id of_match_clk_en7523[] = {
 	{ .compatible = "airoha,en7523-scu", .data = &en7523_data },
 	{ .compatible = "airoha,en7581-scu", .data = &en7581_data },
+	{ .compatible = "airoha,an7583-scu", .data = &an7583_data },
 	{ .compatible = "econet,en751221-scu", .data = &en751221_data },
 	{ /* sentinel */ }
 };
Signature · 1 line
2.53.0
AI review
#7 lore raw

Re: [PATCH v5 3/3] clk: en7523: add support for Airoha AN7583 clock

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

Pre-existing issues:
- [High] Clocks registered via clk_hw_register_fixed_rate() and clk_hw_register() are leaked and leave dangling pointers in the Common Clock Framework if probe fails.
- [High] Read-modify-write race condition in en7523_reset_update without a lock.
--

commit bef5b4bfdccbca2ef2af773a13a17e2000ca2bec
Author: Christian Marangi <[email protected]>

clk: en7523: add support for Airoha AN7583 clock

This commit adds support for the Airoha AN7583 clock and reset. It introduces a new SoC that shares register addresses with EN7581 but implements different bits, additional base clocks, and dedicated resets.

Quoted 4 lines
drivers/clk/clk-en7523.c +0 -0
index 087ff4568124f..217d5d5f932d6 100644

[ ... ]

Quoted 10 lines
drivers/clk/clk-en7523.c +6 -0
@@ -1057,6 +1057,28 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
 				     en7581_rst_ofs);
 }
 
+static int an7583_clk_hw_init(struct platform_device *pdev,
+			      struct clk_hw_onecell_data *clk_data)
+{
+	struct device *dev = &pdev->dev;
+	struct regmap *map;
+	void __iomem *base;

drivers/clk/clk-en7523.c static int en7581_clk_hw_init(struct platform_device *pdev, · line 1075

Quoted 10 lines
drivers/clk/clk-en7523.c +10 -0
+
+	map = syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,chip-scu");
+	if (IS_ERR(map))
+		return PTR_ERR(map);
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	en7581_register_clocks(dev, clk_data, map, base);

[Severity: High]
This isn't a bug introduced by this patch, but does calling en7581_register_clocks() here leak memory and leave dangling pointers if the subsequent en7581_reset_register() fails?

en7581_register_clocks() registers clocks using clk_hw_register_fixed_rate() and clk_hw_register() without their devm counterparts, but allocates the inner structures (like struct en_clk_gate) using devm_kzalloc().

If en7581_reset_register() fails, the probe will fail. The devres framework will automatically free the memory allocated by devm_kzalloc(), but the clocks won't be unregistered from the Common Clock Framework, leaving it with dangling pointers and memory leaks for the fixed rate clocks.

Could these be switched to the devm_clk_hw_register_* family of functions?

drivers/clk/clk-en7523.c static int en7581_clk_hw_init(struct platform_device *pdev, · line 1080

Quoted 5 lines
drivers/clk/clk-en7523.c +5 -0
+
+	return en7581_reset_register(dev, base, an7583_rst_map,
+				     ARRAY_SIZE(an7583_rst_map),
+				     en7581_rst_ofs);
+}

[Severity: High]
This is a pre-existing issue, but can concurrent resets trigger a race condition since there is no locking during the reset updates?

en7581_reset_register() assigns en7581_reset_ops, which invokes en7523_reset_update(). That function performs an unlocked read-modify-write:

    val = readl(addr);
    if (assert)
        val |= BIT(id % RST_NR_PER_BANK);
    else
        val &= ~BIT(id % RST_NR_PER_BANK);
    writel(val, addr);

Since multiple independent peripheral drivers (e.g., PCIe, USB, UART) can trigger concurrent reset_control_assert() or reset_control_deassert() calls for different bits within the same register bank, could one CPU overwrite and drop another CPU's concurrent state change?

Could a spinlock be added to serialize access to these shared reset registers?

Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=3