dt-bindings: pinctrl: tegra238: add missing AON pin groups
Subsystems (4)
PATCH 1/2 dt-bindings: pinctrl: tegra238: add missing AON pin groups
Add 24 pin groups, and their matching drive groups, on ports EE, FF, GG and HH to the Tegra238 AON pinmux binding. These groups are present on the AON pin controller, so device trees that mux these pins through it validate against the schema.
--- .../pinctrl/nvidia,tegra238-pinmux-aon.yaml | 26 ++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-)
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml +23 -3
@@ -38,8 +38,16 @@ patternProperties: gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4, dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7, - pwm3_pee0, pwm7_pee1, - # drive groups (ordered PAA, PBB, PCC, PDD, PEE) + pwm3_pee0, pwm7_pee1, soc_gpio49_pee2, + soc_gpio82_pee3, soc_gpio50_pee4, soc_gpio83_pee5, + soc_gpio69_pff0, soc_gpio70_pff1, soc_gpio71_pff2, + soc_gpio72_pff3, soc_gpio73_pff4, soc_gpio74_pff5, + soc_gpio80_pff6, soc_gpio76_pff7, soc_gpio77_pgg0, + soc_gpio84_pgg1, uart2_tx_pgg2, uart2_rx_pgg3, + uart2_rts_pgg4, uart2_cts_pgg5, soc_gpio85_pgg6, + uart5_tx_pgg7, uart5_rx_phh0, uart5_rts_phh1, + uart5_cts_phh2, soc_gpio86_phh3, + # drive groups (ordered PAA, PBB, PCC, PDD, PEE, PFF, PGG, PHH) drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1, drive_vcomp_alert_paa2, drive_pwm1_paa3, drive_batt_oc_paa4, drive_soc_gpio04_paa5,
@@ -53,7 +61,19 @@ patternProperties: drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3, drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5, drive_soc_gpio19_pdd6, drive_pwm2_pdd7, - drive_pwm3_pee0, drive_pwm7_pee1 ] + drive_pwm3_pee0, drive_pwm7_pee1, + drive_soc_gpio49_pee2, drive_soc_gpio50_pee4, + drive_soc_gpio82_pee3, drive_soc_gpio71_pff2, + drive_soc_gpio76_pff7, drive_soc_gpio74_pff5, + drive_soc_gpio86_phh3, drive_soc_gpio72_pff3, + drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6, + drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5, + drive_soc_gpio73_pff4, drive_soc_gpio70_pff1, + drive_soc_gpio85_pgg6, drive_soc_gpio69_pff0, + drive_uart5_tx_pgg7, drive_uart5_rx_phh0, + drive_uart2_tx_pgg2, drive_uart2_rx_pgg3, + drive_uart2_cts_pgg5, drive_uart2_rts_pgg4, + drive_uart5_cts_phh2, drive_uart5_rts_phh1 ] required: - compatible
Signature · 1 line
2.50.1
PATCH 2/2 pinctrl: tegra238: add missing AON pin groups
Add 24 pin groups on ports EE, FF, GG and HH to the AON pin controller group table (tegra238_aon_groups[]). Their pin arrays, drive-group macros and pin descriptors were already defined, but the matching PINGROUP() entries were not present, so these pins could not be muxed or configured through the AON pin controller.
The pin arrays were not referenced, so the build emitted -Wunused-const-variable warnings, and commit 119de2c33d96 ("pinctrl:
tegra238: remove unused entries") removed three of them. Restore those arrays and add the full set of PINGROUP() entries to make the pins usable.
--- drivers/pinctrl/tegra/pinctrl-tegra238.c | 120 +++++++++++++++++++++++ 1 file changed, 120 insertions(+)
drivers/pinctrl/tegra/pinctrl-tegra238.c +120 -0
@@ -1074,6 +1074,102 @@ static const unsigned int pwm7_pee1_pins[] = { TEGRA_PIN_PWM7_PEE1, }; +static const unsigned int soc_gpio49_pee2_pins[] = { +TEGRA_PIN_SOC_GPIO49_PEE2 , +}; + +static const unsigned int soc_gpio82_pee3_pins[] = { +TEGRA_PIN_SOC_GPIO82_PEE3 , +}; + +static const unsigned int soc_gpio50_pee4_pins[] = { +TEGRA_PIN_SOC_GPIO50_PEE4 , +}; + +static const unsigned int soc_gpio83_pee5_pins[] = { +TEGRA_PIN_SOC_GPIO83_PEE5 , +}; + +static const unsigned int soc_gpio69_pff0_pins[] = { +TEGRA_PIN_SOC_GPIO69_PFF0 , +}; + +static const unsigned int soc_gpio70_pff1_pins[] = { +TEGRA_PIN_SOC_GPIO70_PFF1 , +}; + +static const unsigned int soc_gpio71_pff2_pins[] = { +TEGRA_PIN_SOC_GPIO71_PFF2 , +}; + +static const unsigned int soc_gpio72_pff3_pins[] = { +TEGRA_PIN_SOC_GPIO72_PFF3 , +}; + +static const unsigned int soc_gpio73_pff4_pins[] = { +TEGRA_PIN_SOC_GPIO73_PFF4 , +}; + +static const unsigned int soc_gpio74_pff5_pins[] = { +TEGRA_PIN_SOC_GPIO74_PFF5 , +}; + +static const unsigned int soc_gpio80_pff6_pins[] = { +TEGRA_PIN_SOC_GPIO80_PFF6 , +}; + +static const unsigned int soc_gpio76_pff7_pins[] = { +TEGRA_PIN_SOC_GPIO76_PFF7 , +}; + +static const unsigned int soc_gpio77_pgg0_pins[] = { +TEGRA_PIN_SOC_GPIO77_PGG0 , +}; + +static const unsigned int soc_gpio84_pgg1_pins[] = { +TEGRA_PIN_SOC_GPIO84_PGG1 , +}; + +static const unsigned int uart2_tx_pgg2_pins[] = { +TEGRA_PIN_UART2_TX_PGG2 , +}; + +static const unsigned int uart2_rx_pgg3_pins[] = { +TEGRA_PIN_UART2_RX_PGG3 , +}; + +static const unsigned int uart2_rts_pgg4_pins[] = { +TEGRA_PIN_UART2_RTS_PGG4 , +}; + +static const unsigned int uart2_cts_pgg5_pins[] = { +TEGRA_PIN_UART2_CTS_PGG5 , +}; + +static const unsigned int soc_gpio85_pgg6_pins[] = { +TEGRA_PIN_SOC_GPIO85_PGG6 , +}; + +static const unsigned int uart5_tx_pgg7_pins[] = { +TEGRA_PIN_UART5_TX_PGG7 , +}; + +static const unsigned int uart5_rx_phh0_pins[] = { +TEGRA_PIN_UART5_RX_PHH0 , +}; + +static const unsigned int uart5_rts_phh1_pins[] = { +TEGRA_PIN_UART5_RTS_PHH1 , +}; + +static const unsigned int uart5_cts_phh2_pins[] = { +TEGRA_PIN_UART5_CTS_PHH2 , +}; + +static const unsigned int soc_gpio86_phh3_pins[] = { +TEGRA_PIN_SOC_GPIO86_PHH3 , +}; +static const unsigned int sdmmc1_comp_pins[] = {TEGRA_PIN_SDMMC1_COMP , };
@@ -1890,6 +1986,30 @@ static const struct tegra_pingroup tegra238_aon_groups[] = {PINGROUP (dmic1_clk_pdd4,DMIC1_CLK ,RSVD1 ,DMIC5_CLK ,RSVD3 ,0x11d0 ,1 ,Y ,-1 ,7 ,6 ,8 ,-1 ,10 ,12 ),PINGROUP (dmic1_dat_pdd5,DMIC1_DAT ,RSVD1 ,DMIC5_DAT ,RSVD3 ,0x11d8 ,1 ,Y ,-1 ,7 ,6 ,8 ,-1 ,10 ,12 ),PINGROUP (soc_gpio19_pdd6,RSVD0 ,WDT_RESET_OUTB ,RSVD2 ,RSVD3 ,0x10f8 ,1 ,Y ,-1 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio49_pee2,RSVD0 ,RSVD1 ,RSVD2 ,RSVD3 ,0x10c0 ,1 ,Y ,-1 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio50_pee4,RSVD0 ,RSVD1 ,RSVD2 ,RSVD3 ,0x10c8 ,1 ,Y ,-1 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio82_pee3,RSVD0 ,RSVD1 ,RSVD2 ,RSVD3 ,0x10d0 ,1 ,Y ,-1 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio71_pff2,PPC_MODE_1 ,RSVD1 ,RSVD2 ,RSVD3 ,0x10d8 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio76_pff7,RSVD0 ,RSVD1 ,TSC_EDGE_OUT0 ,TSC_EDGE_OUT0A ,0x10e0 ,1 ,Y ,-1 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio74_pff5,PPC_READY ,PPC_I2C_DAT ,RSVD2 ,RSVD3 ,0x10e8 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio86_phh3,RSVD0 ,SPI5_CS1 ,TSC_EDGE_OUT3 ,TSC_EDGE_OUT0D ,0x1100 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio72_pff3,PPC_MODE_2 ,RSVD1 ,RSVD2 ,RSVD3 ,0x1108 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio77_pgg0,RSVD0 ,RSVD1 ,TSC_EDGE_OUT1 ,TSC_EDGE_OUT0B ,0x1110 ,1 ,Y ,-1 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio80_pff6,RSVD0 ,PPC_RST_N ,RSVD2 ,RSVD3 ,0x1118 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio84_pgg1,RSVD0 ,RSVD1 ,TSC_EDGE_OUT2 ,TSC_EDGE_OUT0C ,0x1120 ,1 ,Y ,-1 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio83_pee5,RSVD0 ,RSVD1 ,RSVD2 ,RSVD3 ,0x1128 ,1 ,Y ,-1 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio73_pff4,PPC_CC ,PPC_I2C_CLK ,RSVD2 ,RSVD3 ,0x1130 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio70_pff1,PPC_MODE_0 ,RSVD1 ,RSVD2 ,RSVD3 ,0x1138 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio85_pgg6,RSVD0 ,SPI4_CS1 ,RSVD2 ,RSVD3 ,0x1148 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (soc_gpio69_pff0,PPC_INT_N ,RSVD1 ,RSVD2 ,RSVD3 ,0x1150 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (uart5_tx_pgg7,UARTE_TXD ,SPI5_SCK ,RSVD2 ,RSVD3 ,0x1168 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (uart5_rx_phh0,UARTE_RXD ,SPI5_MISO ,RSVD2 ,RSVD3 ,0x1170 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (uart2_tx_pgg2,UARTB_TXD ,SPI4_SCK ,RSVD2 ,RSVD3 ,0x1178 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (uart2_rx_pgg3,UARTB_RXD ,SPI4_MISO ,RSVD2 ,RSVD3 ,0x1180 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (uart2_cts_pgg5,UARTB_CTS ,SPI4_CS0 ,RSVD2 ,RSVD3 ,0x1188 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (uart2_rts_pgg4,UARTB_RTS ,SPI4_MOSI ,RSVD2 ,RSVD3 ,0x1190 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (uart5_cts_phh2,UARTE_CTS ,SPI5_CS0 ,RSVD2 ,RSVD3 ,0x1198 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), +PINGROUP (uart5_rts_phh1,UARTE_RTS ,SPI5_MOSI ,RSVD2 ,RSVD3 ,0x11a0 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ),PINGROUP (pwm2_pdd7,GP_PWM2 ,LED_BLINK ,RSVD2 ,RSVD3 ,0x11b0 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ),PINGROUP (pwm3_pee0,GP_PWM3 ,RSVD1 ,RSVD2 ,RSVD3 ,0x11b8 ,1 ,Y ,5 ,7 ,6 ,8 ,-1 ,10 ,12 ), PINGROUP(pwm7_pee1, GP_PWM7, RSVD1, RSVD2, RSVD3, 0x11a8, 1, Y, 5, 7, 6, 8, -1, 10, 12),
Signature · 1 line
2.50.1
Linus Walleij
maintainerRe: [PATCH 2/2] pinctrl: tegra238: add missing AON pin groups
Quoted 6 lines · Prathamesh Shete
Add 24 pin groups on ports EE, FF, GG and HH to the AON pin controller group table (tegra238_aon_groups[]). Their pin arrays, drive-group macros and pin descriptors were already defined, but the matching
PINGROUP()entries were not present, so these pins could not be muxed or configured through the AON pin controller.
Quoted 8 lines
The pin arrays were not referenced, so the build emitted -Wunused-const-variable warnings, and commit
119de2c33d96("pinctrl:
tegra238: remove unused entries") removed three of them. Restore those arrays and add the full set ofPINGROUP()entries to make the pins usable.Fixes 25cac7292d49 ("pinctrl: tegra: Add Tegra238 pinmux driver")Signed-off-by Prathamesh Shete <[email protected]>
Patches applied.
Yours,
Linus Walleij
[email protected]
AI reviewThank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] The newly added drive groups are completely unsorted, directly contradicting the explicit ordering…
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The newly added drive groups are completely unsorted, directly contradicting the explicit ordering constraint defined in the YAML comment. --
commit 5b9124b6ede7db6d75188db397f7ab63141b1fc6
Author: Prathamesh Shete <[email protected]>
dt-bindings: pinctrl: tegra238: add missing AON pin groups
Add 24 pin groups, and their matching drive groups, on ports EE, FF, GG and HH to the Tegra238 AON pinmux binding. These groups are present on the AON pin controller, so device trees that mux these pins through it validate against the schema.
Quoted 5 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml +0
-0@@ -38,8 +38,16 @@ patternProperties:
[ ... ]
Quoted 4 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml +1
-1- # drive groups (ordered PAA, PBB, PCC, PDD, PEE) + # drive groups (ordered PAA, PBB, PCC, PDD, PEE, PFF, PGG, PHH) drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1, drive_vcomp_alert_paa2, drive_pwm1_paa3,
[ ... ]
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml patternProperties: · line 68
Quoted 10 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml +5
-1@@ -53,7 +61,19 @@ patternProperties: drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3, drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5, drive_soc_gpio19_pdd6, drive_pwm2_pdd7, - drive_pwm3_pee0, drive_pwm7_pee1 ] + drive_pwm3_pee0, drive_pwm7_pee1, + drive_soc_gpio49_pee2, drive_soc_gpio50_pee4, + drive_soc_gpio82_pee3, drive_soc_gpio71_pff2, + drive_soc_gpio76_pff7, drive_soc_gpio74_pff5, + drive_soc_gpio86_phh3, drive_soc_gpio72_pff3,
[Severity: Low]
Does this order violate the comment preceding the drive groups?
The comment explicitly specifies that the drive groups should be ordered by port (PAA, PBB, PCC, PDD, PEE, PFF, PGG, PHH).
However, the newly added drive groups appear to be jumbled and not ordered by port. For example, drive_soc_gpio86_phh3 appears before drive_soc_gpio72_pff3, and drive_soc_gpio76_pff7 appears before drive_soc_gpio74_pff5.
Should these be sorted sequentially by port to match the documented formatting constraint?
Quoted 11 lines
Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml +8
-0+ drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6, + drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5, + drive_soc_gpio73_pff4, drive_soc_gpio70_pff1, + drive_soc_gpio85_pgg6, drive_soc_gpio69_pff0, + drive_uart5_tx_pgg7, drive_uart5_rx_phh0, + drive_uart2_tx_pgg2, drive_uart2_rx_pgg3, + drive_uart2_cts_pgg5, drive_uart2_rts_pgg4, + drive_uart5_cts_phh2, drive_uart5_rts_phh1 ] required: - compatible
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1
pw-bot: not-applicable
Linus Walleij
maintainerQuoted 7 lines · Prathamesh Shete
Add 24 pin groups, and their matching drive groups, on ports EE, FF, GG and HH to the Tegra238 AON pinmux binding. These groups are present on the AON pin controller, so device trees that mux these pins through it validate against the schema.
Fixes 9323f8a0e12c ("dt-bindings: pinctrl: Document Tegra238 pin controllers")Signed-off-by Prathamesh Shete <[email protected]>
Patch applied.
Yours,
Linus Walleij