Nuvoton NPCM FIU DTS fixes and binding conversion

This series fixes the in-tree NPCM7xx FIU controller nodes so their resources match what the DTS actually describes, and converts the legacy Nuvoton NPCM FIU binding to YAML DT schema.

Patch 1 drops the bogus "memory" entry from reg-names on the NPCM7xx FIU nodes and removes redundant clock-names from those single-clock controllers.

Patch 2 renames the schema to nuvoton,npcm750-fiu.yaml, explains why the direct-mapped flash window is optional, keeps the requested example ordering, and simplifies reg/reg-names to the ordered minItems form.

Changes since version 2:
- Drop redundant FIU clock-names from the NPCM7xx DTSI together with the bogus reg-names cleanup.
- Rename the schema to nuvoton,npcm750-fiu.yaml and keep reg/reg-names immediately after compatible in the example.
- Explain why the direct-mapped flash window is optional and model reg/reg-names as ordered minItems arrays.
- Drop clock-names from the schema to match the driver and updated DTS.

Changes since version 1:
- Drop interrupts property.
- Drop unused label.
- Keep reg as the second property, followed by reg-names.

Tomer Maimon (2):
arm: dts: nuvoton: npcm7xx: Drop bogus FIU reg-names and clock-names
spi: dt-bindings: nuvoton,npcm750-fiu: Convert to DT schema

2.34.1

The NPCM7xx FIU controller nodes only describe the control register block and reference a single unnamed clock. The second "memory" name in reg-names is bogus because there is no matching second reg entry, and the clock-names strings are redundant because spi-npcm-fiu gets the sole clock with devm_clk_get_enabled(dev, NULL) rather than a named lookup.

Drop both so the DTS matches the resources actually consumed by the driver.

---
 arch/arm/boot/dts/nuvoton/nuvoton-common-npcm7xx.dtsi | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

index ab3c3c5713ae..83cd10b47273 100644
@@ -191,9 +191,8 @@ fiu0: spi@fb000000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xfb000000 0x1000>;
-			reg-names = "control", "memory";
+			reg-names = "control";
 			clocks = <&clk NPCM7XX_CLK_SPI0>;
-			clock-names = "clk_spi0";
 			status = "disabled";
 		};
 

@@ -202,9 +201,8 @@ fiu3: spi@c0000000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xc0000000 0x1000>;
-			reg-names = "control", "memory";
+			reg-names = "control";
 			clocks = <&clk NPCM7XX_CLK_SPI3>;
-			clock-names = "clk_spi3";
 			pinctrl-names = "default";
 			pinctrl-0 = <&spi3_pins>;
 			status = "disabled";

@@ -215,9 +213,8 @@ fiux: spi@fb001000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0xfb001000 0x1000>;
-			reg-names = "control", "memory";
+			reg-names = "control";
 			clocks = <&clk NPCM7XX_CLK_SPIX>;
-			clock-names = "clk_spix";
 			status = "disabled";
 		};
 

2.34.1

Convert the Nuvoton NPCM FIU binding to DT schema format.

Document the required control registers and the optional direct- mapped flash window separately, matching the driver behavior when the direct mapping is not described.

---
 .../bindings/spi/nuvoton,npcm-fiu.txt         | 58 ------------
 .../bindings/spi/nuvoton,npcm750-fiu.yaml     | 93 +++++++++++++++++++
 2 files changed, 93 insertions(+), 58 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt
 create mode 100644 Documentation/devicetree/bindings/spi/nuvoton,npcm750-fiu.yaml

deleted file mode 100644
index fb38e96d395f..000000000000
@@ -1,58 +0,0 @@
-* Nuvoton FLASH Interface Unit (FIU) SPI Controller
-
-NPCM FIU supports single, dual and quad communication interface.
-
-The NPCM7XX supports three FIU modules,
-FIU0 and FIUx supports two chip selects,
-FIU3 support four chip select.
-
-The NPCM8XX supports four FIU modules,
-FIU0 and FIUx supports two chip selects,
-FIU1 and FIU3 supports four chip selects.
-
-Required properties:
-  - compatible : "nuvoton,npcm750-fiu" for Poleg NPCM7XX BMC
-			     "nuvoton,npcm845-fiu" for Arbel NPCM8XX BMC
-  - #address-cells : should be 1.
-  - #size-cells : should be 0.
-  - reg : the first contains the register location and length,
-          the second contains the memory mapping address and length
-  - reg-names: Should contain the reg names "control" and "memory"
-  - clocks : phandle of FIU reference clock.
-
-Required properties in case the pins can be muxed:
-  - pinctrl-names : a pinctrl state named "default" must be defined.
-  - pinctrl-0 : phandle referencing pin configuration of the device.
-
-Optional property:
-  - nuvoton,spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD.
-
-Aliases:
-- All the FIU controller nodes should be represented in the aliases node using
-  the following format 'fiu{n}' where n is a unique number for the alias.
-  In the NPCM7XX BMC:
-  		fiu0 represent fiu 0 controller
-  		fiu1 represent fiu 3 controller
-  		fiu2 represent fiu x controller
-
-  In the NPCM8XX BMC:
-  		fiu0 represent fiu 0 controller
-  		fiu1 represent fiu 1 controller
-  		fiu2 represent fiu 3 controller
-  		fiu3 represent fiu x controller
-
-Example:
-fiu3: spi@c00000000 {
-	compatible = "nuvoton,npcm750-fiu";
-	#address-cells = <1>;
-	#size-cells = <0>;
-	reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>;
-	reg-names = "control", "memory";
-	clocks = <&clk NPCM7XX_CLK_AHB>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&spi3_pins>;
-	flash@0 {
-			...
-	};
-};
-

2.34.1

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