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arm64: dts: nuvoton: add NPCM845 SoC and EVB support

PATCH Superseded Tomer Maimon 2 participants 8 messages Jun 10 – Jun 15

Subsystems (2)
Device tree bindings Arm/nuvoton npcm architecture

v4 of 10 Superseded Latest is v10 →

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Tomer Maimon

author maintainer
#0 lore raw

v4 cover arm64: dts: nuvoton: add NPCM845 SoC and EVB support

This series fix warnings and adds device tree support for peripherals on the Nuvoton NPCM845 SoC and its Evaluation Board (EVB).
The first patch fix warning and arrange node order.
The second patch introduces peripheral nodes for Ethernet, MMC, SPI, USB, RNG, ADC, PWM-FAN, I2C, and OP-TEE firmware in the NPCM845 SoC device tree. The third patch enables these peripherals for the NPCM845-EVB, adding MDIO nodes, reserved memory, aliases, and board-specific configurations like PHY modes and SPI flash partitions.

The NPCM8XX device tree tested on NPCM845 evaluation board.

This series depends on:
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/

Addressed comments from:
- Rob Herring: https://patchwork.ozlabs.org/project/openbmc/cover/[email protected]/#3588084

Changes since version 3:
- reomve tmp100.

Changes since version 2:
- Fix dts warning
- Arrange node order by ascending unit address.

Changes since version 1:
- Fix commit message
- Fix dtbs_check warnings.

Tomer Maimon (3):
arm64: dts: nuvoton: npcm845: Reorder timer0 and PECI nodes
arm64: dts: nuvoton: npcm845: Add peripheral nodes
arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 726 +++++++++++++++++-
 .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 413 ++++++++++
 .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |  11 +-
 3 files changed, 1130 insertions(+), 20 deletions(-)
Signature · 1 line
2.34.1
author maintainer
#1 lore raw

PATCH v4 1/3 arm64: dts: nuvoton: npcm845: Reorder timer0 and PECI nodes

Move the timer0 and PECI nodes so the APB children are ordered by ascending unit address. Keep the existing timer0 clock-names property unchanged.

Signed-off-by Tomer Maimon <[email protected]>
---
 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 26 ++++++++++++-------
 1 file changed, 17 insertions(+), 9 deletions(-)
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +17 -9
index c781190b42c5..7976baafb994 100644
@@ -59,15 +59,6 @@ apb {
 			ranges = <0x0 0x0 0xf0000000 0x00300000>,
 				<0xfff00000 0x0 0xfff00000 0x00016000>;
 
-			peci: peci-controller@100000 {
-				compatible = "nuvoton,npcm845-peci";
-				reg = <0x100000 0x1000>;
-				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-				clocks = <&clk NPCM8XX_CLK_APB3>;
-				cmd-timeout-ms = <1000>;
-				status = "disabled";
-			};
-
 			timer0: timer@8000 {
 				compatible = "nuvoton,npcm845-timer";
 				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

@@ -139,6 +130,14 @@ serial6: serial@6000 {
 				status = "disabled";
 			};
 
+			timer0: timer@8000 {
+				compatible = "nuvoton,npcm845-timer";
+				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+				reg = <0x8000 0x1C>;
+				clocks = <&refclk>;
+				clock-names = "refclk";
+			};
+
 			watchdog0: watchdog@801c {
 				compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
 				interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;

@@ -162,6 +161,15 @@ watchdog2: watchdog@a01c {
 				status = "disabled";
 				clocks = <&refclk>;
 			};
+
+			peci: peci-controller@100000 {
+				compatible = "nuvoton,npcm845-peci";
+				reg = <0x100000 0x1000>;
+				interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk NPCM8XX_CLK_APB3>;
+				cmd-timeout-ms = <1000>;
+				status = "disabled";
+			};
 		};
 	};
Signature · 1 line
2.34.1
author maintainer
#2 lore raw

PATCH v4 2/3 arm64: dts: nuvoton: npcm845: Add peripheral nodes

In reply to Tomer Maimon

Extend the NPCM845 SoC DTSI with the peripheral controller nodes needed by the evaluation board and downstream platforms. Add the Ethernet MACs, USB device controllers and PHY, MMC controller, FIU controllers, memory controller, RNG, ADC, PWM/FAN controller, and I2C buses. Also add the OP-TEE firmware node needed to describe these blocks.

Signed-off-by Tomer Maimon <[email protected]>
---
 .../dts/nuvoton/nuvoton-common-npcm8xx.dtsi   | 700 +++++++++++++++++-
 .../boot/dts/nuvoton/nuvoton-npcm845.dtsi     |  11 +-
 2 files changed, 700 insertions(+), 11 deletions(-)
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +691 -9
index 7976baafb994..1e21b2704784 100644
@@ -4,6 +4,7 @@
 #include <dt-bindings/clock/nuvoton,npcm845-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	#address-cells = <2>;

@@ -35,6 +36,11 @@ gic: interrupt-controller@dfff9000 {
 		};
 	};
 
+	udc0_phy: usb-phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+
 	ahb {
 		#address-cells = <2>;
 		#size-cells = <2>;

@@ -51,7 +57,255 @@ clk: rstc: reset-controller@f0801000 {
 			#clock-cells = <1>;
 		};
 
-		apb {
+		gmac1: ethernet@f0804000 {
+			device_type = "network";
+			compatible = "snps,dwmac-3.72a", "snps,dwmac";
+			reg = <0x0 0xf0804000 0x0 0x2000>;
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks	= <&clk NPCM8XX_CLK_AHB>;
+			clock-names = "stmmaceth";
+			pinctrl-names = "default";
+			pinctrl-0 = <&rg2_pins
+					&rg2mdio_pins>;
+			status = "disabled";
+		};
+
+		gmac2: ethernet@f0806000 {
+			device_type = "network";
+			compatible = "snps,dwmac-3.72a", "snps,dwmac";
+			reg = <0x0 0xf0806000 0x0 0x2000>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks	= <&clk NPCM8XX_CLK_AHB>;
+			clock-names = "stmmaceth";
+			pinctrl-names = "default";
+			pinctrl-0 = <&r1_pins
+					&r1err_pins
+					&r1md_pins>;
+			status = "disabled";
+		};
+
+		gmac3: ethernet@f0808000 {
+			device_type = "network";
+			compatible = "snps,dwmac-3.72a", "snps,dwmac";
+			reg = <0x0 0xf0808000 0x0 0x2000>;
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			clocks	= <&clk NPCM8XX_CLK_AHB>;
+			clock-names = "stmmaceth";
+			pinctrl-names = "default";
+			pinctrl-0 = <&r2_pins
+					&r2err_pins
+					&r2md_pins>;
+			status = "disabled";
+		};
+
+		mc: memory-controller@f0824000 {
+			compatible = "nuvoton,npcm845-memory-controller";
+			reg = <0x0 0xf0824000 0x0 0x1000>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		udc0: usb@f0830000 {
+			compatible = "nuvoton,npcm845-udc", "nuvoton,npcm750-udc";
+			reg = <0x0 0xf0830000 0x0 0x1000
+			       0x0 0xfffeb000 0x0 0x800>;
+			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc1: usb@f0831000 {
+			compatible = "nuvoton,npcm845-udc", "nuvoton,npcm750-udc";
+			reg = <0x0 0xf0831000 0x0 0x1000
+			       0x0 0xfffeb800 0x0 0x800>;
+			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc2: usb@f0832000 {
+			compatible = "nuvoton,npcm845-udc", "nuvoton,npcm750-udc";
+			reg = <0x0 0xf0832000 0x0 0x1000
+			       0x0 0xfffec000 0x0 0x800>;
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc3: usb@f0833000 {
+			compatible = "nuvoton,npcm845-udc", "nuvoton,npcm750-udc";
+			reg = <0x0 0xf0833000 0x0 0x1000
+			       0x0 0xfffec800 0x0 0x800>;
+			interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc4: usb@f0834000 {
+			compatible = "nuvoton,npcm845-udc", "nuvoton,npcm750-udc";
+			reg = <0x0 0xf0834000 0x0 0x1000
+			       0x0 0xfffed000 0x0 0x800>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc5: usb@f0835000 {
+			compatible = "nuvoton,npcm845-udc", "nuvoton,npcm750-udc";
+			reg = <0x0 0xf0835000 0x0 0x1000
+			       0x0 0xfffed800 0x0 0x800>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc6: usb@f0836000 {
+			compatible = "nuvoton,npcm845-udc", "nuvoton,npcm750-udc";
+			reg = <0x0 0xf0836000 0x0 0x1000
+			       0x0 0xfffee000 0x0 0x800>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc7: usb@f0837000 {
+			compatible = "nuvoton,npcm845-udc", "nuvoton,npcm750-udc";
+			reg = <0x0 0xf0837000 0x0 0x1000
+			       0x0 0xfffee800 0x0 0x800>;
+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc8: usb@f0838000 {
+			compatible = "nuvoton,npcm845-udc", "nuvoton,npcm750-udc";
+			reg = <0x0 0xf0838000 0x0 0x1000
+			       0x0 0xfffef000 0x0 0x800>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			nuvoton,sysgcr = <&gcr 0x9C 0xC000 0xC000>;
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		udc9: usb@f0839000 {
+			compatible = "nuvoton,npcm845-udc", "nuvoton,npcm750-udc";
+			reg = <0x0 0xf0839000 0x0 0x1000
+			       0x0 0xfffef800 0x0 0x800>;
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			nuvoton,sysgcr = <&gcr 0x9C 0x3000 0x3000>;
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+
+		sdhci: mmc@f0842000 {
+			compatible = "nuvoton,npcm845-sdhci";
+			reg = <0x0 0xf0842000 0x0 0x100>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_AHB>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&mmc8_pins
+				     &mmc_pins>;
+			status = "disabled";
+		};
+
+		fiu0: spi@fb000000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xfb000000 0x0 0x1000>;
+			reg-names = "control";
+			clocks =  <&clk NPCM8XX_CLK_SPI0>;
+			status = "disabled";
+		};
+
+		fiu1: spi@fb002000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xfb002000 0x0 0x1000>;
+			reg-names = "control";
+			clocks =  <&clk NPCM8XX_CLK_SPI1>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi1_pins>;
+			status = "disabled";
+		};
+
+		fiu3: spi@c0000000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xc0000000 0x0 0x1000>;
+			reg-names = "control";
+			clocks =  <&clk NPCM8XX_CLK_SPI3>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&spi3_pins>;
+			status = "disabled";
+		};
+
+		fiux: spi@fb001000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xfb001000 0x0 0x1000>,
+			<0x0 0xf8000000 0x0 0x2000000>;
+			reg-names = "control", "memory";
+			clocks =  <&clk NPCM8XX_CLK_SPIX>;
+			status = "disabled";
+		};
+
+		apb: bus@f0000000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "simple-bus";

@@ -59,14 +313,6 @@ apb {
 			ranges = <0x0 0x0 0xf0000000 0x00300000>,
 				<0xfff00000 0x0 0xfff00000 0x00016000>;
 
-			timer0: timer@8000 {
-				compatible = "nuvoton,npcm845-timer";
-				interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
-				reg = <0x8000 0x1C>;
-				clocks = <&refclk>;
-				clock-names = "refclk";
-			};
-
 			serial0: serial@0 {
 				compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
 				reg = <0x0 0x1000>;

@@ -170,6 +416,442 @@ peci: peci-controller@100000 {
 				cmd-timeout-ms = <1000>;
 				status = "disabled";
 			};
+
+			rng: rng@b000 {
+				compatible = "nuvoton,npcm845-rng";
+				reg = <0xb000 0x8>;
+				status = "disabled";
+			};
+
+			adc: adc@c000 {
+				compatible = "nuvoton,npcm845-adc";
+				reg = <0xC000 0x8>;
+				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk NPCM8XX_CLK_ADC>;
+				resets = <&rstc 0x20 27>;
+				status = "disabled";
+			};
+
+			i2c0: i2c@80000 {
+				reg = <0x80000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb0_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@81000 {
+				reg = <0x81000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb1_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c2: i2c@82000 {
+				reg = <0x82000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb2_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@83000 {
+				reg = <0x83000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb3_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c4: i2c@84000 {
+				reg = <0x84000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb4_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c5: i2c@85000 {
+				reg = <0x85000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb5_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c6: i2c@86000 {
+				reg = <0x86000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb6_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c7: i2c@87000 {
+				reg = <0x87000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb7_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c8: i2c@88000 {
+				reg = <0x88000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb8_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c9: i2c@89000 {
+				reg = <0x89000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb9_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c10: i2c@8a000 {
+				reg = <0x8a000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb10_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c11: i2c@8b000 {
+				reg = <0x8b000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb11_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c12: i2c@8c000 {
+				reg = <0x8c000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb12_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c13: i2c@8d000 {
+				reg = <0x8d000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb13_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c14: i2c@8e000 {
+				reg = <0x8e000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb14_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c15: i2c@8f000 {
+				reg = <0x8f000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb15_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c16: i2c@fff00000 {
+				reg = <0xfff00000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb16_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c17: i2c@fff01000 {
+				reg = <0xfff01000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb17_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c18: i2c@fff02000 {
+				reg = <0xfff02000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb18_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c19: i2c@fff03000 {
+				reg = <0xfff03000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb19_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c20: i2c@fff04000 {
+				reg = <0xfff04000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb20_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c21: i2c@fff05000 {
+				reg = <0xfff05000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb21_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c22: i2c@fff06000 {
+				reg = <0xfff06000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb22_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c23: i2c@fff07000 {
+				reg = <0xfff07000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&smb23_pins>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c24: i2c@fff08000 {
+				reg = <0xfff08000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c25: i2c@fff09000 {
+				reg = <0xfff09000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			i2c26: i2c@fff0a000 {
+				reg = <0xfff0a000 0x1000>;
+				compatible = "nuvoton,npcm845-i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				clocks =  <&clk NPCM8XX_CLK_APB2>;
+				clock-frequency = <100000>;
+				interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+				nuvoton,sys-mgr = <&gcr>;
+				status = "disabled";
+			};
+
+			pwm_fan:pwm-fan-controller@103000 {
+				compatible = "nuvoton,npcm845-pwm-fan";
+				reg = <0x103000 0x3000>,
+					<0x180000 0x8000>;
+				reg-names = "pwm", "fan";
+				clocks =  <&clk NPCM8XX_CLK_APB3>,
+					<&clk NPCM8XX_CLK_APB4>;
+				clock-names = "pwm","fan";
+				interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+						<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pwm0_pins &pwm1_pins
+						&pwm2_pins &pwm3_pins
+						&pwm4_pins &pwm5_pins
+						&pwm6_pins &pwm7_pins
+						&pwm8_pins &pwm9_pins
+						&pwm10_pins &pwm11_pins
+						&fanin0_pins &fanin1_pins
+						&fanin2_pins &fanin3_pins
+						&fanin4_pins &fanin5_pins
+						&fanin6_pins &fanin7_pins
+						&fanin8_pins &fanin9_pins
+						&fanin10_pins &fanin11_pins
+						&fanin12_pins &fanin13_pins
+						&fanin14_pins &fanin15_pins>;
+				status = "disabled";
+			};
+
+			pspi: spi@201000 {
+				compatible = "nuvoton,npcm845-pspi";
+				reg = <0x201000 0x1000>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pspi_pins>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+				clocks =  <&clk NPCM8XX_CLK_APB5>;
+				clock-names = "clk_apb5";
+				resets = <&rstc 0x24 23>;
+				status = "disabled";
+			};
+
 		};
 	};
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845.dtsi +9 -2
index 8239d9a9f0d2..21dea323612d 100644
@@ -64,8 +64,8 @@ arm-pmu {
 	};
 
 	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
+		compatible      = "arm,psci-1.0";
+		method          = "smc";
 	};
 
 	timer {

@@ -75,4 +75,11 @@ timer {
 			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 	};
+
+	firmware {
+		optee {
+			compatible = "linaro,optee-tz";
+			method = "smc";
+		};
+	};
 };
Signature · 1 line
2.34.1
AI review
#3 lore raw

Re: [PATCH v4 2/3] arm64: dts: nuvoton: npcm845: Add peripheral nodes

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [Low] DTC Warning (unit_address_vs_reg): The `apb` node includes a unit address but lacks a `reg`…

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] DTC Warning (unit_address_vs_reg): The apb node includes a unit address but lacks a reg property.
- [Low] DT Binding Schema Violation: nuvoton,sysgcr property is undocumented and forbidden by the ChipIdea USB2 schema. --

commit b1b96db36d76cd5dd1f935613798ed29aade275d
Author: Tomer Maimon <[email protected]>

arm64: dts: nuvoton: npcm845: Add peripheral nodes

Extend the NPCM845 SoC DTSI with the peripheral controller nodes needed by the evaluation board and downstream platforms. Add the Ethernet MACs, USB device controllers and PHY, MMC controller, FIU controllers, memory controller, RNG, ADC, PWM/FAN controller, and I2C buses. Also add the OP-TEE firmware node needed to describe these blocks.

Quoted 4 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +0 -0
index 7976baafb9942..1e21b2704784f 100644

[ ... ]

Quoted 6 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +1 -1
@@ -51,7 +57,255 @@ clk: rstc: reset-controller@f0801000 {
 			#clock-cells = <1>;
 		};
 
-		apb {
+		gmac1: ethernet@f0804000 {

[ ... ]

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 230

Quoted 9 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +9 -0
+		udc8: usb@f0838000 {
+			compatible = "nuvoton,npcm845-udc", "nuvoton,npcm750-udc";
+			reg = <0x0 0xf0838000 0x0 0x1000
+			       0x0 0xfffef000 0x0 0x800>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			nuvoton,sysgcr = <&gcr 0x9C 0xC000 0xC000>;

[Severity: Low]
Does this undocumented nuvoton,sysgcr property cause a dtbs_check warning?

The USB Device Controllers bind to "nuvoton,npcm750-udc", which is evaluated against Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml. This schema specifies unevaluatedProperties: false but does not document nuvoton,sysgcr internally or in any dependencies.

Quoted 5 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +5 -0
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 245

Quoted 10 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +10 -0
+
+		udc9: usb@f0839000 {
+			compatible = "nuvoton,npcm845-udc", "nuvoton,npcm750-udc";
+			reg = <0x0 0xf0839000 0x0 0x1000
+			       0x0 0xfffef800 0x0 0x800>;
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&clk NPCM8XX_CLK_SU>;
+			clock-names = "clk_usb_bridge";
+
+			nuvoton,sysgcr = <&gcr 0x9C 0x3000 0x3000>;

[Severity: Low]
Is this the same undocumented property issue as seen above in udc8?

Quoted 6 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +6 -0
+			phys = <&udc0_phy>;
+			phy_type = "utmi_wide";
+			dr_mode = "peripheral";
+			status = "disabled";
+		};
+

[ ... ]

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 308

Quoted 12 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +12 -0
+		fiux: spi@fb001000 {
+			compatible = "nuvoton,npcm845-fiu";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0xfb001000 0x0 0x1000>,
+			<0x0 0xf8000000 0x0 0x2000000>;
+			reg-names = "control", "memory";
+			clocks =  <&clk NPCM8XX_CLK_SPIX>;
+			status = "disabled";
+		};
+
+		apb: bus@f0000000 {

[Severity: Low]
Will changing this node name to include the @f0000000 unit address trigger a unit_address_vs_reg DTC warning?

According to the Devicetree specification, if a node name includes a unit-address, the node must also have a reg property where the first address matches the unit-address. Because the apb node defines ranges but lacks a reg property, this might introduce build noise.

Quoted 6 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +0 -0
 			#address-cells = <1>;
 			#size-cells = <1>;
 			compatible = "simple-bus";

@@ -59,14 +313,6 @@ apb {
 			ranges = <0x0 0x0 0xf0000000 0x00300000>,
 				<0xfff00000 0x0 0xfff00000 0x00016000>;
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
author maintainer
#4 lore raw

Re: [PATCH v4 2/3] arm64: dts: nuvoton: npcm845: Add peripheral nodes

Hi,

Quoted 39 lines · On Wed, 10 Jun 2026 at 19:20, <[email protected]> wrote:

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Low] DTC Warning (unit_address_vs_reg): The apb node includes a unit address but lacks a reg property.
- [Low] DT Binding Schema Violation: nuvoton,sysgcr property is undocumented and forbidden by the ChipIdea USB2 schema. --

commit b1b96db36d76cd5dd1f935613798ed29aade275d
Author: Tomer Maimon <[email protected]>

arm64: dts: nuvoton: npcm845: Add peripheral nodes

Extend the NPCM845 SoC DTSI with the peripheral controller nodes needed by the evaluation board and downstream platforms. Add the Ethernet MACs, USB device controllers and PHY, MMC controller, FIU controllers, memory controller, RNG, ADC, PWM/FAN controller, and I2C buses. Also add the OP-TEE firmware node needed to describe these blocks.

Quoted 4 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +0 -0
index 7976baafb9942..1e21b2704784f 100644

[ ... ]

Quoted 6 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +1 -1
@@ -51,7 +57,255 @@ clk: rstc: reset-controller@f0801000 {
                      #clock-cells = <1>;
              };
 
-             apb {
+             gmac1: ethernet@f0804000 {

[ ... ]

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 230

Quoted 9 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +9 -0
+             udc8: usb@f0838000 {
+                     compatible = "nuvoton,npcm845-udc", "nuvoton,npcm750-udc";
+                     reg = <0x0 0xf0838000 0x0 0x1000
+                            0x0 0xfffef000 0x0 0x800>;
+                     interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+                     clocks = <&clk NPCM8XX_CLK_SU>;
+                     clock-names = "clk_usb_bridge";
+
+                     nuvoton,sysgcr = <&gcr 0x9C 0xC000 0xC000>;
Quoted 7 lines

[Severity: Low]
Does this undocumented nuvoton,sysgcr property cause a dtbs_check warning?

The USB Device Controllers bind to "nuvoton,npcm750-udc", which is evaluated against Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml. This schema specifies unevaluatedProperties: false but does not document nuvoton,sysgcr internally or in any dependencies.

will be removed at V5

Quoted 11 lines
Quoted 11 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +10 -0
+                     phys = <&udc0_phy>;
+                     phy_type = "utmi_wide";
+                     dr_mode = "peripheral";
+                     status = "disabled";
+             };
+
+             udc9: usb@f0839000 {
+                     compatible = "nuvoton,npcm845-udc", "nuvoton,npcm750-udc";
+                     reg = <0x0 0xf0839000 0x0 0x1000
+                            0x0 0xfffef800 0x0 0x800>;
Quoted 8 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 245

Quoted 5 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +5 -0
+                     interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+                     clocks = <&clk NPCM8XX_CLK_SU>;
+                     clock-names = "clk_usb_bridge";
+
+                     nuvoton,sysgcr = <&gcr 0x9C 0x3000 0x3000>;

[Severity: Low]
Is this the same undocumented property issue as seen above in udc8?

will be removed at V5

Quoted 21 lines
Quoted 7 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +6 -0
+                     phys = <&udc0_phy>;
+                     phy_type = "utmi_wide";
+                     dr_mode = "peripheral";
+                     status = "disabled";
+             };
+

[ ... ]

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi clk: rstc: reset-controller@f0801000 { · line 308

Quoted 12 lines
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +12 -0
+             fiux: spi@fb001000 {
+                     compatible = "nuvoton,npcm845-fiu";
+                     #address-cells = <1>;
+                     #size-cells = <0>;
+                     reg = <0x0 0xfb001000 0x0 0x1000>,
+                     <0x0 0xf8000000 0x0 0x2000000>;
+                     reg-names = "control", "memory";
+                     clocks =  <&clk NPCM8XX_CLK_SPIX>;
+                     status = "disabled";
+             };
+
+             apb: bus@f0000000 {
Quoted 8 lines

[Severity: Low]
Will changing this node name to include the @f0000000 unit address trigger a unit_address_vs_reg DTC warning?

According to the Devicetree specification, if a node name includes a unit-address, the node must also have a reg property where the first address matches the unit-address. Because the apb node defines ranges but lacks a reg property, this might introduce build noise.

would be back to apb in V5

Quoted 10 lines

arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi apb { · line 314

Quoted 7 lines
                      #address-cells = <1>;
                      #size-cells = <1>;
                      compatible = "simple-bus";
arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi +0 -0
@@ -59,14 +313,6 @@ apb {
                      ranges = <0x0 0x0 0xf0000000 0x00300000>,
                              <0xfff00000 0x0 0xfff00000 0x00016000>;

--
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2

Thanks,

Tomer

author maintainer
#5 lore raw

PATCH v4 3/3 arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

In reply to Tomer Maimon

Enable peripheral support for the NPCM845 evaluation board by wiring up the SoC controller nodes to the board design. Add board aliases, GPIO-backed MDIO buses for the external PHYs, a reserved-memory region for TIP firmware, and flash partitions for the FIU boot flash. Enable the Ethernet MACs, MMC controller, FIU controllers, USB device controllers, ADC, RNG, PWM/FAN controller, I2C buses, and PECI interface with the board-specific pinctrl and PHY connections they require.

Signed-off-by Tomer Maimon <[email protected]>
---
 .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts  | 413 ++++++++++++++++++
 1 file changed, 413 insertions(+)
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +413 -0
index 5edf5d13342d..ea92888d9b9e 100644
@@ -10,6 +10,42 @@ / {
 
 	aliases {
 		serial0 = &serial0;
+		ethernet1 = &gmac1;
+		ethernet2 = &gmac2;
+		ethernet3 = &gmac3;
+		mdio-gpio0 = &mdio0;
+		mdio-gpio1 = &mdio1;
+		fiu0 = &fiu0;
+		fiu1 = &fiu3;
+		fiu2 = &fiux;
+		fiu3 = &fiu1;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		i2c2 = &i2c2;
+		i2c3 = &i2c3;
+		i2c4 = &i2c4;
+		i2c5 = &i2c5;
+		i2c6 = &i2c6;
+		i2c7 = &i2c7;
+		i2c8 = &i2c8;
+		i2c9 = &i2c9;
+		i2c10 = &i2c10;
+		i2c11 = &i2c11;
+		i2c12 = &i2c12;
+		i2c13 = &i2c13;
+		i2c14 = &i2c14;
+		i2c15 = &i2c15;
+		i2c16 = &i2c16;
+		i2c17 = &i2c17;
+		i2c18 = &i2c18;
+		i2c19 = &i2c19;
+		i2c20 = &i2c20;
+		i2c21 = &i2c21;
+		i2c22 = &i2c22;
+		i2c23 = &i2c23;
+		i2c24 = &i2c24;
+		i2c25 = &i2c25;
+		i2c26 = &i2c26;
 	};
 
 	chosen {

@@ -26,12 +62,389 @@ refclk: refclk-25mhz {
 		clock-frequency = <25000000>;
 		#clock-cells = <0>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		tip_reserved: tip@0 {
+			reg = <0x0 0x0 0x0 0x6200000>;
+		};
+	};
+
+	mdio0: mdio-0 {
+		compatible = "virtual,mdio-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>,
+			<&gpio1 26 GPIO_ACTIVE_HIGH>;
+
+		phy0: ethernet-phy@0 {
+			reg = <0>;
+		};
+	};
+
+	mdio1: mdio-1 {
+		compatible = "virtual,mdio-gpio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>,
+			<&gpio2 28 GPIO_ACTIVE_HIGH>;
+
+		phy1: ethernet-phy@0 {
+			reg = <0>;
+		};
+	};
+};
+
+&gmac1 {
+	phy-mode = "rgmii-id";
+	snps,eee-force-disable;
+	status = "okay";
+};
+
+&gmac2 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&r1_pins
+			&r1oen_pins>;
+	phy-handle = <&phy0>;
+	status = "okay";
+};
+
+&gmac3 {
+	phy-mode = "rmii";
+	pinctrl-names = "default";
+	pinctrl-0 = <&r2_pins
+			&r2oen_pins>;
+	phy-handle = <&phy1>;
+	status = "okay";
 };
 
 &serial0 {
 	status = "okay";
 };
 
+&fiu0 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			bmc@0 {
+				label = "bmc";
+				reg = <0x00000000 0x04000000>;
+			};
+			u-boot@0 {
+				label = "u-boot";
+				reg = <0x00000000 0x007C0000>;
+			};
+			u-boot-env@7c0000 {
+				label = "u-boot-env";
+				reg = <0x007C0000 0x00040000>;
+			};
+			kernel@800000 {
+				label = "kernel";
+				reg = <0x00800000 0x00800000>;
+			};
+			rofs@1000000 {
+				label = "rofs";
+				reg = <0x01000000 0x02C00000>;
+			};
+			rwfs@3c00000 {
+				label = "rwfs";
+				reg = <0x03C00000 0x00400000>;
+			};
+		};
+	};
+};
+
+&fiu1 {
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		spi-rx-bus-width = <2>;
+		spi-tx-bus-width = <2>;
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			partition@0 {
+				label = "spi1-system1";
+				reg = <0x0 0x0>;
+			};
+		};
+	};
+};
+
+&fiu3 {
+	pinctrl-0 = <&spi3_pins>, <&spi3quad_pins>;
+	status = "okay";
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		spi-rx-bus-width = <1>;
+		reg = <0>;
+		spi-max-frequency = <5000000>;
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			partition@0 {
+				label = "spi3-system1";
+				reg = <0x0 0x0>;
+			};
+		};
+	};
+};
+
+&fiux {
+	spix-mode;
+};
+
+&sdhci {
+	status = "okay";
+};
+
+&udc0 {
+	status = "okay";
+};
+
+&udc1 {
+	status = "okay";
+};
+
+&udc2 {
+	status = "okay";
+};
+
+&udc3 {
+	status = "okay";
+};
+
+&udc4 {
+	status = "okay";
+};
+
+&udc5 {
+	status = "okay";
+};
+
+&udc6 {
+	status = "okay";
+};
+
+&udc7 {
+	status = "okay";
+};
+
+&mc {
+	status = "okay";
+};
+
+&peci {
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
+
+&adc {
+	#io-channel-cells = <1>;
+	status = "okay";
+};
+
 &watchdog1 {
 	status = "okay";
 };
+
+&pwm_fan {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0_pins &pwm1_pins
+		&pwm2_pins &pwm3_pins
+		&pwm4_pins &pwm5_pins
+		&pwm6_pins &pwm7_pins
+		&fanin0_pins &fanin1_pins
+		&fanin2_pins &fanin3_pins
+		&fanin4_pins &fanin5_pins
+		&fanin6_pins &fanin7_pins>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	fan@0 {
+		reg = <0x00>;
+		fan-tach-ch = <0x0 0x1>;
+		cooling-levels = <127 255>;
+	};
+	fan@1 {
+		reg = <0x01>;
+		fan-tach-ch = <0x2 0x3>;
+		cooling-levels = <127 255>;
+	};
+	fan@2 {
+		reg = <0x02>;
+		fan-tach-ch = <0x4 0x5>;
+		cooling-levels = <127 255>;
+	};
+	fan@3 {
+		reg = <0x03>;
+		fan-tach-ch = <0x6 0x7>;
+		cooling-levels = <127 255>;
+	};
+	fan@4 {
+		reg = <0x04>;
+		fan-tach-ch = <0x8 0x9>;
+		cooling-levels = <127 255>;
+	};
+	fan@5 {
+		reg = <0x05>;
+		fan-tach-ch = <0xa 0xb>;
+		cooling-levels = <127 255>;
+	};
+	fan@6 {
+		reg = <0x06>;
+		fan-tach-ch = <0xc 0xd>;
+		cooling-levels = <127 255>;
+	};
+	fan@7 {
+		reg = <0x07>;
+		fan-tach-ch = <0xe 0xf>;
+		cooling-levels = <127 255>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	eeprom@50 {
+		compatible = "atmel,24c256";
+		reg = <0x50>;
+	};
+};
+
+&i2c2 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	ipmb@10 {
+		compatible = "ipmb-dev";
+		reg = <0x10>;
+		i2c-protocol;
+	};
+};
+
+&i2c3 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	ipmb@11 {
+		compatible = "ipmb-dev";
+		reg = <0x11>;
+		i2c-protocol;
+	};
+};
+
+&i2c4 {
+	status = "okay";
+};
+
+&i2c5 {
+	status = "okay";
+};
+
+&i2c6 {
+	status = "okay";
+};
+
+&i2c7 {
+	status = "okay";
+};
+
+&i2c8 {
+	status = "okay";
+};
+
+&i2c9 {
+	status = "okay";
+};
+
+&i2c10 {
+	status = "okay";
+};
+
+&i2c11 {
+	status = "okay";
+};
+
+&i2c12 {
+	status = "okay";
+};
+
+&i2c13 {
+	status = "okay";
+};
+
+&i2c14 {
+	status = "okay";
+};
+
+&i2c15 {
+	status = "okay";
+};
+
+&i2c16 {
+	status = "okay";
+};
+
+&i2c17 {
+	status = "okay";
+};
+
+&i2c18 {
+	status = "okay";
+};
+
+&i2c19 {
+	status = "okay";
+};
+
+&i2c20 {
+	status = "okay";
+};
+
+&i2c21 {
+	status = "okay";
+};
+
+&i2c22 {
+	status = "okay";
+};
+
+&i2c23 {
+	status = "okay";
+};
+
+&i2c24 {
+	status = "okay";
+};
+
+&i2c25 {
+	status = "okay";
+};
+
+&i2c26 {
+	status = "okay";
+};
Signature · 1 line
2.34.1
AI review
#6 lore raw

Re: [PATCH v4 3/3] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider: - [High] Missing `/bits/ 8` for `fan-tach-ch` and `cooling-levels` causes incorrect 32-bit integer array…

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Missing /bits/ 8 for fan-tach-ch and cooling-levels causes incorrect 32-bit integer array emission, corrupting the thermal fan driver state.
- [High] The tip_reserved memory node lacks the no-map directive, causing speculative external aborts.
- [Medium] Incorrect Device Tree property name spix-mode prevents the FIU controller from enabling SPIX mode.
--

commit 011b4946d76e73a81f86b002033d53a6d052bd40
Author: Tomer Maimon <[email protected]>

arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

Enable peripheral support for the NPCM845 evaluation board by wiring up the SoC controller nodes to the board design.

Quoted 4 lines
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +0 -0
index 5edf5d13342da..ea92888d9b9e2 100644

[ ... ]

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts refclk: refclk-25mhz { · line 72

Quoted 12 lines
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +8 -0
@@ -26,12 +62,389 @@ refclk: refclk-25mhz {
 		clock-frequency = <25000000>;
 		#clock-cells = <0>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		tip_reserved: tip@0 {
+			reg = <0x0 0x0 0x0 0x6200000>;

[Severity: High]
Does this reserved memory region need the no-map directive?

Without no-map, the kernel establishes a direct, cacheable linear mapping over this region. Since this block is isolated by hardware firewalls for the Trusted Information Processing firmware, could speculative execution or prefetching by the CPU into this linear mapping trigger fatal synchronous external aborts or SErrors?

Quoted 2 lines
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +2 -0
+		};
+	};

[ ... ]

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts refclk: refclk-25mhz { · line 209

Quoted 2 lines

+&fiux {

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +1 -0
+	spix-mode;

[Severity: Medium]
Is this property missing the vendor prefix?

The SPI driver for the NPCM FIU (drivers/spi/spi-npcm-fiu.c) appears to check specifically for the "nuvoton,spix-mode" property. If it is only named "spix-mode" here, will the driver fail to detect it and silently fall back to standard mode?

Quoted 1 line

+};

[ ... ]

Quoted 7 lines

+&pwm_fan {

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +6 -0
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pwm0_pins &pwm1_pins
+		&pwm2_pins &pwm3_pins
+		&pwm4_pins &pwm5_pins
+		&pwm6_pins &pwm7_pins

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts refclk: refclk-25mhz { · line 285

Quoted 10 lines
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +10 -0
+		&fanin0_pins &fanin1_pins
+		&fanin2_pins &fanin3_pins
+		&fanin4_pins &fanin5_pins
+		&fanin6_pins &fanin7_pins>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	fan@0 {
+		reg = <0x00>;
+		fan-tach-ch = <0x0 0x1>;
+		cooling-levels = <127 255>;

[Severity: High]
Should these arrays be explicitly sized using /bits/ 8?

The Device Tree compiler natively emits 32-bit big-endian integers for this syntax. However, if the driver (npcm750-pwm-fan.c) explicitly reads both properties using of_property_read_u8_array(), an 8-byte payload like <127 255> would be read as 8 individual u8 elements:
0, 0, 0, 127, 0, 0, 0, 255.

Does this result in registering intermediate thermal cooling states with a 0 duty cycle, inadvertently turning the fan off during active cooling requests?

Quoted 1 line
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +1 -0
+	};
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=3
author maintainer
#7 lore raw

Re: [PATCH v4 3/3] arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

Hi

Quoted 22 lines · On Wed, 10 Jun 2026 at 19:23, <[email protected]> wrote:

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Missing /bits/ 8 for fan-tach-ch and cooling-levels causes incorrect 32-bit integer array emission, corrupting the thermal fan driver state.
- [High] The tip_reserved memory node lacks the no-map directive, causing speculative external aborts.
- [Medium] Incorrect Device Tree property name spix-mode prevents the FIU controller from enabling SPIX mode.
--

commit 011b4946d76e73a81f86b002033d53a6d052bd40
Author: Tomer Maimon <[email protected]>

arm64: dts: nuvoton: npcm845-evb: Add peripheral nodes

Enable peripheral support for the NPCM845 evaluation board by wiring up the SoC controller nodes to the board design.

Quoted 4 lines
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +0 -0
index 5edf5d13342da..ea92888d9b9e2 100644

[ ... ]

Quoted 15 lines

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts refclk: refclk-25mhz { · line 72

Quoted 12 lines
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +8 -0
@@ -26,12 +62,389 @@ refclk: refclk-25mhz {
              clock-frequency = <25000000>;
              #clock-cells = <0>;
      };
+
+     reserved-memory {
+             #address-cells = <2>;
+             #size-cells = <2>;
+             ranges;
+
+             tip_reserved: tip@0 {
+                     reg = <0x0 0x0 0x0 0x6200000>;

[Severity: High]
Does this reserved memory region need the no-map directive?

No, the kernel shouldn't use this memory

Quoted 10 lines

Without no-map, the kernel establishes a direct, cacheable linear mapping over this region. Since this block is isolated by hardware firewalls for the Trusted Information Processing firmware, could speculative execution or prefetching by the CPU into this linear mapping trigger fatal synchronous external aborts or SErrors?

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts refclk: refclk-25mhz { · line 74

Quoted 2 lines
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +2 -0
+             };
+     };
Quoted 7 lines

[ ... ]

Quoted 2 lines

+&fiux {
+ spix-mode;

[Severity: Medium]
Is this property missing the vendor prefix?

Would be changed in V5

Quoted 28 lines

The SPI driver for the NPCM FIU (drivers/spi/spi-npcm-fiu.c) appears to check specifically for the "nuvoton,spix-mode" property. If it is only named "spix-mode" here, will the driver fail to detect it and silently fall back to standard mode?

Quoted 1 line

+};

[ ... ]

Quoted 7 lines

+&pwm_fan {

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +6 -0
+     status = "okay";
+     pinctrl-names = "default";
+     pinctrl-0 = <&pwm0_pins &pwm1_pins
+             &pwm2_pins &pwm3_pins
+             &pwm4_pins &pwm5_pins
+             &pwm6_pins &pwm7_pins

arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts refclk: refclk-25mhz { · line 285

Quoted 10 lines
arch/arm64/boot/dts/nuvoton/nuvoton-npcm845-evb.dts +10 -0
+             &fanin0_pins &fanin1_pins
+             &fanin2_pins &fanin3_pins
+             &fanin4_pins &fanin5_pins
+             &fanin6_pins &fanin7_pins>;
+     #address-cells = <1>;
+     #size-cells = <0>;
+     fan@0 {
+             reg = <0x00>;
+             fan-tach-ch = <0x0 0x1>;
+             cooling-levels = <127 255>;
Quoted 2 lines

[Severity: High]
Should these arrays be explicitly sized using /bits/ 8?

Could be used 32 bits.

Quoted 7 lines

The Device Tree compiler natively emits 32-bit big-endian integers for this syntax. However, if the driver (npcm750-pwm-fan.c) explicitly reads both properties using of_property_read_u8_array(), an 8-byte payload like <127 255> would be read as 8 individual u8 elements:
0, 0, 0, 127, 0, 0, 0, 255.

Quoted 7 lines

Does this result in registering intermediate thermal cooling states with a 0 duty cycle, inadvertently turning the fan off during active cooling requests?

Quoted 1 line

+ };

--
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=3

Thanks,

Tomer