Finish removing crypto_rng from drivers/crypto/
Subsystems (12)
cover Finish removing crypto_rng from drivers/crypto/
This series finishes removing the unused, redundant, and frequently broken crypto_rng support from drivers/crypto/. It applies to cryptodev/master.
Patches 1-4 are a resend of
https://lore.kernel.org/linux-crypto/[email protected]/
Please consider these patches for 7.2, considering that most of these drivers had security vulnerabilities which would have needed to be fixed right away anyway. And the qcom hwrng fixes are important too.
Eric Biggers (7):
crypto: qcom-rng - Enable clock in hwrng case
crypto: qcom-rng - Allow zero as a random number
crypto: qcom-rng - Remove crypto_rng interface
hwrng: qcom - Move qcom-rng.c into drivers/char/hw_random/
crypto: sun8i-ce - Remove crypto_rng interface
crypto: sun8i-ss - Remove crypto_rng interface
crypto: caam - Remove crypto_rng interface
arch/arm/configs/multi_v7_defconfig | 2 +-
arch/arm/configs/qcom_defconfig | 2 +-
arch/arm64/configs/defconfig | 2 +-
drivers/char/hw_random/Kconfig | 11 +
drivers/char/hw_random/Makefile | 1 +
drivers/{crypto => char/hw_random}/qcom-rng.c | 156 ++----------
drivers/crypto/Kconfig | 12 -
drivers/crypto/Makefile | 1 -
drivers/crypto/allwinner/Kconfig | 16 --
drivers/crypto/allwinner/sun8i-ce/Makefile | 1 -
.../crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 63 -----
.../crypto/allwinner/sun8i-ce/sun8i-ce-prng.c | 159 ------------
drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h | 29 ---
drivers/crypto/allwinner/sun8i-ss/Makefile | 1 -
.../crypto/allwinner/sun8i-ss/sun8i-ss-core.c | 45 ----
.../crypto/allwinner/sun8i-ss/sun8i-ss-prng.c | 177 -------------
drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h | 23 --
drivers/crypto/caam/Kconfig | 9 -
drivers/crypto/caam/Makefile | 1 -
drivers/crypto/caam/caamprng.c | 241 ------------------
drivers/crypto/caam/intern.h | 15 --
drivers/crypto/caam/jr.c | 2 -
drivers/gpu/drm/ci/arm64.config | 2 +-
23 files changed, 41 insertions(+), 930 deletions(-)
rename drivers/{crypto => char/hw_random}/qcom-rng.c (53%)
delete mode 100644 drivers/crypto/allwinner/sun8i-ce/sun8i-ce-prng.c
delete mode 100644 drivers/crypto/allwinner/sun8i-ss/sun8i-ss-prng.c
delete mode 100644 drivers/crypto/caam/caamprng.cbase-commit: 6ea0ce3a19f9c37a014099e2b0a46b27fa164564
Signature · 1 line
2.54.0
PATCH 1/7 crypto: qcom-rng - Enable clock in hwrng case
Fix qcom-rng.c to enable the clock before accessing the hardware.
--- drivers/crypto/qcom-rng.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
drivers/crypto/qcom-rng.c +16 -0
@@ -111,17 +111,31 @@ static int qcom_rng_seed(struct crypto_rng *tfm, const u8 *seed, unsigned int slen) {return 0 ; } +static int qcom_hwrng_init (struct hwrng *hwrng) +{ + struct qcom_rng *qrng = container_of(hwrng, struct qcom_rng, hwrng); + +return clk_prepare_enable (qrng->clk); +} +static int qcom_hwrng_read (struct hwrng *hwrng,void *data,size_t max,bool wait) { struct qcom_rng *qrng = container_of(hwrng, struct qcom_rng, hwrng);return qcom_rng_read (qrng, data, max); } +static void qcom_hwrng_cleanup (struct hwrng *hwrng) +{ + struct qcom_rng *qrng = container_of(hwrng, struct qcom_rng, hwrng); + +clk_disable_unprepare (qrng->clk); +} +static int qcom_rng_enable (struct qcom_rng *rng) {u32 val;int ret;
@@ -206,11 +220,13 @@ static int qcom_rng_probe(struct platform_device *pdev)return ret; }if (rng->match_data->hwrng_support) { rng->hwrng.name ="qcom_hwrng" ; + rng->hwrng.init = qcom_hwrng_init; rng->hwrng.read = qcom_hwrng_read; + rng->hwrng.cleanup = qcom_hwrng_cleanup; rng->hwrng.quality =QCOM_TRNG_QUALITY ; ret =devm_hwrng_register (&pdev->dev, &rng->hwrng);if (ret) {dev_err (&pdev->dev,"Register hwrng failed: %d\n" , ret); qcom_rng_dev =NULL ;
Signature · 1 line
2.54.0
PATCH 2/7 crypto: qcom-rng - Allow zero as a random number
In reply to Eric BiggersZero is a valid random number and needs to be allowed. Otherwise the output is distinguishable from random.
--- drivers/crypto/qcom-rng.c | 2 -- 1 file changed, 2 deletions(-)
drivers/crypto/qcom-rng.c +0 -2
@@ -63,12 +63,10 @@ static int qcom_rng_read(struct qcom_rng *rng, u8 *data, unsigned int max) 200, 10000);if (ret)return ret; val =readl_relaxed (rng->base +PRNG_DATA_OUT ); -if (!val) -return -EINVAL ;if ((max - currsize) >=WORD_SZ ) {memcpy (data, &val,WORD_SZ ); data +=WORD_SZ ; currsize +=WORD_SZ ;
Signature · 1 line
2.54.0
PATCH 3/7 crypto: qcom-rng - Remove crypto_rng interface
In reply to Eric Biggersqcom-rng.c exposes the same hardware through two completely separate interfaces, crypto_rng and hwrng. However, the implementation of this is buggy because it permits generation operations from these interfaces to run concurrently with each other, accessing the same registers. That is, qcom_rng_generate() synchronizes with itself but not with qcom_hwrng_read(). This results in potential repetition of output from the RNG, output of non-random values, etc.
Fortunately, there's actually no point in hardware RNG drivers implementing the crypto_rng interface. It's not actually used by anything besides the "rng" algorithm type of AF_ALG, which in turn is not actually used in practice. Other crypto_rng hardware drivers are likewise being phased out, leaving just the hwrng support.
Thus, remove it to simplify the code and avoid conflict (and confusion) with the hwrng interface which is the one that actually matters.
--- drivers/crypto/Kconfig | 1 - drivers/crypto/qcom-rng.c | 158 +++++--------------------------------- 2 files changed, 19 insertions(+), 140 deletions(-)
drivers/crypto/Kconfig +0 -1
@@ -639,11 +639,10 @@ config CRYPTO_DEV_QCE_SW_MAX_LEN config CRYPTO_DEV_QCOM_RNG tristate "Qualcomm Random Number Generator Driver" depends on ARCH_QCOM || COMPILE_TEST depends on HW_RANDOM - select CRYPTO_RNG help This driver provides support for the Random Number Generator hardware found on Qualcomm SoCs. To compile this driver as a module, choose M here. The
drivers/crypto/qcom-rng.c +19 -139
248 lines not on this page · raw message
Signature · 1 line
2.54.0
PATCH 4/7 hwrng: qcom - Move qcom-rng.c into drivers/char/hw_random/
In reply to Eric BiggersSince this file just implements a hwrng driver, move it into drivers/char/hw_random/. Rename the kconfig option accordingly as well.
---
arch/arm/configs/multi_v7_defconfig | 2 +-
arch/arm/configs/qcom_defconfig | 2 +-
arch/arm64/configs/defconfig | 2 +-
drivers/char/hw_random/Kconfig | 11 +++++++++++
drivers/char/hw_random/Makefile | 1 +
drivers/{crypto => char/hw_random}/qcom-rng.c | 0
drivers/crypto/Kconfig | 11 -----------
drivers/crypto/Makefile | 1 -
drivers/gpu/drm/ci/arm64.config | 2 +-
9 files changed, 16 insertions(+), 16 deletions(-)
rename drivers/{crypto => char/hw_random}/qcom-rng.c (100%)arch/arm/configs/multi_v7_defconfig +1 -1
@@ -404,10 +404,11 @@ CONFIG_SERIAL_DEV_BUS=y CONFIG_VIRTIO_CONSOLE=y CONFIG_ASPEED_KCS_IPMI_BMC=m CONFIG_ASPEED_BT_IPMI_BMC=m CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_ST=y +CONFIG_HW_RANDOM_QCOM=m CONFIG_TCG_TPM=m CONFIG_TCG_TIS_I2C_INFINEON=m CONFIG_I2C_CHARDEV=y CONFIG_I2C_ARB_GPIO_CHALLENGE=m CONFIG_I2C_MUX_GPIO=y
@@ -1333,11 +1334,10 @@ CONFIG_CRYPTO_DEV_S5P=m CONFIG_CRYPTO_DEV_ATMEL_AES=m CONFIG_CRYPTO_DEV_ATMEL_TDES=m CONFIG_CRYPTO_DEV_ATMEL_SHA=m CONFIG_CRYPTO_DEV_MARVELL_CESA=m CONFIG_CRYPTO_DEV_QCE=m -CONFIG_CRYPTO_DEV_QCOM_RNG=m CONFIG_CRYPTO_DEV_ROCKCHIP=m CONFIG_CRYPTO_DEV_STM32_HASH=m CONFIG_CRYPTO_DEV_STM32_CRYP=m CONFIG_CMA_SIZE_MBYTES=64 CONFIG_PRINTK_TIME=y
arch/arm/configs/qcom_defconfig +1 -1
@@ -115,10 +115,11 @@ CONFIG_SERIO_LIBPS2=y # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_SERIAL_DEV_BUS=y CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_QCOM=m CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_QUP=y CONFIG_SPI=y CONFIG_SPI_QUP=y
@@ -309,11 +310,10 @@ CONFIG_CRYPTO_USER=m CONFIG_CRYPTO_USER_API=m CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_USER_API_RNG=m CONFIG_CRYPTO_USER_API_AEAD=m -CONFIG_CRYPTO_DEV_QCOM_RNG=m CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=64 CONFIG_PRINTK_TIME=y CONFIG_DYNAMIC_DEBUG=y CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
arch/arm64/configs/defconfig +1 -1
@@ -550,10 +550,11 @@ CONFIG_IPMI_DEVICE_INTERFACE=m CONFIG_IPMI_SI=m CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y CONFIG_HW_RANDOM_HISI_TRNG=m CONFIG_HW_RANDOM_XILINX=m +CONFIG_HW_RANDOM_QCOM=m CONFIG_TCG_TPM=y CONFIG_TCG_TIS=m CONFIG_TCG_TIS_SPI=m CONFIG_TCG_TIS_SPI_CR50=y CONFIG_TCG_TIS_I2C_CR50=m
@@ -1953,11 +1954,10 @@ CONFIG_CRYPTO_AES_ARM64_BS=m CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_DEV_SUN8I_CE=m CONFIG_CRYPTO_DEV_FSL_CAAM=m CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM=m CONFIG_CRYPTO_DEV_QCE=m -CONFIG_CRYPTO_DEV_QCOM_RNG=m CONFIG_CRYPTO_DEV_TEGRA=m CONFIG_CRYPTO_DEV_ZYNQMP_AES=m CONFIG_CRYPTO_DEV_ZYNQMP_SHA3=m CONFIG_CRYPTO_DEV_CCREE=m CONFIG_CRYPTO_DEV_HISI_SEC2=m
drivers/char/hw_random/Kconfig +11 -0
@@ -634,10 +634,21 @@ config HW_RANDOM_XILINX Generator and Pseudo random Number in CTR_DRBG mode as defined in NIST SP800-90A. To compile this driver as a module, choose M here: the module will be called xilinx-trng. +config HW_RANDOM_QCOM + tristate "Qualcomm True Random Number Generator Driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on HW_RANDOM + help + This driver provides support for the True Random Number + Generator hardware found on some Qualcomm SoCs. + + To compile this driver as a module, choose M here. The + module will be called qcom-rng. If unsure, say N. + endif # HW_RANDOM config UML_RANDOM depends on UML select HW_RANDOM
drivers/char/hw_random/Makefile +1 -0
@@ -52,5 +52,6 @@ obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o obj-$(CONFIG_HW_RANDOM_XILINX) += xilinx-trng.o +obj-$(CONFIG_HW_RANDOM_QCOM) += qcom-rng.o
drivers/char/hw_random/qcom-rng.c renamed from drivers/crypto/qcom-rng.c +0 -0
drivers/crypto/Kconfig +0 -11
@@ -635,21 +635,10 @@ config CRYPTO_DEV_QCE_SW_MAX_LEN Note that 192-bit keys are not supported by the hardware and are always processed by the software fallback, and all DES requests are done by the hardware. -config CRYPTO_DEV_QCOM_RNG - tristate "Qualcomm Random Number Generator Driver" - depends on ARCH_QCOM || COMPILE_TEST - depends on HW_RANDOM - help - This driver provides support for the Random Number - Generator hardware found on Qualcomm SoCs. - - To compile this driver as a module, choose M here. The - module will be called qcom-rng. If unsure, say N. - config CRYPTO_DEV_IMGTEC_HASH tristate "Imagination Technologies hardware hash accelerator" depends on MIPS || COMPILE_TEST select CRYPTO_MD5 select CRYPTO_SHA1
drivers/crypto/Makefile +0 -1
@@ -25,11 +25,10 @@ obj-$(CONFIG_CRYPTO_DEV_OMAP_DES) += omap-des.o obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o obj-$(CONFIG_CRYPTO_DEV_PADLOCK_AES) += padlock-aes.o obj-$(CONFIG_CRYPTO_DEV_PADLOCK_SHA) += padlock-sha.o obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/ obj-$(CONFIG_CRYPTO_DEV_QCE) += qce/ -obj-$(CONFIG_CRYPTO_DEV_QCOM_RNG) += qcom-rng.o obj-$(CONFIG_CRYPTO_DEV_ROCKCHIP) += rockchip/ obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o obj-$(CONFIG_CRYPTO_DEV_SA2UL) += sa2ul.o obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o obj-$(CONFIG_CRYPTO_DEV_SL3516) += gemini/
drivers/gpu/drm/ci/arm64.config +1 -1
@@ -76,11 +76,10 @@ CONFIG_INTERCONNECT_QCOM_SDM845=y CONFIG_INTERCONNECT_QCOM_MSM8916=y CONFIG_INTERCONNECT_QCOM_MSM8996=y CONFIG_INTERCONNECT_QCOM_OSM_L3=y CONFIG_INTERCONNECT_QCOM_SC7180=y CONFIG_INTERCONNECT_QCOM_SM8350=y -CONFIG_CRYPTO_DEV_QCOM_RNG=y CONFIG_SC_DISPCC_7180=y CONFIG_SC_GPUCC_7180=y CONFIG_SM_GPUCC_8350=y CONFIG_QCOM_SPMI_ADC5=y CONFIG_QCOM_SPMI_VADC=y
@@ -187,10 +186,11 @@ CONFIG_PWM_MEDIATEK=y CONFIG_DRM_MEDIATEK_HDMI=y CONFIG_GNSS=y CONFIG_GNSS_MTK_SERIAL=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_MTK=y +CONFIG_HW_RANDOM_QCOM=y CONFIG_MTK_DEVAPC=y CONFIG_PWM_MTK_DISP=y CONFIG_MTK_CMDQ=y CONFIG_REGULATOR_DA9211=y CONFIG_DRM_ANALOGIX_ANX7625=y
Signature · 1 line
2.54.0
PATCH 5/7 crypto: sun8i-ce - Remove crypto_rng interface
In reply to Eric BiggersSince the crypto_rng interface for hardware PRNGs is unused and is redundant with hwrng and the actual Linux RNG, it's being phased out. Most drivers for it were already removed. Go ahead and remove the sun8i-ce support which is one of the only remaining ones.
Note that the sun8i-ce support for hwrng remains in place. That is the interface that actually matters.
As usual for crypto_rng, this driver was also buggy: its ->generate() function had a use-after-free vulnerability due to using wait_for_completion_interruptible_timeout() without handling shutting down the DMA operation if a signal is sent. There's no point in fixing this separately only to remove the code anyway, so this commit is marked with Fixes and Cc stable.
--- drivers/crypto/allwinner/Kconfig | 8 - drivers/crypto/allwinner/sun8i-ce/Makefile | 1 - .../crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 63 ------- .../crypto/allwinner/sun8i-ce/sun8i-ce-prng.c | 159 ------------------ drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h | 29 ---- 5 files changed, 260 deletions(-) delete mode 100644 drivers/crypto/allwinner/sun8i-ce/sun8i-ce-prng.c
drivers/crypto/allwinner/Kconfig +0 -8
@@ -68,18 +68,10 @@ config CRYPTO_DEV_SUN8I_CE_HASH select CRYPTO_SHA256 select CRYPTO_SHA512 help Say y to enable support for hash algorithms. -config CRYPTO_DEV_SUN8I_CE_PRNG - bool "Support for Allwinner Crypto Engine PRNG" - depends on CRYPTO_DEV_SUN8I_CE - select CRYPTO_RNG - help - Select this option if you want to provide kernel-side support for - the Pseudo-Random Number Generator found in the Crypto Engine. - config CRYPTO_DEV_SUN8I_CE_TRNG bool "Support for Allwinner Crypto Engine TRNG" depends on CRYPTO_DEV_SUN8I_CE select HW_RANDOM help
drivers/crypto/allwinner/sun8i-ce/Makefile +0 -1
@@ -1,5 +1,4 @@ obj-$(CONFIG_CRYPTO_DEV_SUN8I_CE) += sun8i-ce.o sun8i-ce-y += sun8i-ce-core.o sun8i-ce-cipher.o sun8i-ce-$(CONFIG_CRYPTO_DEV_SUN8I_CE_HASH) += sun8i-ce-hash.o -sun8i-ce-$(CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG) += sun8i-ce-prng.o sun8i-ce-$(CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG) += sun8i-ce-trng.o
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c +0 -63
199 lines not on this page · raw message
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-prng.c deleted +0 -159
159 lines not on this page · raw message
drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h +0 -29
@@ -13,11 +13,10 @@#include <linux/debugfs.h> #include <linux/crypto.h> #include <linux/hw_random.h> #include <crypto/internal/hash.h> #include <crypto/md5.h> -#include <crypto/rng.h> #include <crypto/sha1.h> #include <crypto/sha2.h> /* CE Registers */ #define CE_TDQ 0x00
@@ -56,13 +55,11 @@#define CE_ALG_SHA224 18#define CE_ALG_SHA256 19#define CE_ALG_SHA384 20#define CE_ALG_SHA512 21#define CE_ALG_TRNG 48 -#define CE_ALG_PRNG 49#define CE_ALG_TRNG_V2 0x1c -#define CE_ALG_PRNG_V2 0x1d/* Used in ce_variant */ #define CE_ID_NOTSUPP 0xFF#define CE_ID_CIPHER_AES 0
@@ -94,14 +91,10 @@#define ESR_R40 2#define ESR_H5 3#define ESR_H6 4#define ESR_D1 5 -#define PRNG_DATA_SIZE (160 / 8) -#define PRNG_SEED_SIZE DIV_ROUND_UP(175, 8) -#define PRNG_LD BIT(17) -#define CE_DIE_ID_SHIFT 16#define CE_DIE_ID_MASK 0x07#define MAX_SG 8
@@ -134,31 +127,26 @@ struct ce_clock {* @op_mode: list of supported block modes * @cipher_t_dlen_in_bytes: Does the request size for cipher is in * bytes or words * @hash_t_dlen_in_bytes: Does the request size for hash is in * bits or words -* @prng_t_dlen_in_bytes: Does the request size for PRNG is in -* bytes or words * @trng_t_dlen_in_bytes: Does the request size for TRNG is in * bytes or words * @ce_clks: list of clocks needed by this variant * @esr: The type of error register -* @prng: The CE_ALG_XXX value for the PRNG * @trng: The CE_ALG_XXX value for the TRNG */ struct ce_variant {char alg_cipher[CE_ID_CIPHER_MAX ];char alg_hash[CE_ID_HASH_MAX ];u32 op_mode[CE_ID_OP_MAX ];bool cipher_t_dlen_in_bytes;bool hash_t_dlen_in_bits; -bool prng_t_dlen_in_bytes;bool trng_t_dlen_in_bytes;bool needs_word_addresses;struct ce_clock ce_clks[CE_MAX_CLOCKS ];int esr; -unsigned char prng;unsigned char trng; };struct sginfo {__le32 addr;
@@ -325,20 +313,10 @@ struct sun8i_ce_hash_reqctx {u8 result[CE_MAX_HASH_DIGEST_SIZE ]__aligned(CRYPTO_DMA_ALIGN) ;u8 pad[2 *CE_MAX_HASH_BLOCK_SIZE ];struct ahash_request fallback_req;// keep at the end }; -/* -* struct sun8i_ce_prng_ctx - context for PRNG TFM -* @seed: The seed to use -* @slen: The size of the seed -*/ -struct sun8i_ce_rng_tfm_ctx { -void *seed; -unsigned int slen; -}; -/* * struct sun8i_ce_alg_template - crypto_alg template * @type: the CRYPTO_ALG_TYPE for this template * @ce_algo_id: the CE_ID for this template * @ce_blockmode: the type of block operation CE_ID
@@ -355,11 +333,10 @@ struct sun8i_ce_alg_template {u32 ce_blockmode;struct sun8i_ce_dev *ce;union {struct skcipher_engine_alg skcipher;struct ahash_engine_alg hash; -struct rng_alg rng; } alg;unsigned long stat_req;unsigned long stat_fb;unsigned long stat_bytes;unsigned long stat_fb_maxsg;
@@ -396,13 +373,7 @@ int sun8i_ce_hash_final(struct ahash_request *areq);int sun8i_ce_hash_update (struct ahash_request *areq);int sun8i_ce_hash_finup (struct ahash_request *areq);int sun8i_ce_hash_digest (struct ahash_request *areq);int sun8i_ce_hash_run (struct crypto_engine *engine,void *breq); -int sun8i_ce_prng_generate (struct crypto_rng *tfm,const u8 *src, -unsigned int slen,u8 *dst,unsigned int dlen); -int sun8i_ce_prng_seed (struct crypto_rng *tfm,const u8 *seed,unsigned int slen); -void sun8i_ce_prng_exit (struct crypto_tfm *tfm); -int sun8i_ce_prng_init (struct crypto_tfm *tfm); -int sun8i_ce_hwrng_register (struct sun8i_ce_dev *ce);void sun8i_ce_hwrng_unregister (struct sun8i_ce_dev *ce);
Signature · 1 line
2.54.0
PATCH 6/7 crypto: sun8i-ss - Remove crypto_rng interface
In reply to Eric BiggersSince the crypto_rng interface for hardware PRNGs is unused and is redundant with hwrng and the actual Linux RNG, it's being phased out. Most drivers for it were already removed. Go ahead and remove the sun8i-ss support which is one of the only remaining ones.
As usual for crypto_rng, this driver was also buggy: its ->generate() function had a use-after-free vulnerability due to using wait_for_completion_interruptible_timeout() without handling shutting down the DMA operation if a signal is sent. Also, it had a buffer overread bug in the line 'memcpy(ctx->seed, d + dlen, ctx->slen);'. There's no point in fixing these bugs separately only to remove the code anyway, so this commit is marked with Fixes and Cc stable.
--- drivers/crypto/allwinner/Kconfig | 8 - drivers/crypto/allwinner/sun8i-ss/Makefile | 1 - .../crypto/allwinner/sun8i-ss/sun8i-ss-core.c | 45 ----- .../crypto/allwinner/sun8i-ss/sun8i-ss-prng.c | 177 ------------------ drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h | 23 --- 5 files changed, 254 deletions(-) delete mode 100644 drivers/crypto/allwinner/sun8i-ss/sun8i-ss-prng.c
drivers/crypto/allwinner/Kconfig +0 -8
@@ -103,18 +103,10 @@ config CRYPTO_DEV_SUN8I_SS_DEBUG help Say y to enable sun8i-ss debug stats. This will create /sys/kernel/debug/sun8i-ss/stats for displaying the number of requests per flow and per algorithm. -config CRYPTO_DEV_SUN8I_SS_PRNG - bool "Support for Allwinner Security System PRNG" - depends on CRYPTO_DEV_SUN8I_SS - select CRYPTO_RNG - help - Select this option if you want to provide kernel-side support for - the Pseudo-Random Number Generator found in the Security System. - config CRYPTO_DEV_SUN8I_SS_HASH bool "Enable support for hash on sun8i-ss" depends on CRYPTO_DEV_SUN8I_SS select CRYPTO_MD5 select CRYPTO_SHA1
drivers/crypto/allwinner/sun8i-ss/Makefile +0 -1
@@ -1,4 +1,3 @@ obj-$(CONFIG_CRYPTO_DEV_SUN8I_SS) += sun8i-ss.o sun8i-ss-y += sun8i-ss-core.o sun8i-ss-cipher.o -sun8i-ss-$(CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG) += sun8i-ss-prng.o sun8i-ss-$(CONFIG_CRYPTO_DEV_SUN8I_SS_HASH) += sun8i-ss-hash.o
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c +0 -45
95 lines not on this page · raw message
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-prng.c deleted +0 -177
177 lines not on this page · raw message
drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h +0 -23
@@ -6,11 +6,10 @@* Copyright (C) 2016-2019 Corentin LABBE <[email protected]> */ #include <crypto/aes.h> #include <crypto/des.h> #include <crypto/engine.h> -#include <crypto/rng.h> #include <crypto/skcipher.h> #include <linux/atomic.h> #include <linux/debugfs.h> #include <linux/crypto.h> #include <crypto/internal/hash.h>
@@ -25,11 +24,10 @@#define SS_ALG_AES 0#define SS_ALG_DES (1 << 2)#define SS_ALG_3DES (2 << 2)#define SS_ALG_MD5 (3 << 2) -#define SS_ALG_PRNG (4 << 2)#define SS_ALG_SHA1 (6 << 2)#define SS_ALG_SHA224 (7 << 2)#define SS_ALG_SHA256 (8 << 2)#define SS_CTL_REG 0x00
@@ -66,24 +64,19 @@#define SS_ID_HASH_MAX 4#define SS_FLOW0 BIT(30)#define SS_FLOW1 BIT(31) -#define SS_PRNG_CONTINUE BIT(18) -#define MAX_SG 8#define MAXFLOW 2#define SS_MAX_CLOCKS 2#define SS_DIE_ID_SHIFT 20#define SS_DIE_ID_MASK 0x07 -#define PRNG_DATA_SIZE (160 / 8) -#define PRNG_SEED_SIZE DIV_ROUND_UP(175, 8) -#define MAX_PAD_SIZE 4096/* * struct ss_clock - Describe clocks used by sun8i-ss * @name: Name of clock needed by this variant
@@ -211,20 +204,10 @@ struct sun8i_cipher_tfm_ctx {u32 keylen;struct sun8i_ss_dev *ss;struct crypto_skcipher *fallback_tfm; }; -/* -* struct sun8i_ss_prng_ctx - context for PRNG TFM -* @seed: The seed to use -* @slen: The size of the seed -*/ -struct sun8i_ss_rng_tfm_ctx { -void *seed; -unsigned int slen; -}; -/* * struct sun8i_ss_hash_tfm_ctx - context for an ahash TFM * @fallback_tfm: pointer to the fallback TFM * @ss: pointer to the private data of driver handling this TFM */
@@ -272,11 +255,10 @@ struct sun8i_ss_alg_template {u32 ss_algo_id;u32 ss_blockmode;struct sun8i_ss_dev *ss;union {struct skcipher_engine_alg skcipher; -struct rng_alg rng;struct ahash_engine_alg hash; } alg;unsigned long stat_req;unsigned long stat_fb;unsigned long stat_bytes;
@@ -298,15 +280,10 @@ int sun8i_ss_skdecrypt(struct skcipher_request *areq);int sun8i_ss_skencrypt (struct skcipher_request *areq);int sun8i_ss_get_engine_number (struct sun8i_ss_dev *ss);int sun8i_ss_run_task (struct sun8i_ss_dev *ss,struct sun8i_cipher_req_ctx *rctx,const char *name); -int sun8i_ss_prng_generate (struct crypto_rng *tfm,const u8 *src, -unsigned int slen,u8 *dst,unsigned int dlen); -int sun8i_ss_prng_seed (struct crypto_rng *tfm,const u8 *seed,unsigned int slen); -int sun8i_ss_prng_init (struct crypto_tfm *tfm); -void sun8i_ss_prng_exit (struct crypto_tfm *tfm);int sun8i_ss_hash_init_tfm (struct crypto_ahash *tfm);void sun8i_ss_hash_exit_tfm (struct crypto_ahash *tfm);int sun8i_ss_hash_init (struct ahash_request *areq);int sun8i_ss_hash_export (struct ahash_request *areq,void *out);
Signature · 1 line
2.54.0
PATCH 7/7 crypto: caam - Remove crypto_rng interface
In reply to Eric BiggersSince the crypto_rng interface for hardware PRNGs is unused and is redundant with hwrng and the actual Linux RNG, it's being phased out. Most drivers for it were already removed. Go ahead and remove the CAAM support which is one of the only remaining ones.
Note that the CAAM support for hwrng remains in place. That is the interface that actually matters.
Note that this code also had several issues, including dlen > 65535 causing corruption of the CAAM descriptor.
--- drivers/crypto/caam/Kconfig | 9 -- drivers/crypto/caam/Makefile | 1 - drivers/crypto/caam/caamprng.c | 241 --------------------------------- drivers/crypto/caam/intern.h | 15 -- drivers/crypto/caam/jr.c | 2 - 5 files changed, 268 deletions(-) delete mode 100644 drivers/crypto/caam/caamprng.c
drivers/crypto/caam/Kconfig +0 -9
@@ -143,24 +143,15 @@ config CRYPTO_DEV_FSL_CAAM_PKC_API signature and verification. config CRYPTO_DEV_FSL_CAAM_RNG_API bool "Register caam device for hwrng API" default y - select CRYPTO_RNG select HW_RANDOM help Selecting this will register the SEC4 hardware rng to the hw_random API for supplying the kernel entropy pool. -config CRYPTO_DEV_FSL_CAAM_PRNG_API - bool "Register Pseudo random number generation implementation with Crypto API" - default y - select CRYPTO_RNG - help - Selecting this will register the SEC hardware prng to - the Crypto API. - config CRYPTO_DEV_FSL_CAAM_BLOB_GEN bool config CRYPTO_DEV_FSL_CAAM_RNG_TEST bool "Test caam rng"
drivers/crypto/caam/Makefile +0 -1
@@ -18,11 +18,10 @@ caam-y := ctrl.o caam_jr-y := jr.o key_gen.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += caamalg_qi.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o -caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API) += caamprng.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API) += caampkc.o pkc_desc.o caam_jr-$(CONFIG_CRYPTO_DEV_FSL_CAAM_BLOB_GEN) += blob_gen.o caam-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += qi.o caam-$(CONFIG_DEBUG_FS) += debugfs.o
drivers/crypto/caam/caamprng.c deleted +0 -241
241 lines not on this page · raw message
drivers/crypto/caam/intern.h +0 -15
@@ -210,25 +210,10 @@ static inline int caam_rng_init(struct device *dev)static inline void caam_rng_exit (struct device *dev) {}#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API */ -#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API - -int caam_prng_register (struct device *dev); -void caam_prng_unregister (void *data); - -#else - -static inline int caam_prng_register (struct device *dev) -{ -return 0 ; -} - -static inline void caam_prng_unregister (void *data) {} -#endif /* CONFIG_CRYPTO_DEV_FSL_CAAM_PRNG_API */ -#ifdef CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI int caam_qi_algapi_init (struct device *dev);void caam_qi_algapi_exit (void );
drivers/crypto/caam/jr.c +0 -2
@@ -38,11 +38,10 @@ static void register_algs(struct caam_drv_private_jr *jrpriv,caam_algapi_init (dev);caam_algapi_hash_init (dev);caam_pkc_init (dev); jrpriv->hwrng = !caam_rng_init (dev); -caam_prng_register (dev);caam_qi_algapi_init (dev); algs_unlock:mutex_unlock (&algs_lock); }
@@ -53,11 +52,10 @@ static void unregister_algs(void)if (--active_devs !=0 ) goto algs_unlock;caam_qi_algapi_exit (); -caam_prng_unregister (NULL );caam_pkc_exit ();caam_algapi_hash_exit ();caam_algapi_exit (); algs_unlock:
Signature · 1 line
2.54.0
Herbert Xu
maintainerQuoted 50 lines · Eric Biggers
This series finishes removing the unused, redundant, and frequently broken
crypto_rngsupport fromdrivers/crypto/. It applies to cryptodev/master.Patches 1-4 are a resend of
https://lore.kernel.org/linux-crypto/[email protected]/Please consider these patches for 7.2, considering that most of these drivers had security vulnerabilities which would have needed to be fixed right away anyway. And the qcom hwrng fixes are important too.
Eric Biggers (7):
crypto: qcom-rng - Enable clock in hwrng case
crypto: qcom-rng - Allow zero as a random number
crypto: qcom-rng - Removecrypto_rnginterface
hwrng: qcom - Moveqcom-rng.cintodrivers/char/hw_random/
crypto: sun8i-ce - Removecrypto_rnginterface
crypto: sun8i-ss - Removecrypto_rnginterface
crypto: caam - Removecrypto_rnginterfacearch/arm/configs/multi_v7_defconfig | 2 +- arch/arm/configs/qcom_defconfig | 2 +- arch/arm64/configs/defconfig | 2 +- drivers/char/hw_random/Kconfig | 11 + drivers/char/hw_random/Makefile | 1 + drivers/{crypto => char/hw_random}/qcom-rng.c | 156 ++---------- drivers/crypto/Kconfig | 12 - drivers/crypto/Makefile | 1 - drivers/crypto/allwinner/Kconfig | 16 -- drivers/crypto/allwinner/sun8i-ce/Makefile | 1 - .../crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 63 ----- .../crypto/allwinner/sun8i-ce/sun8i-ce-prng.c | 159 ------------ drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h | 29 --- drivers/crypto/allwinner/sun8i-ss/Makefile | 1 - .../crypto/allwinner/sun8i-ss/sun8i-ss-core.c | 45 ---- .../crypto/allwinner/sun8i-ss/sun8i-ss-prng.c | 177 ------------- drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h | 23 -- drivers/crypto/caam/Kconfig | 9 - drivers/crypto/caam/Makefile | 1 - drivers/crypto/caam/caamprng.c | 241 ------------------ drivers/crypto/caam/intern.h | 15 -- drivers/crypto/caam/jr.c | 2 - drivers/gpu/drm/ci/arm64.config | 2 +- 23 files changed, 41 insertions(+), 930 deletions(-) rename drivers/{crypto => char/hw_random}/qcom-rng.c (53%) delete mode 100644 drivers/crypto/allwinner/sun8i-ce/sun8i-ce-prng.c delete mode 100644 drivers/crypto/allwinner/sun8i-ss/sun8i-ss-prng.c delete mode 100644 drivers/crypto/caam/caamprng.c
Quoted 1 line
base-commit:
6ea0ce3a19f9c37a014099e2b0a46b27fa164564
Patches 4-7 applied. Thanks.
Signature · 3 lines
Email: Herbert Xu <[email protected]> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt