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cpufreq: tegra124: Disable DFLL clock on removal

PATCH In review Myeonghun Pak 2 participants 3 messages Jun 26 – Jun 28

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Tegra architecture support CPU frequency scaling framework
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Myeonghun Pak

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#0 lore raw

PATCH 1/1 cpufreq: tegra124: Disable DFLL clock on removal

tegra124_cpu_switch_to_dfll() enables the DFLL clock before switching the CPU clock parent to it. If cpufreq_dt_pdev_register() fails after that point, or when the driver is removed, the driver only drops clock references and never disables the enabled DFLL clock.

Add a helper for switching the CPU back to PLLP and disabling DFLL, then use it in the post-DFLL probe unwind path and in remove.

Fixes 9f5ed5fe6060 ("cpufreq: tegra124: do not handle the CPU rail")
Co-developed-by Ijae Kim <[email protected]>
Signed-off-by Ijae Kim <[email protected]>
Signed-off-by Myeonghun Pak <[email protected]>
---
 drivers/cpufreq/tegra124-cpufreq.c | 25 +++++++++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)
drivers/cpufreq/tegra124-cpufreq.c +24 -2
index f8a76bbec..1fb3bf50b 100644
@@ -54,12 +54,25 @@
 	return ret;
 }
 
+static int tegra124_cpu_disable_dfll(struct tegra124_cpufreq_priv *priv)
+{
+	int ret;
+
+	ret = clk_set_parent(priv->cpu_clk, priv->pllp_clk);
+	if (ret)
+		return ret;
+
+	clk_disable_unprepare(priv->dfll_clk);
+
+	return 0;
+}
+
 static int tegra124_cpufreq_probe(struct platform_device *pdev)
 {
 	struct device_node *np __free(device_node) = of_cpu_device_node_get(0);
 	struct tegra124_cpufreq_priv *priv;
 	struct device *cpu_dev;
-	int ret;
+	int err, ret;
 
 	if (!np)
 		return -ENODEV;

@@ -101,13 +114,17 @@
 	priv->cpufreq_dt_pdev = cpufreq_dt_pdev_register(&pdev->dev);
 	if (IS_ERR(priv->cpufreq_dt_pdev)) {
 		ret = PTR_ERR(priv->cpufreq_dt_pdev);
-		goto out_put_pllp_clk;
+		goto out_disable_dfll;
 	}
 
 	platform_set_drvdata(pdev, priv);
 
 	return 0;
 
+out_disable_dfll:
+	err = tegra124_cpu_disable_dfll(priv);
+	if (err)
+		dev_err(&pdev->dev, "failed to disable DFLL clock: %d\n", err);
 out_put_pllp_clk:
 	clk_put(priv->pllp_clk);
 out_put_pllx_clk:

@@ -175,12 +192,17 @@
 static void tegra124_cpufreq_remove(struct platform_device *pdev)
 {
 	struct tegra124_cpufreq_priv *priv = dev_get_drvdata(&pdev->dev);
+	int err;
 
 	if (!IS_ERR(priv->cpufreq_dt_pdev)) {
 		platform_device_unregister(priv->cpufreq_dt_pdev);
 		priv->cpufreq_dt_pdev = ERR_PTR(-ENODEV);
 	}
 
+	err = tegra124_cpu_disable_dfll(priv);
+	if (err)
+		dev_err(&pdev->dev, "failed to disable DFLL clock: %d\n", err);
+
 	clk_put(priv->pllp_clk);
 	clk_put(priv->pllx_clk);
 	clk_put(priv->dfll_clk);
Signature · 1 line
2.39.5
maintainer
#1 lore raw
Quoted 4 lines · Myeonghun Pak

tegra124_cpu_switch_to_dfll() enables the DFLL clock before switching the CPU clock parent to it. If cpufreq_dt_pdev_register() fails after that point, or when the driver is removed, the driver only drops clock references and never disables the enabled DFLL clock.

So after this change, if we successful switch to the DFLL, but we fail to register the device, we disable the DFLL. That does not sound good because the CPU will be using that clock at the time. I am not sure what the value in this change really is.

Jon

Signature · 1 line
nvpublic
author
#2 lore raw

Thanks for reviewing.

Yes, after tegra124_cpu_switch_to_dfll() succeeds, the CPU clock is parented to DFLL. The intended cleanup path is not to disable DFLL while the CPU is still using it, but to first reparent the CPU clock back to PLLP and only then disable DFLL.

That is why the helper does:

    clk_set_parent(priv->cpu_clk, priv->pllp_clk);
    clk_disable_unprepare(priv->dfll_clk);

This follows the same ordering as the suspend path, where the driver also switches the CPU clock source to PLLP before disabling DFLL.

2026년 6월 27일 (토) 오전 2:18, Jon Hunter <[email protected]>님이 작성:

Quoted 19 lines · Myeonghun Pak
Quoted 4 lines

tegra124_cpu_switch_to_dfll() enables the DFLL clock before switching the CPU clock parent to it. If cpufreq_dt_pdev_register() fails after that point, or when the driver is removed, the driver only drops clock references and never disables the enabled DFLL clock.

So after this change, if we successful switch to the DFLL, but we fail to register the device, we disable the DFLL. That does not sound good because the CPU will be using that clock at the time. I am not sure what the value in this change really is.

Jon

--
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