clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM
Subsystems (7)
v2 cover clk: sunxi-ng: Add support for Allwinner A733 CCU and PRCM
Add support for the main CCU and the PRCM module (R-CCU) found in the Allwinner A733 SoC. The clock architecture of the A733 is an evolution of the previous A523 design but introduces several significant changes.
One of the key changes is the introduction of a "pll-ref" clock that normalizes the physical oscillator frequency (which can be 19.2MHz, 24MHz, or 26MHz) into a consistent 24MHz reference for the entire clock tree. Additionally, while the A733 inherits many module clock structures from the A523, the MCU_CCU has been removed, and the overall clock tree has been expanded to support more new functional units.
Also update the sunxi-ng SDM (Sigma-Delta Modulation) helper to support a new dual-pattern register design. On the A733, the SDM enable bit has been moved from the main PLL register to a second pattern register (PATTERN1). The driver is updated to handle this register layout to ensure accurate frequency synthesis for "pll-audio0".
The parent clocks for several instances in the main CCU are difficult to determine as the user manual provides limited information on their specific clock sources. In these cases, the implementation follows vendor practices and previous SoC designs, generally defaulting to "hosc" where documentation is lacking. The bus clock gates in the PRCM (R-CCU) are explicitly defined based on the Memory Map in the manual, which clearly associates each module with its respective bus.
---
Changes in v2:
- Rework the clocks property in DT bindings to source hosc directly from the oscillator to adapt to the new RTC binding
- Clean up the SDM dual-pattern helper macro and add the missing enable parameter for pll-audio0
- Number single-instance clocks with 0, e.g. GPU0, VE_ENC0/VE_DEC0,
DRAM0, NAND0, GPADC0, THS0, etc
- Correct 8x PLL post-divider names to 12x for video and DE PLLs (pll-videoX-12x, pll-de-12x)
- Drop gic, cpu-peri, nsi clocks
- Rename clocks: OWA -> SPDIF, USB_REF -> USB01_REF, HDMI_ESM -> HDCP_ESM, PWMCTRL -> PWM
- Mark bus-dram0, ahb-store and mbus-store critical to avoid DMA, MMC and SPI NOR failures when unused clocks are disabled
- Switch PRCM timer clocks to P-only helpers
- Fix bus gate bit positions for UARTs and correct the sysdap register address
- Interleave bus clocks into function clocks
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Junhui Liu (8):
dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support
clk: sunxi-ng: sdm: Add dual patterns support
clk: sunxi-ng: a733: Add PRCM CCU
clk: sunxi-ng: a733: Add PLL clocks support
clk: sunxi-ng: a733: Add bus clocks support
clk: sunxi-ng: a733: Add mod clocks support
clk: sunxi-ng: a733: Add bus clock gates
clk: sunxi-ng: a733: Add reset lines
.../bindings/clock/allwinner,sun60i-a733-ccu.yaml | 107 + drivers/clk/sunxi-ng/Kconfig | 10 + drivers/clk/sunxi-ng/Makefile | 4 + drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c | 273 +++ drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 2360 ++++++++++++++++++++ drivers/clk/sunxi-ng/ccu_sdm.c | 51 +- drivers/clk/sunxi-ng/ccu_sdm.h | 29 +- include/dt-bindings/clock/sun60i-a733-ccu.h | 290 +++ include/dt-bindings/clock/sun60i-a733-r-ccu.h | 39 + include/dt-bindings/reset/sun60i-a733-ccu.h | 129 ++ include/dt-bindings/reset/sun60i-a733-r-ccu.h | 23 + 11 files changed, 3289 insertions(+), 26 deletions(-)
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260202-a733-clk-0d4fc00a9f9c
Best regards,
Signature · 1 line
Junhui Liu <[email protected]>
PATCH v2 1/8 dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support
The CCU and R-CCU (PRCM) modules provide clocks and reset functions for the Allwinner A733 SoC. The clock architecture of the A733 is evolved from the A523, though the root clocking strategy transitions from a static oscillator frequency in the Devicetree to the "hosc" clock, which is determined by choosing from three possible frequencies (19.2MHz, 24MHz, or 26MHz) by the RTC hardware, and finally feeds the CCU and R-CCU.
Additionally, the MCU_CCU module found in previous designs is removed from the A733, and the clock tree is expanded with more clock outputs to support new functional modules.
Signed-off-by Junhui Liu <[email protected]>
--- .../bindings/clock/allwinner,sun60i-a733-ccu.yaml | 107 ++++++++ include/dt-bindings/clock/sun60i-a733-ccu.h | 290 +++++++++++++++++++++ include/dt-bindings/clock/sun60i-a733-r-ccu.h | 39 +++ include/dt-bindings/reset/sun60i-a733-ccu.h | 129 +++++++++ include/dt-bindings/reset/sun60i-a733-r-ccu.h | 23 ++ 5 files changed, 588 insertions(+)
Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml new file +107 -0
@@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/allwinner,sun60i-a733-ccu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A733 Clock Control Unit + +maintainers: + - Junhui Liu <[email protected]> + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + compatible: + enum: + - allwinner,sun60i-a733-ccu + - allwinner,sun60i-a733-r-ccu + + reg: + maxItems: 1 + + clocks: + minItems: 4 + maxItems: 7 + + clock-names: + minItems: 4 + maxItems: 7 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + enum: + - allwinner,sun60i-a733-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (19.2MHz, 24MHz, or 26MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Low Frequency Oscillator fanout + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: losc-fanout + + - if: + properties: + compatible: + enum: + - allwinner,sun60i-a733-r-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (19.2MHz, 24MHz, or 26MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: System 24MHz Clock + - description: Peripherals PLL 0 (200 MHz output) + - description: Peripherals PLL 0 (300 MHz output) + - description: Peripherals PLL 1 (300 MHz output) + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: sys-24m + - const: pll-periph0-200m + - const: pll-periph0-300m + - const: pll-periph1-300m + +additionalProperties: false + +examples: + - | + clock-controller@2002000 { + compatible = "allwinner,sun60i-a733-ccu"; + reg = <0x02002000 0x2000>; + clocks = <&osc>, <&rtc 0>, <&rtc 2>, <&rtc 1>; + clock-names = "hosc", "losc", "iosc", "losc-fanout"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +...
include/dt-bindings/clock/sun60i-a733-ccu.h new file +290 -0
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include/dt-bindings/clock/sun60i-a733-r-ccu.h new file +39 -0
@@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* +* Copyright (C) 2026 Junhui Liu <[email protected]> +*/ + +#ifndef _DT_BINDINGS_CLK_SUN60I_A733_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN60I_A733_R_CCU_H_ + +#define CLK_R_AHB 0 +#define CLK_R_APB0 1 +#define CLK_R_APB1 2 +#define CLK_R_TIMER0 3 +#define CLK_R_TIMER1 4 +#define CLK_R_TIMER2 5 +#define CLK_R_TIMER3 6 +#define CLK_BUS_R_TIMER 7 +#define CLK_BUS_R_TWD 8 +#define CLK_R_PWM 9 +#define CLK_BUS_R_PWM 10 +#define CLK_R_SPI 11 +#define CLK_BUS_R_SPI 12 +#define CLK_BUS_R_MSGBOX 13 +#define CLK_BUS_R_UART0 14 +#define CLK_BUS_R_UART1 15 +#define CLK_BUS_R_I2C0 16 +#define CLK_BUS_R_I2C1 17 +#define CLK_BUS_R_I2C2 18 +#define CLK_BUS_R_PPU 19 +#define CLK_BUS_R_TZMA 20 +#define CLK_BUS_R_CPU_BIST 21 +#define CLK_R_IR_RX 22 +#define CLK_BUS_R_IR_RX 23 +#define CLK_BUS_R_RTC 24 +#define CLK_R_RISCV 25 +#define CLK_BUS_R_RISCV 26 +#define CLK_BUS_R_RISCV_CFG 27 +#define CLK_BUS_R_CPUCFG 28 + +#endif /* _DT_BINDINGS_CLK_SUN60I_A733_R_CCU_H_ */
include/dt-bindings/reset/sun60i-a733-ccu.h new file +129 -0
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include/dt-bindings/reset/sun60i-a733-r-ccu.h new file +23 -0
@@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* +* Copyright (C) 2026 Junhui Liu <[email protected]> +*/ + +#ifndef _DT_BINDINGS_RST_SUN60I_A733_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN60I_A733_R_CCU_H_ + +#define RST_BUS_R_TIMER 0 +#define RST_BUS_R_PWM 1 +#define RST_BUS_R_SPI 2 +#define RST_BUS_R_MSGBOX 3 +#define RST_BUS_R_UART0 4 +#define RST_BUS_R_UART1 5 +#define RST_BUS_R_I2C0 6 +#define RST_BUS_R_I2C1 7 +#define RST_BUS_R_I2C2 8 +#define RST_BUS_R_IR_RX 9 +#define RST_BUS_R_RTC 10 +#define RST_BUS_R_RISCV_CFG 11 +#define RST_BUS_R_CPUCFG 12 + +#endif /* _DT_BINDINGS_RST_SUN60I_A733_R_CCU_H_ */
Signature · 1 line
2.54.0
[email protected]
AI reviewRe: [PATCH v2 1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] The conditionals for 'allwinner,sun60i-a733-ccu' and 'allwinner,sun60i-a733-r-ccu' fail to…
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The conditionals for 'allwinner,sun60i-a733-ccu' and 'allwinner,sun60i-a733-r-ccu' fail to constrain the array lengths of 'clocks' and 'clock-names', leading to incomplete schema validation. --
--- Patch [1]: [PATCH v2 1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support --- commit 8cfed61380df8be01d658a1c9e237ca6deace817
Author: Junhui Liu <[email protected]>
dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support
This commit introduces the device tree bindings for the Allwinner A733 Clock Control Unit (CCU) and R-CCU. It transitions the root clocking strategy to the "hosc" clock and expands the clock tree outputs.
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Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml new file +0
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[ ... ]
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Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml new file +28
-0+ clocks: + minItems: 4 + maxItems: 7 + + clock-names: + minItems: 4 + maxItems: 7 + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + enum: + - allwinner,sun60i-a733-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (19.2MHz, 24MHz, or 26MHz)
Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml line 64
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Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml new file +10
-0+ - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Low Frequency Oscillator fanout + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: losc-fanout
[Severity: Medium]
Since the top-level schema defines maxItems: 7 for clocks and clock-names, does this conditional block need to explicitly define maxItems: 4 for both properties to prevent up to 3 extra clocks from being silently accepted during schema validation?
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Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml new file +18
-0+ + - if: + properties: + compatible: + enum: + - allwinner,sun60i-a733-r-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (19.2MHz, 24MHz, or 26MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: System 24MHz Clock + - description: Peripherals PLL 0 (200 MHz output) + - description: Peripherals PLL 0 (300 MHz output) + - description: Peripherals PLL 1 (300 MHz output)
Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml line 92
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Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml new file +10
-0+ + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: sys-24m + - const: pll-periph0-200m + - const: pll-periph0-300m + - const: pll-periph1-300m
[Severity: Medium]
Similarly, does this conditional block need to explicitly define minItems: 7 for both clocks and clock-names so that incomplete nodes with as few as 4 clocks are rejected by schema validation?
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Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml new file +2
-0+ +additionalProperties: false
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1
Re: [PATCH v2 1/8] dt-bindings: clk: sun60i-a733-ccu: Add allwinner A733 support
In reply to Junhui LiuDocumentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml line 18
Quoted 7 lines · Junhui Liu
Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml new file +7
-0+properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 +
Please order according to DTS coding style. compatible is ALWAYS the first, then reg. Then name ordering, so reset-cells go to the end.
Quoted 9 lines
Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml new file +9
-0+ compatible: + enum: + - allwinner,sun60i-a733-ccu + - allwinner,sun60i-a733-r-ccu + + reg: + maxItems: 1 + + clocks:
Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml line 37
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Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml new file +10
-0+ minItems: 4 + maxItems: 7 + + clock-names: + minItems: 4 + maxItems: 7 + +required: + - "#clock-cells" + - "#reset-cells"
As well.
include/dt-bindings/clock/sun60i-a733-ccu.h
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Documentation/devicetree/bindings/clock/allwinner,sun60i-a733-ccu.yaml new file +70
-0+ - compatible + - reg + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + enum: + - allwinner,sun60i-a733-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (19.2MHz, 24MHz, or 26MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Low Frequency Oscillator fanout + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: losc-fanout + + - if: + properties: + compatible: + enum: + - allwinner,sun60i-a733-r-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (19.2MHz, 24MHz, or 26MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: System 24MHz Clock + - description: Peripherals PLL 0 (200 MHz output) + - description: Peripherals PLL 0 (300 MHz output) + - description: Peripherals PLL 1 (300 MHz output) + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: sys-24m + - const: pll-periph0-200m + - const: pll-periph0-300m + - const: pll-periph1-300m + +additionalProperties: false + +examples: + - | + clock-controller@2002000 { + compatible = "allwinner,sun60i-a733-ccu"; + reg = <0x02002000 0x2000>; + clocks = <&osc>, <&rtc 0>, <&rtc 2>, <&rtc 1>; + clock-names = "hosc", "losc", "iosc", "losc-fanout"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +...include/dt-bindings/clock/sun60i-a733-ccu.h new file +0
-0
Filename must match compatible.
include/dt-bindings/clock/sun60i-a733-ccu.h line 1
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include/dt-bindings/clock/sun60i-a733-ccu.h new file +1
-0@@ -0,0 +1,290 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
Why different license than the binding?
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include/dt-bindings/clock/sun60i-a733-ccu.h new file +2
-0+/* +* Copyright (C) 2026 Junhui Liu <[email protected]>
...
include/dt-bindings/clock/sun60i-a733-r-ccu.h
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include/dt-bindings/clock/sun60i-a733-ccu.h new file +21
-0+#define CLK_BUS_DSC 257 +#define CLK_CSI_MASTER0 258 +#define CLK_CSI_MASTER1 259 +#define CLK_CSI_MASTER2 260 +#define CLK_CSI 261 +#define CLK_BUS_CSI 262 +#define CLK_ISP 263 +#define CLK_RES_DCAP_24M 264 +#define CLK_APB2JTAG 265 +#define CLK_FANOUT_24M 266 +#define CLK_FANOUT_12M 267 +#define CLK_FANOUT_16M 268 +#define CLK_FANOUT_25M 269 +#define CLK_FANOUT_27M 270 +#define CLK_FANOUT_PCLK 271 +#define CLK_FANOUT0 272 +#define CLK_FANOUT1 273 +#define CLK_FANOUT2 274 +#define CLK_FANOUT3 275 + +#endif /* _DT_BINDINGS_CLK_SUN60I_A733_CCU_H_ */ include/dt-bindings/clock/sun60i-a733-r-ccu.h new file +0
-0
Here as well and so on (other places as well).
Best regards,
Krzysztof
PATCH v2 2/8 clk: sunxi-ng: sdm: Add dual patterns support
In reply to Junhui LiuOn newer Allwinner platforms like the A733, the Sigma-Delta Modulation (SDM) control logic is more complex. The SDM enable bit, which was previously located in the PLL register, is now moved to a second pattern register (PATTERN1).
To support this, rename the existing "tuning" members to "pattern0" to align with the datasheet, and introduce the _SUNXI_CCU_SDM_DUAL_PAT macro to provide pattern1 register support. Related operations are also updated.
Tested-by Jerome Brunet <[email protected]>
Signed-off-by Junhui Liu <[email protected]>
--- drivers/clk/sunxi-ng/ccu_sdm.c | 51 +++++++++++++++++++++++++++++------------- drivers/clk/sunxi-ng/ccu_sdm.h | 29 +++++++++++++++--------- 2 files changed, 54 insertions(+), 26 deletions(-)
drivers/clk/sunxi-ng/ccu_sdm.c +36 -15
@@ -18,7 +18,10 @@ bool ccu_sdm_helper_is_enabled(struct ccu_common *common,if (sdm->enable && !(readl (common->base + common->reg) & sdm->enable))return false; -return !!(readl (common->base + sdm->tuning_reg) & sdm->tuning_enable); +if (sdm->pat1_enable && !(readl (common->base + sdm->pat1_reg) & sdm->pat1_enable)) +return false; + +return !!(readl (common->base + sdm->pat0_reg) & sdm->pat0_enable); }EXPORT_SYMBOL_NS_GPL (ccu_sdm_helper_is_enabled,"SUNXI_CCU" );
@@ -37,18 +40,27 @@ void ccu_sdm_helper_enable(struct ccu_common *common,for (i =0 ; i < sdm->table_size; i++)if (sdm->table[i].rate == rate)writel (sdm->table[i].pattern, - common->base + sdm->tuning_reg); + common->base + sdm->pat0_reg);/* Make sure SDM is enabled */ spin_lock_irqsave (common->lock, flags); - reg =readl (common->base + sdm->tuning_reg); -writel (reg | sdm->tuning_enable, common->base + sdm->tuning_reg); + reg =readl (common->base + sdm->pat0_reg); +writel (reg | sdm->pat0_enable, common->base + sdm->pat0_reg);spin_unlock_irqrestore (common->lock, flags); -spin_lock_irqsave (common->lock, flags); - reg =readl (common->base + common->reg); -writel (reg | sdm->enable, common->base + common->reg); -spin_unlock_irqrestore (common->lock, flags); +if (sdm->enable) { +spin_lock_irqsave (common->lock, flags); + reg =readl (common->base + common->reg); +writel (reg | sdm->enable, common->base + common->reg); +spin_unlock_irqrestore (common->lock, flags); + } + +if (sdm->pat1_enable) { +spin_lock_irqsave (common->lock, flags); + reg =readl (common->base + sdm->pat1_reg); +writel (reg | sdm->pat1_enable, common->base + sdm->pat1_reg); +spin_unlock_irqrestore (common->lock, flags); + } }EXPORT_SYMBOL_NS_GPL (ccu_sdm_helper_enable,"SUNXI_CCU" );
@@ -61,14 +73,23 @@ void ccu_sdm_helper_disable(struct ccu_common *common,if (!(common->features &CCU_FEATURE_SIGMA_DELTA_MOD ))return ; -spin_lock_irqsave (common->lock, flags); - reg =readl (common->base + common->reg); -writel (reg & ~sdm->enable, common->base + common->reg); -spin_unlock_irqrestore (common->lock, flags); +if (sdm->enable) { +spin_lock_irqsave (common->lock, flags); + reg =readl (common->base + common->reg); +writel (reg & ~sdm->enable, common->base + common->reg); +spin_unlock_irqrestore (common->lock, flags); + } + +if (sdm->pat1_enable) { +spin_lock_irqsave (common->lock, flags); + reg =readl (common->base + sdm->pat1_reg); +writel (reg & ~sdm->pat1_enable, common->base + sdm->pat1_reg); +spin_unlock_irqrestore (common->lock, flags); + }spin_lock_irqsave (common->lock, flags); - reg =readl (common->base + sdm->tuning_reg); -writel (reg & ~sdm->tuning_enable, common->base + sdm->tuning_reg); + reg =readl (common->base + sdm->pat0_reg); +writel (reg & ~sdm->pat0_enable, common->base + sdm->pat0_reg);spin_unlock_irqrestore (common->lock, flags); }EXPORT_SYMBOL_NS_GPL (ccu_sdm_helper_disable,"SUNXI_CCU" );
@@ -123,7 +144,7 @@ unsigned long ccu_sdm_helper_read_rate(struct ccu_common *common,pr_debug ("%s: clock is sigma-delta modulated\n" ,clk_hw_get_name (&common->hw)); - reg =readl (common->base + sdm->tuning_reg); + reg =readl (common->base + sdm->pat0_reg);pr_debug ("%s: pattern reg is 0x%x" ,clk_hw_get_name (&common->hw), reg);
drivers/clk/sunxi-ng/ccu_sdm.h +18 -11
@@ -33,21 +33,28 @@ struct ccu_sdm_internal {u32 table_size;/* early SoCs don't have the SDM enable bit in the PLL register */ u32 enable; -/* second enable bit in tuning register */ -u32 tuning_enable; -u16 tuning_reg; +/* second enable bit in pattern0 register */ +u32 pat0_enable; +u16 pat0_reg; +/* on some platforms, the sdm enable bit in pattern1 register */ +u32 pat1_enable; +u16 pat1_reg; }; -#define _SUNXI_CCU_SDM (_table, _enable, \ - _reg, _reg_enable) \ - { \ - .table = _table, \ - .table_size = ARRAY_SIZE(_table), \ - .enable = _enable, \ - .tuning_enable = _reg_enable, \ - .tuning_reg = _reg, \ +#define _SUNXI_CCU_SDM_DUAL_PAT (_table, _enable, _pat0, _pat0_enable, _pat1, _pat1_enable) \ + { \ + .table = _table, \ + .table_size = ARRAY_SIZE(_table), \ + .enable = _enable, \ + .pat0_enable = _pat0_enable, \ + .pat0_reg = _pat0, \ + .pat1_enable = _pat1_enable, \ + .pat1_reg = _pat1, \ } +#define _SUNXI_CCU_SDM (_table, _enable, _pat0, _pat0_enable) \ + _SUNXI_CCU_SDM_DUAL_PAT(_table, _enable, _pat0, _pat0_enable, 0, 0) +bool ccu_sdm_helper_is_enabled (struct ccu_common *common,struct ccu_sdm_internal *sdm); void ccu_sdm_helper_enable(struct ccu_common *common,
Signature · 1 line
2.54.0
PATCH v2 3/8 clk: sunxi-ng: a733: Add PRCM CCU
In reply to Junhui LiuAdd support for the Power Reset Clock Management (PRCM) module found in the Allwinner A733 SoC. This clock controller manages the clock control and reset functions for device modules within the CPUS domain.
The PRCM module includes the management of three primary buses: r-ahb, r-apb0, and r-apb1. It also provides clocking for several key peripherals, such as R-UART, R-I2C, R-SPI, and the R-RISCV subsystem. Additionally, the reset lines for these modules are integrated.
Tested-by Jerome Brunet <[email protected]>
Signed-off-by Junhui Liu <[email protected]>
--- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c | 273 +++++++++++++++++++++++++++++++ 3 files changed, 280 insertions(+)
drivers/clk/sunxi-ng/Kconfig +5 -0
@@ -67,6 +67,11 @@ config SUN55I_A523_R_CCU default ARCH_SUNXI depends on ARM64 || COMPILE_TEST +config SUN60I_A733_R_CCU + tristate "Support for the Allwinner A733 PRCM CCU" + default ARCH_SUNXI + depends on ARM64 || COMPILE_TEST + config SUN4I_A10_CCU tristate "Support for the Allwinner A10/A20 CCU" default ARCH_SUNXI
drivers/clk/sunxi-ng/Makefile +2 -0
@@ -36,6 +36,7 @@ obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o obj-$(CONFIG_SUN55I_A523_CCU) += sun55i-a523-ccu.o obj-$(CONFIG_SUN55I_A523_MCU_CCU) += sun55i-a523-mcu-ccu.o obj-$(CONFIG_SUN55I_A523_R_CCU) += sun55i-a523-r-ccu.o +obj-$(CONFIG_SUN60I_A733_R_CCU) += sun60i-a733-r-ccu.o obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o obj-$(CONFIG_SUN6I_A31_CCU) += sun6i-a31-ccu.o
@@ -64,6 +65,7 @@ sun50i-h616-ccu-y += ccu-sun50i-h616.o sun55i-a523-ccu-y += ccu-sun55i-a523.o sun55i-a523-mcu-ccu-y += ccu-sun55i-a523-mcu.o sun55i-a523-r-ccu-y += ccu-sun55i-a523-r.o +sun60i-a733-r-ccu-y += ccu-sun60i-a733-r.o sun4i-a10-ccu-y += ccu-sun4i-a10.o sun5i-ccu-y += ccu-sun5i.o sun6i-a31-ccu-y += ccu-sun6i-a31.o
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c new file +273 -0
273 lines not on this page · raw message
Signature · 1 line
2.54.0
[email protected]
AI reviewRe: [PATCH v2 3/8] clk: sunxi-ng: a733: Add PRCM CCU
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [Medium] Missing reset controls for hardware modules R-TWD, R-PPU, R-TZMA, and R-CPU-BIST. - [Medium] The…
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Missing reset controls for hardware modules R-TWD, R-PPU, R-TZMA, and R-CPU-BIST.
- [Medium] The mux shift for r_cpu_timer0..3 is incorrectly set to 4, which is anomalous for PRCM CCU clocks and likely a copy-paste error. --
--- Patch [3]: [PATCH v2 3/8] clk: sunxi-ng: a733: Add PRCM CCU --- commit 52650c9e3c767283edee5eb6338cdb409a63f50e
Author: Junhui Liu <[email protected]>
clk: sunxi-ng: a733: Add PRCM CCU
Add support for the Power Reset Clock Management (PRCM) module found in the Allwinner A733 SoC. This clock controller manages the clock control and reset functions for device modules within the CPUS domain.
Quoted 5 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c new file +0
-0
[ ... ]
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c new file +10
-0+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0", r_apb_parents, 0x100, +1 ,3 ,/* P */ +4 ,3 ,/* mux */ +BIT (0 ),/* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1", r_apb_parents, 0x104, +1 ,3 ,/* P */ +4 ,3 ,/* mux */ +BIT (0 ),/* gate */ + 0);
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c line 72
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c new file +10
-0+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer2, "r-timer2", r_apb_parents, 0x108, +1 ,3 ,/* P */ +4 ,3 ,/* mux */ +BIT (0 ),/* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer3, "r-timer3", r_apb_parents, 0x10c, +1 ,3 ,/* P */ +4 ,3 ,/* mux */ +BIT (0 ),/* gate */ + 0);
[Severity: Medium]
Are the mux shift values for r_cpu_timer0 through r_cpu_timer3 correct?
Most of the other PRCM clocks in this driver use bit 24 for the mux shift. If the hardware actually expects the mux configuration at bit 24, writing to bits 4-6 might fail to select the correct parent clock and could accidentally overwrite other configuration bits, resulting in incorrect timer frequencies.
[ ... ]
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c line 220
Quoted 3 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c new file +3
-0+static struct ccu_reset_map sun60i_a733_r_ccu_resets[] = { + [RST_BUS_R_TIMER ] = {0x11c ,BIT (16 ) }, + [RST_BUS_R_PWM ] = {0x13c ,BIT (16 ) },
[Severity: Medium]
Should there be reset controls for the R-TWD, R-PPU, R-TZMA, and R-CPU-BIST modules mapped here?
These modules have clock gate offsets defined (0x12c, 0x1ac, 0x1b0, 0x1bc) elsewhere in the driver, but are omitted from this reset list. If they do have corresponding reset lines, missing them could prevent their drivers from taking the hardware out of reset during initialization, potentially causing uninitialized states or bus hangs upon access.
Quoted 2 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c new file +2
-0+ [RST_BUS_R_SPI] = { 0x15c, BIT(16) }, + [RST_BUS_R_MSGBOX] = { 0x17c, BIT(16) },
[ ... ]
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=3
Re: [PATCH v2 3/8] clk: sunxi-ng: a733: Add PRCM CCU
Quoted 2 lines · On Sun, 12 Jul 2026 08:13:39 +0000 [email protected] wrote:
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Missing reset controls for hardware modules R-TWD, R-PPU, R-TZMA, and R-CPU-BIST.
Those devices indeed have no reset controls, so the code is right.
Quoted 1 line
- [Medium] The mux shift for
r_cpu_timer0..3is incorrectly set to 4, which is anomalous for PRCM CCU clocks and likely a copy-paste error.
Those timer control register differs from the other ones, so the code is correct: CLK_SRC_SEL is bits [6:4], S_TIMER<n>_CLK_GATING is bit 0.
Cheers,
Andre
Quoted 67 lines
--
--- Patch [3]: [PATCH v2 3/8] clk: sunxi-ng: a733: Add PRCM CCU --- commit
52650c9e3c767283edee5eb6338cdb409a63f50e
Author: Junhui Liu <[email protected]>clk: sunxi-ng: a733: Add PRCM CCU
Add support for the Power Reset Clock Management (PRCM) module found in the Allwinner A733 SoC. This clock controller manages the clock control and reset functions for device modules within the CPUS domain.
Quoted 5 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c new file +0
-0[ ... ]
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c new file +10
-0+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer0, "r-timer0", r_apb_parents, 0x100, +1 ,3 ,/* P */ +4 ,3 ,/* mux */ +BIT (0 ),/* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer1, "r-timer1", r_apb_parents, 0x104, +1 ,3 ,/* P */ +4 ,3 ,/* mux */ +BIT (0 ),/* gate */ + 0);drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c line 72
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c new file +10
-0+static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer2, "r-timer2", r_apb_parents, 0x108, +1 ,3 ,/* P */ +4 ,3 ,/* mux */ +BIT (0 ),/* gate */ + 0); +static SUNXI_CCU_P_DATA_WITH_MUX_GATE(r_cpu_timer3, "r-timer3", r_apb_parents, 0x10c, +1 ,3 ,/* P */ +4 ,3 ,/* mux */ +BIT (0 ),/* gate */ + 0);[Severity: Medium]
Are the mux shift values forr_cpu_timer0throughr_cpu_timer3correct?Most of the other PRCM clocks in this driver use bit 24 for the mux shift. If the hardware actually expects the mux configuration at bit 24, writing to bits 4-6 might fail to select the correct parent clock and could accidentally overwrite other configuration bits, resulting in incorrect timer frequencies.
[ ... ]
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c line 220
Quoted 3 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c new file +3
-0+static struct ccu_reset_map sun60i_a733_r_ccu_resets[] = { + [RST_BUS_R_TIMER ] = {0x11c ,BIT (16 ) }, + [RST_BUS_R_PWM ] = {0x13c ,BIT (16 ) },[Severity: Medium]
Should there be reset controls for the R-TWD, R-PPU, R-TZMA, and R-CPU-BIST modules mapped here?These modules have clock gate offsets defined (
0x12c,0x1ac,0x1b0,0x1bc) elsewhere in the driver, but are omitted from this reset list. If they do have corresponding reset lines, missing them could prevent their drivers from taking the hardware out of reset during initialization, potentially causing uninitialized states or bus hangs upon access.Quoted 2 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733-r.c new file +2
-0+ [RST_BUS_R_SPI] = { 0x15c, BIT(16) }, + [RST_BUS_R_MSGBOX] = { 0x17c, BIT(16) },[ ... ]
Re: [PATCH v2 3/8] clk: sunxi-ng: a733: Add PRCM CCU
In reply to Junhui LiuHi Junhui,
I re-reviewed patch 3 in v2 after Andre pointed out that my RFC reply lacked a formal tag.
I compared the RFC and v2 PRCM drivers and rechecked v2 against the Allwinner A733 User Manual V0.92, chapter 4.2.5. I checked all 11 programmable clock definitions (register offsets and divider/mux/gate fields), all 18 bus-gate definitions, and all 13 reset-map entries. They match the manual.
The RFC-to-v2 changes do not invalidate that check: the four R timer clocks move from the MP helper with no M field to the P-only helper while keeping their offsets and P/mux/gate fields unchanged, and the R PWM identifiers are renamed while keeping their offset/mux/gate fields unchanged. I also checked the gate-only BGRs for R-TWD, R-PPU, R-TZMA, and R-CPU-BIST; the manual defines gate bit 0 but no reset bit for those registers, matching v2.
Reviewed-by Enzo Adriano <[email protected]>
This analysis was done with AI assistance and each finding was checked against the cited sources.
Thanks,
Enzo
PATCH v2 4/8 clk: sunxi-ng: a733: Add PLL clocks support
In reply to Junhui LiuAdd PLL clock support for the main CCU of the Allwinner A733 SoC. The structure is mostly similar to the sun55i, with the addition of a PLL_REF clock that normalizes the hardware-detected DCXO/hosc frequency (19.2MHz, 24MHz, or 26MHz) into a consistent 24MHz reference for all subsequent PLLs.
The behaviors of PLL_AUDIO0 and PLL_AUDIO1 are ported from the vendor driver. Specifically, PLL_AUDIO0 is configured with SDM parameters to provide a 22.5792MHz * 4 output, while PLL_AUDIO1 is integrated into the main CCU without using SDM.
Tested-by Jerome Brunet <[email protected]>
Signed-off-by Junhui Liu <[email protected]>
--- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 539 +++++++++++++++++++++++++++++++++ 3 files changed, 546 insertions(+)
drivers/clk/sunxi-ng/Kconfig +5 -0
@@ -67,6 +67,11 @@ config SUN55I_A523_R_CCU default ARCH_SUNXI depends on ARM64 || COMPILE_TEST +config SUN60I_A733_CCU + tristate "Support for the Allwinner A733 CCU" + default ARCH_SUNXI + depends on ARM64 || COMPILE_TEST + config SUN60I_A733_R_CCU tristate "Support for the Allwinner A733 PRCM CCU" default ARCH_SUNXI
drivers/clk/sunxi-ng/Makefile +2 -0
@@ -36,6 +36,7 @@ obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o obj-$(CONFIG_SUN55I_A523_CCU) += sun55i-a523-ccu.o obj-$(CONFIG_SUN55I_A523_MCU_CCU) += sun55i-a523-mcu-ccu.o obj-$(CONFIG_SUN55I_A523_R_CCU) += sun55i-a523-r-ccu.o +obj-$(CONFIG_SUN60I_A733_CCU) += sun60i-a733-ccu.o obj-$(CONFIG_SUN60I_A733_R_CCU) += sun60i-a733-r-ccu.o obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o
@@ -65,6 +66,7 @@ sun50i-h616-ccu-y += ccu-sun50i-h616.o sun55i-a523-ccu-y += ccu-sun55i-a523.o sun55i-a523-mcu-ccu-y += ccu-sun55i-a523-mcu.o sun55i-a523-r-ccu-y += ccu-sun55i-a523-r.o +sun60i-a733-ccu-y += ccu-sun60i-a733.o sun60i-a733-r-ccu-y += ccu-sun60i-a733-r.o sun4i-a10-ccu-y += ccu-sun4i-a10.o sun5i-ccu-y += ccu-sun5i.o
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +539 -0
539 lines not on this page · raw message
Signature · 1 line
2.54.0
[email protected]
AI reviewRe: [PATCH v2 4/8] clk: sunxi-ng: a733: Add PLL clocks support
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [High] The `hws` flexible array in `sun60i_a733_hw_clks` is allocated with insufficient size, leading to…
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] The hws flexible array in sun60i_a733_hw_clks is allocated with insufficient size, leading to an out-of-bounds read in sunxi_ccu_probe.
- [Medium] The driver is missing the MODULE_DEVICE_TABLE macro, which prevents it from being autoloaded by udev when built as a loadable module. --
--- Patch [4]: [PATCH v2 4/8] clk: sunxi-ng: a733: Add PLL clocks support --- commit 803dab2e98d8379ce658bcbb6ef611389e990997
Author: Junhui Liu <[email protected]>
clk: sunxi-ng: a733: Add PLL clocks support
Add PLL clock support for the main CCU of the Allwinner A733 SoC. The structure is mostly similar to the sun55i, with the addition of a PLL_REF clock that normalizes the hardware-detected DCXO/hosc frequency (19.2MHz, 24MHz, or 26MHz) into a consistent 24MHz reference for all subsequent PLLs.
Quoted 5 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +0
-0
[ ... ]
Quoted 3 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +3
-0+static struct clk_hw_onecell_data sun60i_a733_hw_clks = { + .hws = { + [CLK_PLL_REF ] = &pll_ref_clk.common.hw,
[ ... ]
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 462
Quoted 5 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +5
-0+ [CLK_PLL_DE_4X] = &pll_de_4x_clk.common.hw, + [CLK_PLL_DE_3X] = &pll_de_3x_clk.common.hw, + }, + .num = CLK_FANOUT3 + 1, +};
[Severity: High]
Since this structure statically initializes a flexible array, the compiler will only allocate space for the explicitly initialized elements (up to CLK_PLL_DE_3X, which is 43 elements). However, .num is set to CLK_FANOUT3 + 1.
Will this cause sunxi_ccu_probe() to read out-of-bounds when iterating up to .num?
If the out-of-bounds memory is non-NULL, could this lead to a panic when dereferencing the pointer?
[ ... ]
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 525
Quoted 4 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +4
-0+static const struct of_device_id sun60i_a733_ccu_ids[] = { + { .compatible ="allwinner,sun60i-a733-ccu" }, + {/* sentinel */ } +};
[Severity: Medium]
When this driver is built as a loadable module, will it fail to autoload?
It appears to be missing a MODULE_DEVICE_TABLE(of, sun60i_a733_ccu_ids) declaration to export the alias metadata for udev.
Quoted 9 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +9
-0+ +static struct platform_driver sun60i_a733_ccu_driver = { + .probe = sun60i_a733_ccu_probe, + .driver = { + .name ="sun60i-a733-ccu" , + .suppress_bind_attrs = true, + .of_match_table = sun60i_a733_ccu_ids, + }, +};
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=4
Chen-Yu Tsai
maintainerRe: [PATCH v2 4/8] clk: sunxi-ng: a733: Add PLL clocks support
In reply to Junhui Liu(trimmed recipient list a bit)
Quoted 69 lines · Junhui Liu
Add PLL clock support for the main CCU of the Allwinner A733 SoC. The structure is mostly similar to the sun55i, with the addition of a
PLL_REFclock that normalizes the hardware-detected DCXO/hosc frequency (19.2MHz, 24MHz, or 26MHz) into a consistent 24MHz reference for all subsequent PLLs.The behaviors of
PLL_AUDIO0andPLL_AUDIO1are ported from the vendor driver. Specifically,PLL_AUDIO0is configured with SDM parameters to provide a 22.5792MHz * 4 output, whilePLL_AUDIO1is integrated into the main CCU without using SDM.Tested-by Jerome Brunet <[email protected]>Signed-off-by Junhui Liu <[email protected]>--- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 539 +++++++++++++++++++++++++++++++++ 3 files changed, 546 insertions(+)drivers/clk/sunxi-ng/Kconfig +5
-0@@ -67,6 +67,11 @@ config SUN55I_A523_R_CCU default ARCH_SUNXI depends on ARM64 || COMPILE_TEST +config SUN60I_A733_CCU + tristate "Support for the Allwinner A733 CCU" + default ARCH_SUNXI + depends on ARM64 || COMPILE_TEST + config SUN60I_A733_R_CCU tristate "Support for the Allwinner A733 PRCM CCU" default ARCH_SUNXIdrivers/clk/sunxi-ng/Makefile +2
-0@@ -36,6 +36,7 @@ obj-$(CONFIG_SUN50I_H616_CCU) += sun50i-h616-ccu.o obj-$(CONFIG_SUN55I_A523_CCU) += sun55i-a523-ccu.o obj-$(CONFIG_SUN55I_A523_MCU_CCU) += sun55i-a523-mcu-ccu.o obj-$(CONFIG_SUN55I_A523_R_CCU) += sun55i-a523-r-ccu.o +obj-$(CONFIG_SUN60I_A733_CCU) += sun60i-a733-ccu.o obj-$(CONFIG_SUN60I_A733_R_CCU) += sun60i-a733-r-ccu.o obj-$(CONFIG_SUN4I_A10_CCU) += sun4i-a10-ccu.o obj-$(CONFIG_SUN5I_CCU) += sun5i-ccu.o@@ -65,6 +66,7 @@ sun50i-h616-ccu-y += ccu-sun50i-h616.o sun55i-a523-ccu-y += ccu-sun55i-a523.o sun55i-a523-mcu-ccu-y += ccu-sun55i-a523-mcu.o sun55i-a523-r-ccu-y += ccu-sun55i-a523-r.o +sun60i-a733-ccu-y += ccu-sun60i-a733.o sun60i-a733-r-ccu-y += ccu-sun60i-a733-r.o sun4i-a10-ccu-y += ccu-sun4i-a10.o sun5i-ccu-y += ccu-sun5i.odrivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +7
-0@@ -0,0 +1,539 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* +* Copyright (C) 2023 [email protected] +* Copyright (C) 2026 Junhui Liu <[email protected]> +* Based on the A523 CCU driver: +* Copyright (C) 2023-2024 Arm Ltd. +*/
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 17
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +10
-0+ +#include <linux/clk-provider.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/platform_device.h> + +#include <dt-bindings/clock/sun60i-a733-ccu.h> +#include <dt-bindings/reset/sun60i-a733-ccu.h> + +#include "../clk.h"
What do you need this for?
Quoted 68 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +68
-0+ +#include "ccu_common.h" + +#include "ccu_div.h" +#include "ccu_mult.h" +#include "ccu_nkmp.h" +#include "ccu_nm.h" + +/* +* The DCXO oscillator, the root of most of the clock tree, which may be +* 19.2MHz, 24MHz, or 26MHz. +*/ +static const struct clk_parent_data hosc[] = { + { .fw_name ="hosc" } +}; + +/************************************************************************** +* PLLs * +**************************************************************************/ + +/* +* Undocumented, taken from the vendor kernel. +* PLL_REF normalizes the DCXO frequency to a 24MHz reference for downstream +* PLLs. +*/ +#define SUN60I_A733_PLL_REF_REG 0x000 +static struct ccu_nkmp pll_ref_clk = { + .enable =BIT (27 ), + .lock =BIT (28 ), + .n =_SUNXI_CCU_MULT (8 ,8 ), + .m =_SUNXI_CCU_DIV (16 ,7 ),/* output divider */ + .p =_SUNXI_CCU_DIV (1 ,1 ),/* input divider */ + .common = { + .reg =SUN60I_A733_PLL_REF_REG , + .hw.init =CLK_HW_INIT_PARENTS_DATA ("pll-ref" , hosc, + &ccu_nkmp_ops, +CLK_SET_RATE_GATE ), + }, +}; + +/* +* Most clock-defining macros expect an *array* of parent clocks, even if +* they do not contain a muxer to select between different parents. +* The macros ending in just _HW take a simple clock pointer, but then create +* a single-entry array out of that. The macros using _HWS take such an +* array (even when it is a single entry one), this avoids having those +* helper arrays created inside *every* clock definition. +* This means for every clock that is referenced more than once it is +* useful to create such a dummy array and use _HWS. +*/ +static const struct clk_hw *pll_ref_hws[] = { + &pll_ref_clk.common.hw +}; + +#define SUN60I_A733_PLL_DDR_REG 0x020 +static struct ccu_nkmp pll_ddr_clk = { + .enable =BIT (27 ), + .lock =BIT (28 ), + .n =_SUNXI_CCU_MULT_MIN (8 ,8 ,11 ), + .m =_SUNXI_CCU_DIV (20 ,3 ),/* output divider */ + .p =_SUNXI_CCU_DIV (1 ,1 ),/* input divider */ + .common = { + .reg =SUN60I_A733_PLL_DDR_REG , + .hw.init =CLK_HW_INIT_PARENTS_HW ("pll-ddr" , pll_ref_hws, + &ccu_nkmp_ops, +CLK_SET_RATE_GATE | +CLK_IS_CRITICAL ), + },
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 95
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +10
-0+}; + +/* +* There is no actual clock output with that frequency (2.4 GHz), instead it +* has multiple outputs with adjustable dividers from that base frequency. +* Model them separately as divider clocks based on that parent here. +*/ +#define SUN60I_A733_PLL_PERIPH0_REG 0x0a0 +static struct ccu_nm pll_periph0_4x_clk = { + .enable =BIT (25 ) |BIT (26 ) |BIT (27 ),
The gate helper sort of expects this to be just one bit. And the three bits here are for the three individual outputs (2x, 800M, 480M). I think you should move the bits to the individual outputs, and use BIT(31) here instead (or just leave out the enable bit for this one).
Quoted 23 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +23
-0+ .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = SUN60I_A733_PLL_PERIPH0_REG, + .hw.init =CLK_HW_INIT_PARENTS_HW ("pll-periph0-4x" , + pll_ref_hws, &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_periph0_4x_hws[] = { + &pll_periph0_4x_clk.common.hw +}; + +static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x", pll_periph0_4x_hws, + SUN60I_A733_PLL_PERIPH0_REG, 20, 3, 0); +static const struct clk_hw *pll_periph0_2x_hws[] = { + &pll_periph0_2x_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M", pll_periph0_4x_hws, + SUN60I_A733_PLL_PERIPH0_REG, 16, 3, 0); +static SUNXI_CCU_M_HWS(pll_periph0_480M_clk, "pll-periph0-480M", pll_periph0_4x_hws,
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 128
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +10
-0+ SUN60I_A733_PLL_PERIPH0_REG, 2, 3, 0); +static const struct clk_hw *pll_periph0_480M_hws[] = { + &pll_periph0_480M_clk.common.hw +}; +static CLK_FIXED_FACTOR_HWS(pll_periph0_600M_clk, "pll-periph0-600M", + pll_periph0_2x_hws, 2, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph0_400M_clk, "pll-periph0-400M", + pll_periph0_2x_hws, 3, 1, 0); +static CLK_FIXED_FACTOR_HWS(pll_periph0_300M_clk, "pll-periph0-300M", + pll_periph0_2x_hws, 4, 1, 0);
Technically this is divided from the 600M one.
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 130
Quoted 2 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +2
-0+static CLK_FIXED_FACTOR_HWS(pll_periph0_200M_clk, "pll-periph0-200M", + pll_periph0_2x_hws, 6, 1, 0);
This one from the 400M one.
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 132
Quoted 2 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +2
-0+static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, "pll-periph0-150M", + pll_periph0_2x_hws, 8, 1, 0);
This one from the 300M one.
The same comments apply to PLL periph1 as well.
[...]
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 196
Quoted 3 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +3
-0+#define SUN60I_A733_PLL_VIDEO0_REG 0x120 +static struct ccu_nm pll_video0_12x_clk = { + .enable =BIT (26 ) |BIT (27 ),
Same thing as peri0. The gates are for the individual outputs. They should be modeled as such. Also applies to the other video PLLs.
[...]
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +10
-0+/* +* PLL_AUDIO0 has a m1 divider in addition to the usual N, M factors. +* Since we only need some fixed frequency from this PLL (22.5792MHz x 4), +* ignore the divider and force it to 1 (encoded as 0), in the probe function +* below. +* The M factor must be an even number to produce a 50% duty cycle output. +*/ +#define SUN60I_A733_PLL_AUDIO0_REG 0x260 +static struct ccu_sdm_setting pll_audio0_sdm_table[] = { + { .rate =90316800 , .pattern =0xa002872b , .m =20 , .n =75 },/* 22.5792 * 4 */
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 309
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +10
-0+}; + +static struct ccu_nm pll_audio0_4x_clk = { + .enable =BIT (27 ), + .lock =BIT (28 ), + .n =_SUNXI_CCU_MULT_MIN (8 ,8 ,11 ), + .m =_SUNXI_CCU_DIV (16 ,7 ), + .sdm =_SUNXI_CCU_SDM_DUAL_PAT (pll_audio0_sdm_table,0 , +0x268 ,BIT (31 ), +0x26c ,BIT (27 ) |BIT (31 )),
Ideally we should call this the "new fractional" mode. But that's probably a different subject.
Quoted 7 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +7
-0+ .common = { + .reg = SUN60I_A733_PLL_AUDIO0_REG, + .features = CCU_FEATURE_SIGMA_DELTA_MOD, + .hw.init =CLK_HW_INIT_PARENTS_HW ("pll-audio0-4x" , pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + },
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 326
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +10
-0+}; + +#define SUN60I_A733_PLL_AUDIO1_REG 0x280 +static struct ccu_nm pll_audio1_clk = { + .enable =BIT (27 ), + .lock =BIT (28 ), + .n =_SUNXI_CCU_MULT_MIN (8 ,8 ,11 ), + .m =_SUNXI_CCU_DIV (1 ,1 ),/* input divider */ + .common = { + .reg =SUN60I_A733_PLL_AUDIO1_REG ,
You should still fill in the CCU_FEATURE_SIGMA_DELTA_MOD flag and .sdm field. Even though you aren't using it here, it could have been left on somehow, and if the kernel doesn't know about it, it can't turn it off, and then the clock coming out of it won't be correct.
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 339
Quoted 13 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +13
-0+ .hw.init = CLK_HW_INIT_PARENTS_HW("pll-audio1", pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_audio1_hws[] = { + &pll_audio1_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_audio1_div2_clk, "pll-audio1-div2", pll_audio1_hws, + SUN60I_A733_PLL_AUDIO1_REG, 20, 3, 0); +static SUNXI_CCU_M_HWS(pll_audio1_div5_clk, "pll-audio1-div5", pll_audio1_hws, + SUN60I_A733_PLL_AUDIO1_REG, 16, 3, 0);
Perhaps these should be made fixed? Otherwise the names don't apply correctly.
Quoted 9 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +9
-0+ +#define SUN60I_A733_PLL_NPU_REG 0x2a0 +static struct ccu_nkmp pll_npu_clk = { + .enable =BIT (27 ), + .lock =BIT (28 ), + .n =_SUNXI_CCU_MULT_MIN (8 ,8 ,11 ), + .m =_SUNXI_CCU_DIV (20 ,3 ),/* output divider */ + .p =_SUNXI_CCU_DIV (1 ,1 ),/* input divider */ + .common = {
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 358
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +10
-0+ .reg = SUN60I_A733_PLL_NPU_REG, + .hw.init =CLK_HW_INIT_PARENTS_HW ("pll-npu" , pll_ref_hws, + &ccu_nkmp_ops, + CLK_SET_RATE_GATE), + }, +}; + +#define SUN60I_A733_PLL_DE_REG 0x2e0 +static struct ccu_nm pll_de_12x_clk = { + .enable =BIT (26 ) |BIT (27 ),
Same as before. These are gates for the individual outputs. Please move them there.
Quoted 8 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +8
-0+ .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = SUN60I_A733_PLL_DE_REG, + .hw.init =CLK_HW_INIT_PARENTS_HW ("pll-de-12x" , pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE),
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 376
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +10
-0+ }, +}; + +static const struct clk_hw *pll_de_hws[] = { + &pll_de_12x_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_de_4x_clk, "pll-de-4x", pll_de_hws, + SUN60I_A733_PLL_DE_REG, 20, 3, 0); +static SUNXI_CCU_M_HWS(pll_de_3x_clk, "pll-de-3x", pll_de_hws, + SUN60I_A733_PLL_DE_REG, 16, 3, 0);
Should we make the values fixed or the divider read-only?
Quoted 127 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +127
-0+ +/* +* Contains all clocks that are controlled by a hardware register. They +* have a (sunxi) .common member, which needs to be initialised by the common +* sunxi CCU code, to be filled with the MMIO base address and the shared lock. +*/ +static struct ccu_common *sun60i_a733_ccu_clks[] = { + &pll_ref_clk.common, + &pll_ddr_clk.common, + &pll_periph0_4x_clk.common, + &pll_periph0_2x_clk.common, + &pll_periph0_800M_clk.common, + &pll_periph0_480M_clk.common, + &pll_periph1_4x_clk.common, + &pll_periph1_2x_clk.common, + &pll_periph1_800M_clk.common, + &pll_periph1_480M_clk.common, + &pll_gpu0_clk.common, + &pll_video0_12x_clk.common, + &pll_video0_4x_clk.common, + &pll_video0_3x_clk.common, + &pll_video1_12x_clk.common, + &pll_video1_4x_clk.common, + &pll_video1_3x_clk.common, + &pll_video2_12x_clk.common, + &pll_video2_4x_clk.common, + &pll_video2_3x_clk.common, + &pll_ve0_clk.common, + &pll_ve1_clk.common, + &pll_audio0_4x_clk.common, + &pll_audio1_clk.common, + &pll_audio1_div2_clk.common, + &pll_audio1_div5_clk.common, + &pll_npu_clk.common, + &pll_de_12x_clk.common, + &pll_de_4x_clk.common, + &pll_de_3x_clk.common, +}; + +static struct clk_hw_onecell_data sun60i_a733_hw_clks = { + .hws = { + [CLK_PLL_REF ] = &pll_ref_clk.common.hw, + [CLK_PLL_DDR ] = &pll_ddr_clk.common.hw, + [CLK_PLL_PERIPH0_4X ] = &pll_periph0_4x_clk.common.hw, + [CLK_PLL_PERIPH0_2X ] = &pll_periph0_2x_clk.common.hw, + [CLK_PLL_PERIPH0_800M ] = &pll_periph0_800M_clk.common.hw, + [CLK_PLL_PERIPH0_480M ] = &pll_periph0_480M_clk.common.hw, + [CLK_PLL_PERIPH0_600M ] = &pll_periph0_600M_clk.hw, + [CLK_PLL_PERIPH0_400M ] = &pll_periph0_400M_clk.hw, + [CLK_PLL_PERIPH0_300M ] = &pll_periph0_300M_clk.hw, + [CLK_PLL_PERIPH0_200M ] = &pll_periph0_200M_clk.hw, + [CLK_PLL_PERIPH0_160M ] = &pll_periph0_160M_clk.hw, + [CLK_PLL_PERIPH0_150M ] = &pll_periph0_150M_clk.hw, + [CLK_PLL_PERIPH1_4X ] = &pll_periph1_4x_clk.common.hw, + [CLK_PLL_PERIPH1_2X ] = &pll_periph1_2x_clk.common.hw, + [CLK_PLL_PERIPH1_800M ] = &pll_periph1_800M_clk.common.hw, + [CLK_PLL_PERIPH1_480M ] = &pll_periph1_480M_clk.common.hw, + [CLK_PLL_PERIPH1_600M ] = &pll_periph1_600M_clk.hw, + [CLK_PLL_PERIPH1_400M ] = &pll_periph1_400M_clk.hw, + [CLK_PLL_PERIPH1_300M ] = &pll_periph1_300M_clk.hw, + [CLK_PLL_PERIPH1_200M ] = &pll_periph1_200M_clk.hw, + [CLK_PLL_PERIPH1_160M ] = &pll_periph1_160M_clk.hw, + [CLK_PLL_PERIPH1_150M ] = &pll_periph1_150M_clk.hw, + [CLK_PLL_GPU0 ] = &pll_gpu0_clk.common.hw, + [CLK_PLL_VIDEO0_12X ] = &pll_video0_12x_clk.common.hw, + [CLK_PLL_VIDEO0_4X ] = &pll_video0_4x_clk.common.hw, + [CLK_PLL_VIDEO0_3X ] = &pll_video0_3x_clk.common.hw, + [CLK_PLL_VIDEO1_12X ] = &pll_video1_12x_clk.common.hw, + [CLK_PLL_VIDEO1_4X ] = &pll_video1_4x_clk.common.hw, + [CLK_PLL_VIDEO1_3X ] = &pll_video1_3x_clk.common.hw, + [CLK_PLL_VIDEO2_12X ] = &pll_video2_12x_clk.common.hw, + [CLK_PLL_VIDEO2_4X ] = &pll_video2_4x_clk.common.hw, + [CLK_PLL_VIDEO2_3X ] = &pll_video2_3x_clk.common.hw, + [CLK_PLL_VE0 ] = &pll_ve0_clk.common.hw, + [CLK_PLL_VE1 ] = &pll_ve1_clk.common.hw, + [CLK_PLL_AUDIO0_4X ] = &pll_audio0_4x_clk.common.hw, + [CLK_PLL_AUDIO1 ] = &pll_audio1_clk.common.hw, + [CLK_PLL_AUDIO1_DIV2 ] = &pll_audio1_div2_clk.common.hw, + [CLK_PLL_AUDIO1_DIV5 ] = &pll_audio1_div5_clk.common.hw, + [CLK_PLL_NPU ] = &pll_npu_clk.common.hw, + [CLK_PLL_DE_12X ] = &pll_de_12x_clk.common.hw, + [CLK_PLL_DE_4X ] = &pll_de_4x_clk.common.hw, + [CLK_PLL_DE_3X ] = &pll_de_3x_clk.common.hw, + }, + .num =CLK_FANOUT3 +1 , +}; + +static const struct sunxi_ccu_desc sun60i_a733_ccu_desc = { + .ccu_clks = sun60i_a733_ccu_clks, + .num_ccu_clks =ARRAY_SIZE (sun60i_a733_ccu_clks), + + .hw_clks = &sun60i_a733_hw_clks, +}; + +static const u32 pll_regs[] = { +SUN60I_A733_PLL_REF_REG , +SUN60I_A733_PLL_DDR_REG , +SUN60I_A733_PLL_PERIPH0_REG , +SUN60I_A733_PLL_PERIPH1_REG , +SUN60I_A733_PLL_GPU_REG , +SUN60I_A733_PLL_VIDEO0_REG , +SUN60I_A733_PLL_VIDEO1_REG , +SUN60I_A733_PLL_VIDEO2_REG , +SUN60I_A733_PLL_VE0_REG , +SUN60I_A733_PLL_VE1_REG , +SUN60I_A733_PLL_AUDIO0_REG , +SUN60I_A733_PLL_AUDIO1_REG , +SUN60I_A733_PLL_NPU_REG , +SUN60I_A733_PLL_DE_REG , +}; + +static int sun60i_a733_ccu_probe (struct platform_device *pdev) +{ +void __iomem *reg; +u32 val; +int i, ret; + + reg =devm_platform_ioremap_resource (pdev,0 ); +if (IS_ERR (reg)) +return PTR_ERR (reg); + +/* +* The PLL clock code does not model all bits, for instance it does +* not support a separate enable and gate bit. We present the +* gate bit(27) as the enable bit, but then have to set the +* PLL Enable, LDO Enable, and Lock Enable bits on all PLLs here. +*/
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 513
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +10
-0+for (i =0 ; i <ARRAY_SIZE (pll_regs); i++) { + val =readl (reg + pll_regs[i]); + val |=BIT (31 ) |BIT (30 ) |BIT (29 ); +writel (val, reg + pll_regs[i]); + } + +/* Enforce m1 = 0 for PLL_AUDIO0 */ + val =readl (reg +SUN60I_A733_PLL_AUDIO0_REG ); + val &= ~BIT (1 ); +writel (val, reg +SUN60I_A733_PLL_AUDIO0_REG );
We should also force the divider for all the divN or Nx outputs.
Thanks
ChenYu
Quoted 31 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +26
-1+ + ret =devm_sunxi_ccu_probe (&pdev->dev, reg, &sun60i_a733_ccu_desc); +if (ret) +return ret; + +return 0 ; +} + +static const struct of_device_id sun60i_a733_ccu_ids[] = { + { .compatible ="allwinner,sun60i-a733-ccu" }, + {/* sentinel */ } +}; + +static struct platform_driver sun60i_a733_ccu_driver = { + .probe = sun60i_a733_ccu_probe, + .driver = { + .name ="sun60i-a733-ccu" , + .suppress_bind_attrs = true, + .of_match_table = sun60i_a733_ccu_ids, + }, +}; +module_platform_driver (sun60i_a733_ccu_driver); + +MODULE_IMPORT_NS ("SUNXI_CCU" ); +MODULE_DESCRIPTION ("Support for the Allwinner A733 CCU" ); +MODULE_LICENSE ("GPL" ); --2.54.0
Re: [PATCH v2 4/8] clk: sunxi-ng: a733: Add PLL clocks support
Hi Chen-Yu,
Thanks for your review. I will address the comments in v3.
Quoted 22 lines · Chen-Yu Tsai
(trimmed recipient list a bit)
Quoted 19 lines · Junhui Liu
Add PLL clock support for the main CCU of the Allwinner A733 SoC. The structure is mostly similar to the sun55i, with the addition of a
PLL_REFclock that normalizes the hardware-detected DCXO/hosc frequency (19.2MHz, 24MHz, or 26MHz) into a consistent 24MHz reference for all subsequent PLLs.The behaviors of
PLL_AUDIO0andPLL_AUDIO1are ported from the vendor driver. Specifically,PLL_AUDIO0is configured with SDM parameters to provide a 22.5792MHz * 4 output, whilePLL_AUDIO1is integrated into the main CCU without using SDM.Tested-by Jerome Brunet <[email protected]>Signed-off-by Junhui Liu <[email protected]>--- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/sunxi-ng/Makefile | 2 + drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 539 +++++++++++++++++++++++++++++++++ 3 files changed, 546 insertions(+)
[...]
Quoted 6 lines
Quoted 6 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +6
-0+ +/* +* There is no actual clock output with that frequency (2.4 GHz), instead it +* has multiple outputs with adjustable dividers from that base frequency. +* Model them separately as divider clocks based on that parent here. +*/
Quoted 8 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 95
Quoted 3 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +3
-0+#define SUN60I_A733_PLL_PERIPH0_REG 0x0a0 +static struct ccu_nm pll_periph0_4x_clk = { + .enable =BIT (25 ) |BIT (26 ) |BIT (27 ),The gate helper sort of expects this to be just one bit. And the three bits here are for the three individual outputs (2x, 800M, 480M). I think you should move the bits to the individual outputs, and use BIT(31) here instead (or just leave out the enable bit for this one).
I will leave out the enable bit for the PLL core and move the three output gate bits to their corresponding child clocks.
[...]
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 339
Quoted 8 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +8
-0+ +static const struct clk_hw *pll_audio1_hws[] = { + &pll_audio1_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_audio1_div2_clk, "pll-audio1-div2", pll_audio1_hws, + SUN60I_A733_PLL_AUDIO1_REG, 20, 3, 0); +static SUNXI_CCU_M_HWS(pll_audio1_div5_clk, "pll-audio1-div5", pll_audio1_hws, + SUN60I_A733_PLL_AUDIO1_REG, 16, 3, 0);Perhaps these should be made fixed? Otherwise the names don't apply correctly.
Agreed. Since the names explicitly describe fixed /2 and /5 divisions, I will model these two outputs as fixed-factor clocks and initialize the corresponding divider fields accordingly.
[...]
Quoted 12 lines
Quoted 12 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +12
-0+ .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 11), + .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ + .common = { + .reg = SUN60I_A733_PLL_DE_REG, + .hw.init =CLK_HW_INIT_PARENTS_HW ("pll-de-12x" , pll_ref_hws, + &ccu_nm_ops, + CLK_SET_RATE_GATE), + }, +}; + +static const struct clk_hw *pll_de_hws[] = {
Quoted 8 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 376
Quoted 6 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +6
-0+ &pll_de_12x_clk.common.hw +}; +static SUNXI_CCU_M_HWS(pll_de_4x_clk, "pll-de-4x", pll_de_hws, + SUN60I_A733_PLL_DE_REG, 20, 3, 0); +static SUNXI_CCU_M_HWS(pll_de_3x_clk, "pll-de-3x", pll_de_hws, + SUN60I_A733_PLL_DE_REG, 16, 3, 0);Should we make the values fixed or the divider read-only?
After checking the manual again, I don't think these dividers should be fixed or read-only.
The 4X and 3X suffixes appear to be hardware output names rather than fixed multiplication factors. The manual describes both P0 and P1 as programmable dividers and only gives their default frequencies; it does not say that their values must remain fixed.
For example, the default frequencies of DEPLL4X and DEPLL3X are 1044 MHz and 696 MHz, respectively. If the suffixes represented multiples of a common base frequency, 1044 MHz / 4 * 3 would be 783 MHz, not 696 MHz.
[...]
Quoted 11 lines
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drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +11
-0+ +/* +* The PLL clock code does not model all bits, for instance it does +* not support a separate enable and gate bit. We present the +* gate bit(27) as the enable bit, but then have to set the +* PLL Enable, LDO Enable, and Lock Enable bits on all PLLs here. +*/ +for (i =0 ; i <ARRAY_SIZE (pll_regs); i++) { + val =readl (reg + pll_regs[i]); + val |=BIT (31 ) |BIT (30 ) |BIT (29 ); +writel (val, reg + pll_regs[i]);
Quoted 8 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c line 513
Quoted 6 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c new file +6
-0+ } + +/* Enforce m1 = 0 for PLL_AUDIO0 */ + val =readl (reg +SUN60I_A733_PLL_AUDIO0_REG ); + val &= ~BIT (1 ); +writel (val, reg +SUN60I_A733_PLL_AUDIO0_REG );We should also force the divider for all the divN or Nx outputs.
For the reasons above, I plan to force the divider values only for the divN outputs, whose names explicitly specify their division ratios, and leave the Nx output dividers programmable.
Quoted 5 lines
Thanks
ChenYu
Signature · 2 lines
Best regards, Junhui Liu
PATCH v2 5/8 clk: sunxi-ng: a733: Add bus clocks support
In reply to Junhui LiuAdd the essential bus clocks in the Allwinner A733 CCU, including AHB, APB0, APB1, APB_UART, and MBUS. These buses are necessary for many other functional modules. An additional trace clock is also added as it fall within the register address range of the bus clocks, even though it is not strictly bus clocks.
The MBUS clock is marked as critical to ensure the memory bus remains operational at all times. And the hardware requires an update bit (bit 27) to be set so that the configuration takes effect and the updated parameters can be correctly read back for the MBUS clock.
Tested-by Jerome Brunet <[email protected]>
Signed-off-by Junhui Liu <[email protected]>
--- drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 91 ++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+)
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +91 -0
@@ -19,6 +19,7 @@#include "ccu_common.h" #include "ccu_div.h" +#include "ccu_mp.h" #include "ccu_mult.h" #include "ccu_nkmp.h" #include "ccu_nm.h"
@@ -69,6 +70,16 @@ static const struct clk_hw *pll_ref_hws[] = { &pll_ref_clk.common.hw }; +/* +* There is a non-software-configurable mux selecting between the DCXO and the +* PLL_REF in hardware, whose output is fed to the sys-24M clock. Although both +* sys-24M and pll-ref are fixed at 24 MHz, define a 1:1 fixed factor clock to +* provide logical separation: +* - pll-ref is dedicated to feeding other PLLs +* - sys-24M serves as reference clock for downstream functional modules +*/ +static CLK_FIXED_FACTOR_HWS(sys_24M_clk, "sys-24M", pll_ref_hws, 1, 1, 0); +#define SUN60I_A733_PLL_DDR_REG 0x020static struct ccu_nkmp pll_ddr_clk = { .enable =BIT (27 ),
@@ -375,6 +386,73 @@ static SUNXI_CCU_M_HWS(pll_de_4x_clk, "pll-de-4x", pll_de_hws, static SUNXI_CCU_M_HWS(pll_de_3x_clk, "pll-de-3x", pll_de_hws, SUN60I_A733_PLL_DE_REG, 16, 3, 0); +/************************************************************************** +* bus clocks * +**************************************************************************/ + +static const struct clk_parent_data ahb_apb_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name ="losc" }, + { .fw_name ="iosc" }, + { .hw = &pll_periph0_600M_clk.hw }, +}; + +static SUNXI_CCU_M_DATA_WITH_MUX(ahb_clk, "ahb", ahb_apb_parents, 0x500, +0 ,5 ,/* M */ +24 ,2 ,/* mux */ + 0); + +static SUNXI_CCU_M_DATA_WITH_MUX(apb0_clk, "apb0", ahb_apb_parents, 0x510, +0 ,5 ,/* M */ +24 ,2 ,/* mux */ + 0); + +static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", ahb_apb_parents, 0x518, +0 ,5 ,/* M */ +24 ,2 ,/* mux */ + 0); + +static const struct clk_parent_data apb_uart_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name ="losc" }, + { .fw_name ="iosc" }, + { .hw = &pll_periph0_600M_clk.hw }, + { .hw = &pll_periph0_480M_clk.common.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX(apb_uart_clk, "apb-uart", apb_uart_parents, 0x538, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ + 0); + +static const struct clk_parent_data trace_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name ="losc" }, + { .fw_name ="iosc" }, + { .hw = &pll_periph0_300M_clk.hw }, + { .hw = &pll_periph0_400M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(trace_clk, "trace", trace_parents, 0x540, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data mbus_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph1_600M_clk.hw }, + { .hw = &pll_ddr_clk.common.hw }, + { .hw = &pll_periph1_480M_clk.common.hw }, + { .hw = &pll_periph1_400M_clk.hw }, + { .hw = &pll_npu_clk.common.hw }, +}; +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x588, +0 ,5 ,/* M */ +0 ,0 ,/* no P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ +CLK_IS_CRITICAL , + CCU_FEATURE_UPDATE_BIT); +/* * Contains all clocks that are controlled by a hardware register. They * have a (sunxi) .common member, which needs to be initialised by the common
@@ -411,11 +489,18 @@ static struct ccu_common *sun60i_a733_ccu_clks[] = { &pll_de_12x_clk.common, &pll_de_4x_clk.common, &pll_de_3x_clk.common, + &ahb_clk.common, + &apb0_clk.common, + &apb1_clk.common, + &apb_uart_clk.common, + &trace_clk.common, + &mbus_clk.common, };static struct clk_hw_onecell_data sun60i_a733_hw_clks = { .hws = { [CLK_PLL_REF ] = &pll_ref_clk.common.hw, + [CLK_SYS_24M ] = &sys_24M_clk.hw, [CLK_PLL_DDR ] = &pll_ddr_clk.common.hw, [CLK_PLL_PERIPH0_4X ] = &pll_periph0_4x_clk.common.hw, [CLK_PLL_PERIPH0_2X ] = &pll_periph0_2x_clk.common.hw,
@@ -457,6 +542,12 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = { [CLK_PLL_DE_12X] = &pll_de_12x_clk.common.hw, [CLK_PLL_DE_4X] = &pll_de_4x_clk.common.hw, [CLK_PLL_DE_3X] = &pll_de_3x_clk.common.hw, + [CLK_AHB] = &ahb_clk.common.hw, + [CLK_APB0] = &apb0_clk.common.hw, + [CLK_APB1] = &apb1_clk.common.hw, + [CLK_APB_UART] = &apb_uart_clk.common.hw, + [CLK_TRACE] = &trace_clk.common.hw, + [CLK_MBUS] = &mbus_clk.common.hw, }, .num = CLK_FANOUT3 + 1, };
Signature · 1 line
2.54.0
[email protected]
AI reviewRe: [PATCH v2 5/8] clk: sunxi-ng: a733: Add bus clocks support
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
Pre-existing issues:
- [Critical] Defining mbus_clk with a 0-width P prescaler causes undefined behavior in ccu_mp_set_rate(), leading to the critical memory bus clock register being completely cleared.
- [High] The MBUS clock requires an update bit to commit rate changes, but it is defined using ccu_mp operations which completely ignore the CCU_FEATURE_UPDATE_BIT flag. --
--- Patch [5]: [PATCH v2 5/8] clk: sunxi-ng: a733: Add bus clocks support --- commit 40f96b18647c7ab7dc42f9a7456046beab510ac6
Author: Junhui Liu <[email protected]>
clk: sunxi-ng: a733: Add bus clocks support
This commit adds the essential bus clocks in the Allwinner A733 CCU, including AHB, APB0, APB1, APB_UART, and MBUS. It also marks the MBUS clock as critical to ensure the memory bus remains operational.
Quoted 3 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +0
-0
[ ... ]
drivers/clk/sunxi-ng/ccu-sun60i-a733.c static SUNXI_CCU_M_HWS(pll_de_4x_clk, "pll-de-4x", pll_de_hws, · line 450
Quoted 11 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +11
-0+static const struct clk_parent_data mbus_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph1_600M_clk.hw }, + { .hw = &pll_ddr_clk.common.hw }, + { .hw = &pll_periph1_480M_clk.common.hw }, + { .hw = &pll_periph1_400M_clk.hw }, + { .hw = &pll_npu_clk.common.hw }, +}; +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x588, +0 ,5 ,/* M */ + 0, 0, /* no P */
[Severity: Critical]
This is a pre-existing issue in the framework, but does defining mbus_clk with a 0-width P prescaler cause undefined behavior when the rate is set?
When ccu_mp_set_rate() is called in drivers/clk/sunxi-ng/ccu_mp.c, it evaluates the mask for the P prescaler:
drivers/clk/sunxi-ng/ccu_mp.c:ccu_mp_set_rate() {
...
reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
...
}Since p.width is 0, this expands to GENMASK(-1, 0). On 64-bit architectures, the shift by 64 is masked to 0, which makes ~GENMASK evaluate to 0 and clears the entire mbus_clk register, including the critical clock gate bit.
Could this lead to a system crash during boot or runtime frequency scaling?
drivers/clk/sunxi-ng/ccu-sun60i-a733.c static SUNXI_CCU_M_HWS(pll_de_4x_clk, "pll-de-4x", pll_de_hws, · line 454
Quoted 4 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +4
-0+24 ,3 ,/* mux */ +BIT (31 ),/* gate */ +CLK_IS_CRITICAL , + CCU_FEATURE_UPDATE_BIT);
[Severity: High]
This is also a pre-existing issue in the framework, but will the hardware actually commit rate changes for this clock?
The commit message notes that the hardware requires bit 27 to be set for the configuration to take effect. However, ccu_mp_set_rate() does not process the CCU_FEATURE_UPDATE_BIT flag before writing the register:
drivers/clk/sunxi-ng/ccu_mp.c:ccu_mp_set_rate() {
...
writel(reg, cmp->common.base + cmp->common.reg);
spin_unlock_irqrestore(cmp->common.lock, flags);
...
}Since the update bit is never toggled by the ccu_mp operations, does this leave the software state permanently out of sync with the hardware state when the mbus_clk rate is configured?
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=5
PATCH v2 6/8 clk: sunxi-ng: a733: Add mod clocks support
In reply to Junhui LiuAdd the module clocks found in the Allwinner A733 SoC, including video, storage, interfaces and others. While most of these clocks are similar to those in the A523 SoC, this implementation accounts for changes in register offsets and introduces support for new modules.
Tested-by Jerome Brunet <[email protected]>
Signed-off-by Junhui Liu <[email protected]>
--- drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 1118 ++++++++++++++++++++++++++++++++ 1 file changed, 1118 insertions(+)
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +1118 -0
@@ -19,8 +19,10 @@#include "ccu_common.h" #include "ccu_div.h" +#include "ccu_gate.h" #include "ccu_mp.h" #include "ccu_mult.h" +#include "ccu_mux.h" #include "ccu_nkmp.h" #include "ccu_nm.h"
@@ -79,6 +81,9 @@ static const struct clk_hw *pll_ref_hws[] = {* - sys-24M serves as reference clock for downstream functional modules */ static CLK_FIXED_FACTOR_HWS(sys_24M_clk, "sys-24M", pll_ref_hws, 1, 1, 0); +static const struct clk_hw *sys_24M_hws[] = { + &sys_24M_clk.hw +};#define SUN60I_A733_PLL_DDR_REG 0x020static struct ccu_nkmp pll_ddr_clk = {
@@ -137,10 +142,16 @@ static CLK_FIXED_FACTOR_HWS(pll_periph0_400M_clk, "pll-periph0-400M", pll_periph0_2x_hws, 3, 1, 0); static CLK_FIXED_FACTOR_HWS(pll_periph0_300M_clk, "pll-periph0-300M", pll_periph0_2x_hws, 4, 1, 0); +static const struct clk_hw *pll_periph0_300M_hws[] = { + &pll_periph0_300M_clk.hw +}; static CLK_FIXED_FACTOR_HWS(pll_periph0_200M_clk, "pll-periph0-200M", pll_periph0_2x_hws, 6, 1, 0); static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, "pll-periph0-150M", pll_periph0_2x_hws, 8, 1, 0); +static const struct clk_hw *pll_periph0_150M_hws[] = { + &pll_periph0_150M_clk.hw +}; static CLK_FIXED_FACTOR_HWS(pll_periph0_160M_clk, "pll-periph0-160M", pll_periph0_480M_hws, 3, 1, 0);
@@ -453,6 +464,923 @@ static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x58CLK_IS_CRITICAL , CCU_FEATURE_UPDATE_BIT); +/************************************************************************** +* mod clocks * +**************************************************************************/ + +static const struct clk_parent_data timer_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name ="iosc" }, + { .fw_name ="losc" }, + { .hw = &pll_periph0_200M_clk.hw }, + { .fw_name ="hosc" }, +}; +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer0_clk, "timer0", timer_parents, 0x800, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer1_clk, "timer1", timer_parents, 0x804, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer2_clk, "timer2", timer_parents, 0x808, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer3_clk, "timer3", timer_parents, 0x80c, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer4_clk, "timer4", timer_parents, 0x810, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer5_clk, "timer5", timer_parents, 0x814, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer6_clk, "timer6", timer_parents, 0x818, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer7_clk, "timer7", timer_parents, 0x81c, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer8_clk, "timer8", timer_parents, 0x820, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer9_clk, "timer9", timer_parents, 0x824, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +/* Undocumented, taken from the vendor kernel. */ +static const struct clk_parent_data avs_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name ="hosc" }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(avs_clk, "avs-clk", avs_parents, 0x880, +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_hw *de_parents[] = { + &pll_de_3x_clk.common.hw, + &pll_de_4x_clk.common.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_300M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(de0_clk, "de0", de_parents, 0xa00, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *di_parents[] = { + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", di_parents, 0xa20, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *g2d_parents[] = { + &pll_periph0_400M_clk.hw, + &pll_periph0_300M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", g2d_parents, 0xa40, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *eink_parents[] = { + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(eink_clk, "eink", eink_parents, 0xa60, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *eink_panel_parents[] = { + &pll_video0_4x_clk.common.hw, + &pll_video0_3x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video1_3x_clk.common.hw, + &pll_periph0_300M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(eink_panel_clk, "eink-panel", eink_panel_parents, 0xa64, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *ve_enc_parents[] = { + &pll_ve0_clk.common.hw, + &pll_ve1_clk.common.hw, + &pll_periph0_800M_clk.common.hw, + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_de_3x_clk.common.hw, + &pll_npu_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_enc0_clk, "ve-enc0", ve_enc_parents, 0xa80, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *ve_dec_parents[] = { + &pll_ve1_clk.common.hw, + &pll_ve0_clk.common.hw, + &pll_periph0_800M_clk.common.hw, + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_de_3x_clk.common.hw, + &pll_npu_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_dec0_clk, "ve-dec0", ve_dec_parents, 0xa88, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + CLK_SET_RATE_PARENT); + +static const struct clk_hw *ce_parents[] = { + &sys_24M_clk.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_600M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0xac0, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_hw *npu_parents[] = { + &pll_npu_clk.common.hw, + &pll_periph0_800M_clk.common.hw, + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_ve0_clk.common.hw, + &pll_ve1_clk.common.hw, + &pll_de_3x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0xb00, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +/* +* GPU_CLK = ClockSource * ((16 - M) / 16) +* Here we use a div_table to select M values that result in integer divisors. +*/ +static struct clk_div_table gpu_div_table[] = { + { .val =0 , .div =1 }, + { .val =8 , .div =2 }, + { .val =12 , .div =4 }, + { .val =14 , .div =8 }, + { .val =15 , .div =16 }, + {/* sentinel */ }, +}; +static const struct clk_parent_data gpu_parents[] = { + { .hw = &pll_gpu0_clk.common.hw, }, + { .hw = &pll_periph0_800M_clk.common.hw, }, + { .hw = &pll_periph0_600M_clk.hw, }, + { .hw = &pll_periph0_400M_clk.hw, }, + { .hw = &pll_periph0_300M_clk.hw, }, + { .hw = &pll_periph0_200M_clk.hw, }, +}; +static struct ccu_div gpu0_clk = { + .enable =BIT (31 ), + .div =_SUNXI_CCU_DIV_TABLE (0 ,4 , gpu_div_table), + .mux =_SUNXI_CCU_MUX (24 ,3 ), + .common = { + .reg =0xb20 , + .features =CCU_FEATURE_UPDATE_BIT , + .hw.init =CLK_HW_INIT_PARENTS_DATA ("gpu0" , gpu_parents, + &ccu_div_ops,0 ), + } +}; + +static const struct clk_parent_data dram_parents[] = { + { .hw = &pll_ddr_clk.common.hw, }, + { .hw = &pll_periph0_800M_clk.common.hw, }, + { .hw = &pll_periph0_600M_clk.hw, }, + { .hw = &pll_de_12x_clk.common.hw, }, + { .hw = &pll_npu_clk.common.hw, }, +}; +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(dram0_clk, "dram0", dram_parents, 0xc00, +0 ,4 ,/* M */ +0 ,0 ,/* no P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ +CLK_IS_CRITICAL , + CCU_FEATURE_UPDATE_BIT); + +static const struct clk_parent_data nand_mmc_parents[] = { + { .hw = &sys_24M_clk.hw, }, + { .hw = &pll_periph0_400M_clk.hw, }, + { .hw = &pll_periph0_300M_clk.hw, }, + { .hw = &pll_periph1_400M_clk.hw, }, + { .hw = &pll_periph1_300M_clk.hw, }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand0_clk0_clk, "nand0-clk0", nand_mmc_parents, 0xc80, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand0_clk1_clk, "nand0-clk1", nand_mmc_parents, 0xc84, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc0_clk, "mmc0", nand_mmc_parents, 0xd00, +0 ,5 ,/* M */ +8 ,5 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ +2 ,/* post div */ + 0); +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc1_clk, "mmc1", nand_mmc_parents, 0xd10, +0 ,5 ,/* M */ +8 ,5 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ +2 ,/* post div */ + 0); + +static const struct clk_parent_data mmc2_mmc3_parents[] = { + { .hw = &sys_24M_clk.hw, }, + { .hw = &pll_periph0_800M_clk.common.hw }, + { .hw = &pll_periph0_600M_clk.hw }, + { .hw = &pll_periph1_800M_clk.common.hw }, + { .hw = &pll_periph1_600M_clk.hw }, +}; +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc2_clk, "mmc2", mmc2_mmc3_parents, 0xd20, +0 ,5 ,/* M */ +8 ,5 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ +2 ,/* post div */ + 0); +static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc3_clk, "mmc3", mmc2_mmc3_parents, 0xd30, +0 ,5 ,/* M */ +8 ,5 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ +2 ,/* post div */ + 0); + +static const struct clk_hw *ufs_axi_parents[] = { + &pll_periph0_300M_clk.hw, + &pll_periph0_200M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(ufs_axi_clk, "ufs-axi", ufs_axi_parents, 0xd80, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data ufs_cfg_parents[] = { + { .hw = &pll_periph0_480M_clk.common.hw }, + { .fw_name ="hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ufs_cfg_clk, "ufs-cfg", ufs_cfg_parents, 0xd84, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data spi_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph0_300M_clk.hw }, + { .hw = &pll_periph0_200M_clk.hw }, + { .hw = &pll_periph1_300M_clk.hw }, + { .hw = &pll_periph1_200M_clk.hw }, + { .hw = &pll_periph0_480M_clk.common.hw }, + { .hw = &pll_periph1_480M_clk.common.hw }, + { .fw_name ="hosc" }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(spi0_clk, "spi0", spi_parents, 0xf00, +0 ,5 ,/* M */ +8 ,5 ,/* N */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(spi1_clk, "spi1", spi_parents, 0xf08, +0 ,5 ,/* M */ +8 ,5 ,/* N */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(spi2_clk, "spi2", spi_parents, 0xf10, +0 ,5 ,/* M */ +8 ,5 ,/* N */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data spif_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph0_400M_clk.hw }, + { .hw = &pll_periph0_300M_clk.hw }, + { .hw = &pll_periph1_400M_clk.hw }, + { .hw = &pll_periph1_300M_clk.hw }, + { .hw = &pll_periph0_160M_clk.hw }, + { .hw = &pll_periph1_160M_clk.hw }, + { .fw_name ="hosc" }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(spif_clk, "spif", spif_parents, 0xf18, +0 ,5 ,/* M */ +8 ,5 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(spi3_clk, "spi3", spi_parents, 0xf20, +0 ,5 ,/* M */ +8 ,5 ,/* N */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +/* Undocumented, taken from the vendor kernel. */ +static SUNXI_CCU_DUALDIV_MUX_GATE(spi4_clk, "spi4", spi_parents, 0xf28, +0 ,5 ,/* M */ +8 ,5 ,/* N */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data gpadc0_24m_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name ="hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gpadc0_24m_clk, "gpadc0-24m", gpadc0_24m_parents, 0xfc0, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data irrx_parents[] = { + { .fw_name ="losc" }, + { .hw = &sys_24M_clk.hw }, + { .fw_name ="hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irrx_clk, "irrx", irrx_parents, 0x1000, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data irtx_parents[] = { + { .fw_name ="losc" }, + { .hw = &pll_periph1_600M_clk.hw }, + { .fw_name ="hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irtx_clk, "irtx", irtx_parents, 0x1008, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +/* Undocumented, taken from the vendor kernel. */ +static const struct clk_parent_data sgpio_parents[] = { + { .fw_name ="losc" }, + { .hw = &sys_24M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(sgpio_clk, "sgpio", sgpio_parents, 0x1060, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +/* Undocumented, taken from the vendor kernel. */ +static const struct clk_hw *lpc_parents[] = { + &pll_video0_3x_clk.common.hw, + &pll_video1_3x_clk.common.hw, + &pll_video2_3x_clk.common.hw, + &pll_periph0_300M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(lpc_clk, "lpc", lpc_parents, 0x1080, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_hw *i2spcm_parents[] = { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.common.hw, + &pll_audio1_div5_clk.common.hw, + &pll_periph0_200M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm0_clk, "i2spcm0", i2spcm_parents, 0x1200, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm1_clk, "i2spcm1", i2spcm_parents, 0x1210, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_clk, "i2spcm2", i2spcm_parents, 0x1220, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_hw *i2spcm2_asrc_parents[] = { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.common.hw, + &pll_audio1_div5_clk.common.hw, + &pll_periph0_300M_clk.hw, + &pll_periph1_300M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_asrc_clk, "i2spcm2_asrc", i2spcm2_asrc_parents, 0x1224, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm3_clk, "i2spcm3", i2spcm_parents, 0x1230, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm4_clk, "i2spcm4", i2spcm_parents, 0x1240, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_hw *spdif_tx_parents[] = { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.common.hw, + &pll_audio1_div5_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(spdif_tx_clk, "spdif-tx", spdif_tx_parents, 0x1280, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_hw *spdif_rx_parents[] = { + &pll_periph0_200M_clk.hw, + &pll_periph0_300M_clk.hw, + &pll_periph0_400M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(spdif_rx_clk, "spdif-rx", spdif_rx_parents, 0x1284, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_hw *dmic_parents[] = { + &pll_audio0_4x_clk.common.hw, + &pll_audio1_div2_clk.common.hw, + &pll_audio1_div5_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dmic_clk, "dmic", dmic_parents, 0x12c0, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +/* +* The first parent is a 48 MHz input clock divided by 4. That 48 MHz clock is +* a 2x multiplier from pll-ref synchronized by pll-periph0, and is also used by +* the OHCI module. +*/ +static const struct clk_parent_data usb_ohci_parents[] = { + { .hw = &pll_periph0_4x_clk.common.hw }, + { .hw = &sys_24M_clk.hw }, + { .fw_name ="losc" }, + { .fw_name ="iosc" }, +}; +static const struct ccu_mux_fixed_prediv usb_ohci_predivs[] = { + { .index =0 , .div =200 }, + { .index =1 , .div =2 }, +}; + +static struct ccu_mux usb_ohci0_clk = { + .enable =BIT (31 ), + .mux = { + .shift =24 , + .width =2 , + .fixed_predivs = usb_ohci_predivs, + .n_predivs =ARRAY_SIZE (usb_ohci_predivs), + }, + .common = { + .reg =0x1300 , + .features =CCU_FEATURE_FIXED_PREDIV , + .hw.init =CLK_HW_INIT_PARENTS_DATA ("usb-ohci0" , usb_ohci_parents, + &ccu_mux_ops,0 ), + }, +}; + +static struct ccu_mux usb_ohci1_clk = { + .enable =BIT (31 ), + .mux = { + .shift =24 , + .width =2 , + .fixed_predivs = usb_ohci_predivs, + .n_predivs =ARRAY_SIZE (usb_ohci_predivs), + }, + .common = { + .reg =0x1308 , + .features =CCU_FEATURE_FIXED_PREDIV , + .hw.init =CLK_HW_INIT_PARENTS_DATA ("usb-ohci1" , usb_ohci_parents, + &ccu_mux_ops,0 ), + }, +}; + +static const struct clk_parent_data usb01_ref_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name ="hosc" }, +}; +static SUNXI_CCU_MUX_DATA(usb01_ref_clk, "usb01-ref", usb01_ref_parents, 0x1340, 24, 3, 0); + +static SUNXI_CCU_MUX_DATA(usb2_u2_ref_clk, "usb2-u2-ref", usb01_ref_parents, 0x1348, 24, 3, 0); + +static const struct clk_parent_data usb2_suspend_parents[] = { + { .fw_name ="losc" }, + { .hw = &sys_24M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_suspend_clk, "usb2-suspend", usb2_suspend_parents, +0x1350 , +0 ,5 ,/* M */ +24 ,1 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data usb2_mf_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph0_300M_clk.hw }, + { .fw_name ="hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_mf_clk, "usb2-mf", usb2_mf_parents, +0x1354 , +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data usb2_u3_utmi_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph0_300M_clk.hw }, + { .fw_name ="hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_u3_utmi_clk, "usb2-u3-utmi", usb2_u3_utmi_parents, +0x1360 , +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data usb2_u2_pipe_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph0_480M_clk.common.hw }, + { .fw_name ="hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(usb2_u2_pipe_clk, "usb2-u2-pipe", usb2_u2_pipe_parents, +0x1364 , +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data pcie_aux_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name ="losc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(pcie_aux_clk, "pcie-aux", pcie_aux_parents, 0x1380, +0 ,5 ,/* M */ +24 ,1 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_hw *pcie_axi_slv_parents[] = { + &pll_periph0_600M_clk.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(pcie_axi_slv_clk, "pcie-axi-slv", pcie_axi_slv_parents, 0x1384, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_hw *serdes_phy_parents[] = { + &sys_24M_clk.hw, + &pll_periph0_600M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(serdes_phy_clk, "serdes-phy", serdes_phy_parents, 0x13c0, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data gmac_ptp_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph0_200M_clk.hw }, + { .fw_name ="hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gmac_ptp_clk, "gmac-ptp", gmac_ptp_parents, 0x1400, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static SUNXI_CCU_M_HWS_WITH_GATE(gmac0_phy_clk, "gmac0-phy", pll_periph0_150M_hws, 0x1410, +0 ,5 ,/* M */ +BIT (31 ),/* gate */ + 0); +/* Undocumented, taken from the vendor kernel. */ +static SUNXI_CCU_M_HWS_WITH_GATE(gmac1_phy_clk, "gmac1-phy", pll_periph0_150M_hws, 0x1420, +0 ,5 ,/* M */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_hw *tcon_lcd_parents[] = { + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, + &pll_periph0_2x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_lcd_parents, 0x1500, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_lcd_parents, 0x1508, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +/* Undocumented, taken from the vendor kernel. */ +static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd2_clk, "tcon-lcd2", tcon_lcd_parents, 0x1510, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_hw *dsi_parents[] = { + &sys_24M_clk.hw, + &pll_periph0_200M_clk.hw, + &pll_periph0_150M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi0_clk, "dsi0", dsi_parents, 0x1580, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi1_clk, "dsi1", dsi_parents, 0x1588, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_hw *combphy_parents[] = { + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, + &pll_periph0_2x_clk.common.hw, + &pll_video0_3x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(combphy0_clk, "combphy0", combphy_parents, 0x15c0, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_M_HW_WITH_MUX_GATE(combphy1_clk, "combphy1", combphy_parents, 0x15c4, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_hw *edp_tv_parents[] = { + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, + &pll_video2_4x_clk.common.hw, + &pll_periph0_2x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(edp_tv_clk, "edp-tv", edp_tv_parents, 0x1640, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k", pll_periph0_2x_hws, 0x1680, +BIT (30 ),/* gate */ +36621 ,/* pre div */ + 0); + +static const struct clk_parent_data hdmi_cec_parents[] = { + { .fw_name ="losc" }, + { .hw = &hdmi_cec_32k_clk.common.hw }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents, 0x1680, +24 ,1 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data hdmi_tv_parents[] = { + { .hw = &pll_video0_4x_clk.common.hw }, + { .hw = &pll_video1_4x_clk.common.hw }, + { .hw = &pll_video2_4x_clk.common.hw }, + { .hw = &pll_periph0_2x_clk.common.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(hdmi_tv_clk, "hdmi-tv", hdmi_tv_parents, 0x1684, +0 ,5 ,/* M */ +8 ,5 ,/* N */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data hdmi_sfr_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name ="hosc" }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_sfr_clk, "hdmi-sfr", hdmi_sfr_parents, 0x1690, +24 ,1 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static SUNXI_CCU_GATE_HWS(hdcp_esm_clk, "hdcp-esm", pll_periph0_300M_hws, 0x1694, BIT(31), 0); + +static const struct clk_parent_data ledc_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_periph0_600M_clk.hw }, + { .fw_name ="hosc" }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ledc_parents, 0x1700, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data csi_master_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .hw = &pll_video0_4x_clk.common.hw }, + { .hw = &pll_video0_3x_clk.common.hw }, + { .hw = &pll_video1_4x_clk.common.hw }, + { .hw = &pll_video1_3x_clk.common.hw }, + { .hw = &pll_video2_4x_clk.common.hw }, + { .hw = &pll_video2_3x_clk.common.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master0_clk, "csi_master0", csi_master_parents, 0x1800, +0 ,5 ,/* M */ +8 ,5 ,/* N */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master1_clk, "csi_master1", csi_master_parents, 0x1804, +0 ,5 ,/* M */ +8 ,5 ,/* N */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_DUALDIV_MUX_GATE(csi_master2_clk, "csi_master2", csi_master_parents, 0x1808, +0 ,5 ,/* M */ +8 ,5 ,/* N */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_hw *csi_parents[] = { + &pll_video2_4x_clk.common.hw, + &pll_de_4x_clk.common.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_600M_clk.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_clk, "csi", csi_parents, 0x1840, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_hw *isp_parents[] = { + &pll_video2_4x_clk.common.hw, + &pll_periph0_480M_clk.common.hw, + &pll_periph0_400M_clk.hw, + &pll_periph0_600M_clk.hw, + &pll_video0_4x_clk.common.hw, + &pll_video1_4x_clk.common.hw, +}; +static SUNXI_CCU_M_HW_WITH_MUX_GATE(isp_clk, "isp", isp_parents, 0x1860, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static SUNXI_CCU_GATE_DATA(res_dcap_24m_clk, "res-dcap-24m", hosc, 0x1a00, BIT(3), 0); + +static const struct clk_parent_data apb2jtag_parents[] = { + { .hw = &sys_24M_clk.hw }, + { .fw_name ="losc" }, + { .fw_name ="iosc" }, + { .hw = &pll_periph0_480M_clk.common.hw }, + { .hw = &pll_periph1_480M_clk.common.hw }, + { .hw = &pll_periph0_200M_clk.hw }, + { .hw = &pll_periph1_200M_clk.hw }, +}; +static SUNXI_CCU_M_DATA_WITH_MUX_GATE(apb2jtag_clk, "apb2jtag", apb2jtag_parents, 0x1c00, +0 ,5 ,/* M */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static SUNXI_CCU_GATE_HWS(fanout_24M_clk, "fanout-24M", sys_24M_hws, 0x1f30, BIT(0), 0); +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_12M_clk, "fanout-12M", sys_24M_hws, 0x1f30, + BIT(1), 2, 0); +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M", pll_periph0_480M_hws, 0x1f30, + BIT(2), 30, 0); +static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M", pll_periph0_2x_hws, 0x1f30, + BIT(3), 48, 0); + +static const struct clk_parent_data fanout_27M_parents[] = { + { .hw = &pll_video0_4x_clk.common.hw }, + { .hw = &pll_video1_4x_clk.common.hw }, + { .hw = &pll_video2_4x_clk.common.hw }, +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_27M_clk, "fanout-27M", fanout_27M_parents, 0x1f34, +0 ,5 ,/* M */ +8 ,5 ,/* N */ +24 ,2 ,/* mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data fanout_pclk_parents[] = { + { .hw = &apb0_clk.common.hw } +}; +static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_pclk_clk, "fanout-pclk", fanout_pclk_parents, 0x1f38, +0 ,5 ,/* M */ +5 ,5 ,/* N */ +0 ,0 ,/* no mux */ +BIT (31 ),/* gate */ + 0); + +static const struct clk_parent_data fanout_parents[] = { + { .fw_name ="losc-fanout" }, + { .hw = &fanout_12M_clk.common.hw, }, + { .hw = &fanout_16M_clk.common.hw, }, + { .hw = &fanout_24M_clk.common.hw, }, + { .hw = &fanout_25M_clk.common.hw, }, + { .hw = &fanout_27M_clk.common.hw, }, + { .hw = &fanout_pclk_clk.common.hw, }, +}; +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout0_clk, "fanout0", fanout_parents, 0x1f3c, +0 ,3 ,/* mux */ +BIT (21 ),/* gate */ + 0); +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout1_clk, "fanout1", fanout_parents, 0x1f3c, +3 ,3 ,/* mux */ +BIT (22 ),/* gate */ + 0); +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout2_clk, "fanout2", fanout_parents, 0x1f3c, +6 ,3 ,/* mux */ +BIT (23 ),/* gate */ + 0); +static SUNXI_CCU_MUX_DATA_WITH_GATE(fanout3_clk, "fanout3", fanout_parents, 0x1f3c, +9 ,3 ,/* mux */ +BIT (24 ),/* gate */ + 0); +/* * Contains all clocks that are controlled by a hardware register. They * have a (sunxi) .common member, which needs to be initialised by the common
@@ -495,6 +1423,101 @@ static struct ccu_common *sun60i_a733_ccu_clks[] = { &apb_uart_clk.common, &trace_clk.common, &mbus_clk.common, + &timer0_clk.common, + &timer1_clk.common, + &timer2_clk.common, + &timer3_clk.common, + &timer4_clk.common, + &timer5_clk.common, + &timer6_clk.common, + &timer7_clk.common, + &timer8_clk.common, + &timer9_clk.common, + &avs_clk.common, + &de0_clk.common, + &di_clk.common, + &g2d_clk.common, + &eink_clk.common, + &eink_panel_clk.common, + &ve_enc0_clk.common, + &ve_dec0_clk.common, + &ce_clk.common, + &npu_clk.common, + &gpu0_clk.common, + &dram0_clk.common, + &nand0_clk0_clk.common, + &nand0_clk1_clk.common, + &mmc0_clk.common, + &mmc1_clk.common, + &mmc2_clk.common, + &mmc3_clk.common, + &ufs_axi_clk.common, + &ufs_cfg_clk.common, + &spi0_clk.common, + &spi1_clk.common, + &spi2_clk.common, + &spif_clk.common, + &spi3_clk.common, + &spi4_clk.common, + &gpadc0_24m_clk.common, + &irrx_clk.common, + &irtx_clk.common, + &sgpio_clk.common, + &lpc_clk.common, + &i2spcm0_clk.common, + &i2spcm1_clk.common, + &i2spcm2_clk.common, + &i2spcm2_asrc_clk.common, + &i2spcm3_clk.common, + &i2spcm4_clk.common, + &spdif_tx_clk.common, + &spdif_rx_clk.common, + &dmic_clk.common, + &usb_ohci0_clk.common, + &usb_ohci1_clk.common, + &usb01_ref_clk.common, + &usb2_u2_ref_clk.common, + &usb2_suspend_clk.common, + &usb2_mf_clk.common, + &usb2_u3_utmi_clk.common, + &usb2_u2_pipe_clk.common, + &pcie_aux_clk.common, + &pcie_axi_slv_clk.common, + &serdes_phy_clk.common, + &gmac_ptp_clk.common, + &gmac0_phy_clk.common, + &gmac1_phy_clk.common, + &tcon_lcd0_clk.common, + &tcon_lcd1_clk.common, + &tcon_lcd2_clk.common, + &dsi0_clk.common, + &dsi1_clk.common, + &combphy0_clk.common, + &combphy1_clk.common, + &edp_tv_clk.common, + &hdmi_cec_32k_clk.common, + &hdmi_cec_clk.common, + &hdmi_tv_clk.common, + &hdmi_sfr_clk.common, + &hdcp_esm_clk.common, + &ledc_clk.common, + &csi_master0_clk.common, + &csi_master1_clk.common, + &csi_master2_clk.common, + &csi_clk.common, + &isp_clk.common, + &res_dcap_24m_clk.common, + &apb2jtag_clk.common, + &fanout_24M_clk.common, + &fanout_12M_clk.common, + &fanout_16M_clk.common, + &fanout_25M_clk.common, + &fanout_27M_clk.common, + &fanout_pclk_clk.common, + &fanout0_clk.common, + &fanout1_clk.common, + &fanout2_clk.common, + &fanout3_clk.common, }; static struct clk_hw_onecell_data sun60i_a733_hw_clks = {
@@ -548,6 +1571,101 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = { [CLK_APB_UART] = &apb_uart_clk.common.hw, [CLK_TRACE] = &trace_clk.common.hw, [CLK_MBUS] = &mbus_clk.common.hw, + [CLK_TIMER0] = &timer0_clk.common.hw, + [CLK_TIMER1] = &timer1_clk.common.hw, + [CLK_TIMER2] = &timer2_clk.common.hw, + [CLK_TIMER3] = &timer3_clk.common.hw, + [CLK_TIMER4] = &timer4_clk.common.hw, + [CLK_TIMER5] = &timer5_clk.common.hw, + [CLK_TIMER6] = &timer6_clk.common.hw, + [CLK_TIMER7] = &timer7_clk.common.hw, + [CLK_TIMER8] = &timer8_clk.common.hw, + [CLK_TIMER9] = &timer9_clk.common.hw, + [CLK_AVS] = &avs_clk.common.hw, + [CLK_DE0] = &de0_clk.common.hw, + [CLK_DI] = &di_clk.common.hw, + [CLK_G2D] = &g2d_clk.common.hw, + [CLK_EINK] = &eink_clk.common.hw, + [CLK_EINK_PANEL] = &eink_panel_clk.common.hw, + [CLK_VE_ENC0] = &ve_enc0_clk.common.hw, + [CLK_VE_DEC0] = &ve_dec0_clk.common.hw, + [CLK_CE] = &ce_clk.common.hw, + [CLK_NPU] = &npu_clk.common.hw, + [CLK_GPU0] = &gpu0_clk.common.hw, + [CLK_DRAM0] = &dram0_clk.common.hw, + [CLK_NAND0_CLK0] = &nand0_clk0_clk.common.hw, + [CLK_NAND0_CLK1] = &nand0_clk1_clk.common.hw, + [CLK_MMC0] = &mmc0_clk.common.hw, + [CLK_MMC1] = &mmc1_clk.common.hw, + [CLK_MMC2] = &mmc2_clk.common.hw, + [CLK_MMC3] = &mmc3_clk.common.hw, + [CLK_UFS_AXI] = &ufs_axi_clk.common.hw, + [CLK_UFS_CFG] = &ufs_cfg_clk.common.hw, + [CLK_SPI0] = &spi0_clk.common.hw, + [CLK_SPI1] = &spi1_clk.common.hw, + [CLK_SPI2] = &spi2_clk.common.hw, + [CLK_SPIF] = &spif_clk.common.hw, + [CLK_SPI3] = &spi3_clk.common.hw, + [CLK_SPI4] = &spi4_clk.common.hw, + [CLK_GPADC0_24M] = &gpadc0_24m_clk.common.hw, + [CLK_IRRX] = &irrx_clk.common.hw, + [CLK_IRTX] = &irtx_clk.common.hw, + [CLK_SGPIO] = &sgpio_clk.common.hw, + [CLK_LPC] = &lpc_clk.common.hw, + [CLK_I2SPCM0] = &i2spcm0_clk.common.hw, + [CLK_I2SPCM1] = &i2spcm1_clk.common.hw, + [CLK_I2SPCM2] = &i2spcm2_clk.common.hw, + [CLK_I2SPCM2_ASRC] = &i2spcm2_asrc_clk.common.hw, + [CLK_I2SPCM3] = &i2spcm3_clk.common.hw, + [CLK_I2SPCM4] = &i2spcm4_clk.common.hw, + [CLK_SPDIF_TX] = &spdif_tx_clk.common.hw, + [CLK_SPDIF_RX] = &spdif_rx_clk.common.hw, + [CLK_DMIC] = &dmic_clk.common.hw, + [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, + [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, + [CLK_USB01_REF] = &usb01_ref_clk.common.hw, + [CLK_USB2_U2_REF] = &usb2_u2_ref_clk.common.hw, + [CLK_USB2_SUSPEND] = &usb2_suspend_clk.common.hw, + [CLK_USB2_MF] = &usb2_mf_clk.common.hw, + [CLK_USB2_U3_UTMI] = &usb2_u3_utmi_clk.common.hw, + [CLK_USB2_U2_PIPE] = &usb2_u2_pipe_clk.common.hw, + [CLK_PCIE_AUX] = &pcie_aux_clk.common.hw, + [CLK_PCIE_AXI_SLV] = &pcie_axi_slv_clk.common.hw, + [CLK_SERDES_PHY] = &serdes_phy_clk.common.hw, + [CLK_GMAC_PTP] = &gmac_ptp_clk.common.hw, + [CLK_GMAC0_PHY] = &gmac0_phy_clk.common.hw, + [CLK_GMAC1_PHY] = &gmac1_phy_clk.common.hw, + [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw, + [CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw, + [CLK_TCON_LCD2] = &tcon_lcd2_clk.common.hw, + [CLK_DSI0] = &dsi0_clk.common.hw, + [CLK_DSI1] = &dsi1_clk.common.hw, + [CLK_COMBPHY0] = &combphy0_clk.common.hw, + [CLK_COMBPHY1] = &combphy1_clk.common.hw, + [CLK_EDP_TV] = &edp_tv_clk.common.hw, + [CLK_HDMI_CEC_32K] = &hdmi_cec_32k_clk.common.hw, + [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw, + [CLK_HDMI_TV] = &hdmi_tv_clk.common.hw, + [CLK_HDMI_SFR] = &hdmi_sfr_clk.common.hw, + [CLK_HDCP_ESM] = &hdcp_esm_clk.common.hw, + [CLK_LEDC] = &ledc_clk.common.hw, + [CLK_CSI_MASTER0] = &csi_master0_clk.common.hw, + [CLK_CSI_MASTER1] = &csi_master1_clk.common.hw, + [CLK_CSI_MASTER2] = &csi_master2_clk.common.hw, + [CLK_CSI] = &csi_clk.common.hw, + [CLK_ISP] = &isp_clk.common.hw, + [CLK_RES_DCAP_24M] = &res_dcap_24m_clk.common.hw, + [CLK_APB2JTAG] = &apb2jtag_clk.common.hw, + [CLK_FANOUT_24M] = &fanout_24M_clk.common.hw, + [CLK_FANOUT_12M] = &fanout_12M_clk.common.hw, + [CLK_FANOUT_16M] = &fanout_16M_clk.common.hw, + [CLK_FANOUT_25M] = &fanout_25M_clk.common.hw, + [CLK_FANOUT_27M] = &fanout_27M_clk.common.hw, + [CLK_FANOUT_PCLK] = &fanout_pclk_clk.common.hw, + [CLK_FANOUT0] = &fanout0_clk.common.hw, + [CLK_FANOUT1] = &fanout1_clk.common.hw, + [CLK_FANOUT2] = &fanout2_clk.common.hw, + [CLK_FANOUT3] = &fanout3_clk.common.hw, }, .num = CLK_FANOUT3 + 1, };
Signature · 1 line
2.54.0
[email protected]
AI reviewRe: [PATCH v2 6/8] clk: sunxi-ng: a733: Add mod clocks support
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
Pre-existing issues:
- [Critical] Undefined Behavior in ccu_mp_set_rate() due to GENMASK(-1, 0) silently clears clock registers. --
--- Patch [6]: [PATCH v2 6/8] clk: sunxi-ng: a733: Add mod clocks support --- commit 9fae602071158ab4bb78bf12e40f53a7e4b2f550
Author: Junhui Liu <[email protected]>
clk: sunxi-ng: a733: Add mod clocks support
Add the module clocks found in the Allwinner A733 SoC, including video, storage, interfaces and others. This implementation accounts for changes in register offsets and introduces support for new modules.
Quoted 4 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +0
-0
[ ... ]
drivers/clk/sunxi-ng/ccu-sun60i-a733.c static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x58 · line 483
Quoted 6 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +6
-0+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer0_clk, "timer0", timer_parents, 0x800, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0);
[Severity: Critical]
This is a pre-existing issue, but won't specifying a width of 0 for the M divider cause undefined behavior in the CCU framework?
When a driver or the clock framework calls clk_set_rate() on these newly introduced clocks (e.g., timer0_clk through timer9_clk, mbus_clk), ccu_mp_set_rate() clears the M and P divider fields:
drivers/clk/sunxi-ng/ccu_mp.c:ccu_mp_set_rate() {
...
reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);
reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);
...
}Because these clocks are instantiated with width = 0, this evaluates to ~GENMASK(-1, 0) at runtime. GENMASK(-1, 0) computes ~0UL >> 64. On ARM64 hardware, the dynamic shift amount is read from the bottom 6 bits of the register (64 & 63 == 0), resulting in a shift of 0, leaving the value as ~0UL (all ones).
The ~GENMASK thus evaluates to 0, which completely zeroes the hardware register, including the clock gate bit (BIT(31)).
[ ... ]
drivers/clk/sunxi-ng/ccu-sun60i-a733.c static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x58 · line 713
Quoted 7 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +7
-0+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(dram0_clk, "dram0", dram_parents, 0xc00, +0 ,4 ,/* M */ +0 ,0 ,/* no P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ +CLK_IS_CRITICAL , + CCU_FEATURE_UPDATE_BIT);
[Severity: Critical]
This isn't a bug introduced by this patch, but dram0_clk is instantiated with a P width of 0. Calling set_rate on it will trigger ~GENMASK(-1, 0) and wipe its register. Since this is the DRAM clock, won't disabling it instantly hang the system?
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=6
Re: [PATCH v2 6/8] clk: sunxi-ng: a733: Add mod clocks support
In reply to Junhui LiuOn Sat Jul 11, 2026 at 4:10 PM CST, Junhui Liu wrote:
[...]
Quoted 1 line
+static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer0_clk, "timer0",
timer_parents,0x800,
I will update these to SUNXI_CCU_P_DATA_WITH_MUX_GATE in next version.
Quoted 59 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +59
-0+0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer1_clk, "timer1", timer_parents, 0x804, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer2_clk, "timer2", timer_parents, 0x808, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer3_clk, "timer3", timer_parents, 0x80c, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer4_clk, "timer4", timer_parents, 0x810, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer5_clk, "timer5", timer_parents, 0x814, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer6_clk, "timer6", timer_parents, 0x818, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer7_clk, "timer7", timer_parents, 0x81c, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer8_clk, "timer8", timer_parents, 0x820, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0); +static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer9_clk, "timer9", timer_parents, 0x824, +0 ,0 ,/* no M */ +0 ,3 ,/* P */ +24 ,3 ,/* mux */ +BIT (31 ),/* gate */ + 0);
[...]
Signature · 2 lines
Best regards, Junhui Liu
PATCH v2 7/8 clk: sunxi-ng: a733: Add bus clock gates
In reply to Junhui LiuAdd the bus clock gates that control access to the devices' register interface on the Allwinner A733 SoC. These clocks are typically single-bit controls in the BGR registers, covering UARTs, SPI, I2C, and various multimedia engines. It also includes bus gates for system components like the IOMMU and MSI-lite interfaces.
Also mark ahb-store and mbus-store clocks as critical, since disabling either gate breaks access to boot/storage devices such as MMC and SPI NOR when unused clocks are disabled.
Tested-by Jerome Brunet <[email protected]>
Signed-off-by Junhui Liu <[email protected]>
--- drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 488 ++++++++++++++++++++++++++++++++- 1 file changed, 487 insertions(+), 1 deletion(-)
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +487 -1
@@ -412,16 +412,19 @@ static SUNXI_CCU_M_DATA_WITH_MUX(ahb_clk, "ahb", ahb_apb_parents, 0x500,0 ,5 ,/* M */ 24 ,2 ,/* mux */ 0); +static const struct clk_hw *ahb_hws[] = { &ahb_clk.common.hw }; static SUNXI_CCU_M_DATA_WITH_MUX(apb0_clk, "apb0", ahb_apb_parents, 0x510,0 ,5 ,/* M */ 24 ,2 ,/* mux */ 0); +static const struct clk_hw *apb0_hws[] = { &apb0_clk.common.hw }; static SUNXI_CCU_M_DATA_WITH_MUX(apb1_clk, "apb1", ahb_apb_parents, 0x518,0 ,5 ,/* M */ 24 ,2 ,/* mux */ 0); +static const struct clk_hw *apb1_hws[] = { &apb1_clk.common.hw };static const struct clk_parent_data apb_uart_parents[] = { { .hw = &sys_24M_clk.hw },
@@ -434,6 +437,9 @@ static SUNXI_CCU_M_DATA_WITH_MUX(apb_uart_clk, "apb-uart", apb_uart_parents, 0x50 ,5 ,/* M */ 24 ,3 ,/* mux */ 0); +static const struct clk_hw *apb_uart_hws[] = { + &apb_uart_clk.common.hw +};static const struct clk_parent_data trace_parents[] = { { .hw = &sys_24M_clk.hw },
@@ -448,6 +454,8 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(trace_clk, "trace", trace_parents, 0x540,BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_its_pcie0_aclk_clk, "bus-its-pcie0-aclk", hosc, 0x574, BIT(1), 0); +static const struct clk_parent_data mbus_parents[] = { { .hw = &sys_24M_clk.hw }, { .hw = &pll_periph1_600M_clk.hw },
@@ -463,9 +471,118 @@ static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x58BIT (31 ),/* gate */ CLK_IS_CRITICAL , CCU_FEATURE_UPDATE_BIT); +static const struct clk_hw *mbus_hws[] = { &mbus_clk.common.hw }; + +static SUNXI_CCU_GATE_HWS(mbus_iommu0_sys_clk, "mbus-iommu0-sys", mbus_hws, 0x58c, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(apb_iommu0_sys_clk, "apb-iommu0-sys", apb0_hws, 0x58c, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(ahb_iommu0_sys_clk, "ahb-iommu0-sys", ahb_hws, 0x58c, BIT(2), 0); + +static SUNXI_CCU_GATE_DATA(bus_msi_lite0_clk, "bus-msi-lite0", hosc, 0x594, BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_msi_lite1_clk, "bus-msi-lite1", hosc, 0x59c, BIT(0), 0); +static SUNXI_CCU_GATE_DATA(bus_msi_lite2_clk, "bus-msi-lite2", hosc, 0x5a4, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(mbus_iommu1_sys_clk, "mbus-iommu1-sys", mbus_hws, 0x5b4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(apb_iommu1_sys_clk, "apb_iommu1-sys", apb0_hws, 0x5b4, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(ahb_iommu1_sys_clk, "ahb_iommu1-sys", ahb_hws, 0x5b4, BIT(2), 0); + +static SUNXI_CCU_GATE_HWS(ahb_ve_dec_clk, "ahb-ve-dec", ahb_hws, + 0x5c0, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(ahb_ve_enc_clk, "ahb-ve-enc", ahb_hws, + 0x5c0, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(ahb_vid_in_clk, "ahb-vid-in", ahb_hws, + 0x5c0, BIT(2), 0); +static SUNXI_CCU_GATE_HWS(ahb_vid_cout0_clk, "ahb-vid-cout0", ahb_hws, + 0x5c0, BIT(3), 0); +static SUNXI_CCU_GATE_HWS(ahb_vid_cout1_clk, "ahb-vid-cout1", ahb_hws, + 0x5c0, BIT(4), 0); +static SUNXI_CCU_GATE_HWS(ahb_de_clk, "ahb-de", ahb_hws, + 0x5c0, BIT(5), 0); +static SUNXI_CCU_GATE_HWS(ahb_npu_clk, "ahb-npu", ahb_hws, + 0x5c0, BIT(6), 0); +static SUNXI_CCU_GATE_HWS(ahb_gpu0_clk, "ahb-gpu0", ahb_hws, + 0x5c0, BIT(7), 0); +static SUNXI_CCU_GATE_HWS(ahb_serdes_clk, "ahb-serdes", ahb_hws, + 0x5c0, BIT(8), 0); +static SUNXI_CCU_GATE_HWS(ahb_usb_sys_clk, "ahb-usb-sys", ahb_hws, + 0x5c0, BIT(9), 0); +static SUNXI_CCU_GATE_HWS(ahb_msi_lite0_clk, "ahb-msi-lite0", ahb_hws, + 0x5c0, BIT(16), 0); +static SUNXI_CCU_GATE_HWS(ahb_store_clk, "ahb-store", ahb_hws, + 0x5c0, BIT(24), CLK_IS_CRITICAL); +static SUNXI_CCU_GATE_HWS(ahb_cpus_clk, "ahb-cpus", ahb_hws, + 0x5c0, BIT(28), 0); + +static SUNXI_CCU_GATE_HWS(mbus_iommu0_clk, "mbus-iommu0", mbus_hws, + 0x5e0, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(mbus_iommu1_clk, "mbus-iommu1", mbus_hws, + 0x5e0, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(mbus_desys_clk, "mbus-desys", mbus_hws, + 0x5e0, BIT(11), 0); +static SUNXI_CCU_GATE_HWS(mbus_ve_enc0_gate_clk, "mbus-ve-enc0-gate", mbus_hws, + 0x5e0, BIT(12), 0); +static SUNXI_CCU_GATE_HWS(mbus_ve_dec0_gate_clk, "mbus-ve-dec0-gate", mbus_hws, + 0x5e0, BIT(14), 0); +static SUNXI_CCU_GATE_HWS(mbus_gpu0_clk, "mbus-gpu0", mbus_hws, + 0x5e0, BIT(16), 0); +static SUNXI_CCU_GATE_HWS(mbus_npu_clk, "mbus-npu", mbus_hws, + 0x5e0, BIT(18), 0); +static SUNXI_CCU_GATE_HWS(mbus_vid_in_clk, "mbus-vid-in", mbus_hws, + 0x5e0, BIT(24), 0); +static SUNXI_CCU_GATE_HWS(mbus_serdes_clk, "mbus-serdes", mbus_hws, + 0x5e0, BIT(28), 0); +static SUNXI_CCU_GATE_HWS(mbus_msi_lite0_clk, "mbus-msi-lite0", mbus_hws, + 0x5e0, BIT(29), 0); +static SUNXI_CCU_GATE_HWS(mbus_store_clk, "mbus-store", mbus_hws, + 0x5e0, BIT(30), CLK_IS_CRITICAL); +static SUNXI_CCU_GATE_HWS(mbus_msi_lite2_clk, "mbus-msi-lite2", mbus_hws, + 0x5e0, BIT(31), 0); + +static SUNXI_CCU_GATE_HWS(mbus_dma0_clk, "mbus-dma0", mbus_hws, + 0x5e4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(mbus_ve_enc0_clk, "mbus-ve-enc0", mbus_hws, + 0x5e4, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws, + 0x5e4, BIT(2), 0); +static SUNXI_CCU_GATE_HWS(mbus_dma1_clk, "mbus-dma1", mbus_hws, + 0x5e4, BIT(3), 0); +static SUNXI_CCU_GATE_HWS(mbus_nand_clk, "mbus-nand", mbus_hws, + 0x5e4, BIT(5), 0); +static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws, + 0x5e4, BIT(8), 0); +static SUNXI_CCU_GATE_HWS(mbus_isp_clk, "mbus-isp", mbus_hws, + 0x5e4, BIT(9), 0); +static SUNXI_CCU_GATE_HWS(mbus_gmac0_clk, "mbus-gmac0", mbus_hws, + 0x5e4, BIT(11), 0); +/* Undocumented, taken from the vendor kernel. */ +static SUNXI_CCU_GATE_HWS(mbus_gmac1_clk, "mbus-gmac1", mbus_hws, + 0x5e4, BIT(12), 0); +static SUNXI_CCU_GATE_HWS(mbus_ve_dec0_clk, "mbus-ve-dec0", mbus_hws, + 0x5e4, BIT(18), 0); + +static SUNXI_CCU_GATE_HWS(bus_dma0_clk, "bus-dma0", ahb_hws, + 0x704, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_dma1_clk, "bus-dma1", ahb_hws, + 0x70c, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", ahb_hws, + 0x724, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_msgbox0_clk, "bus-msgbox0", ahb_hws, + 0x744, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_pwm0_clk, "bus-pwm0", apb0_hws, + 0x784, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_pwm1_clk, "bus-pwm1", apb0_hws, + 0x78c, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", sys_24M_hws, + 0x7a4, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_sysdap_clk, "bus-sysdap", apb1_hws, + 0x7ac, BIT(0), 0);/************************************************************************** -* mod clocks * +* mod clocks with gates * **************************************************************************/ static const struct clk_parent_data timer_parents[] = {
@@ -535,6 +652,7 @@ static SUNXI_CCU_MP_DATA_WITH_MUX_GATE(timer9_clk, "timer9", timer_parents, 0x8224 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_timer_clk, "bus-timer", ahb_hws, 0x850, BIT(0), 0); /* Undocumented, taken from the vendor kernel. */ static const struct clk_parent_data avs_parents[] = {
@@ -560,6 +678,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(de0_clk, "de0", de_parents, 0xa00,24 ,3 ,/* mux */ BIT (31 ),/* gate */ CLK_SET_RATE_PARENT); +static SUNXI_CCU_GATE_HWS(bus_de0_clk, "bus-de0", ahb_hws, 0xa04, BIT(0), 0);static const struct clk_hw *di_parents[] = { &pll_periph0_600M_clk.hw,
@@ -573,6 +692,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(di_clk, "di", di_parents, 0xa20,24 ,3 ,/* mux */ BIT (31 ),/* gate */ CLK_SET_RATE_PARENT); +static SUNXI_CCU_GATE_HWS(bus_di_clk, "bus-di", ahb_hws, 0xa24, BIT(0), 0);static const struct clk_hw *g2d_parents[] = { &pll_periph0_400M_clk.hw,
@@ -585,6 +705,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(g2d_clk, "g2d", g2d_parents, 0xa40,24 ,3 ,/* mux */ BIT (31 ),/* gate */ CLK_SET_RATE_PARENT); +static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", ahb_hws, 0xa44, BIT(0), 0);static const struct clk_hw *eink_parents[] = { &pll_periph0_480M_clk.common.hw,
@@ -608,6 +729,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(eink_panel_clk, "eink-panel", eink_panel_par24 ,3 ,/* mux */ BIT (31 ),/* gate */ CLK_SET_RATE_PARENT); +static SUNXI_CCU_GATE_HWS(bus_eink_clk, "bus-eink", ahb_hws, 0xa6c, BIT(0), 0);static const struct clk_hw *ve_enc_parents[] = { &pll_ve0_clk.common.hw,
@@ -639,6 +761,9 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(ve_dec0_clk, "ve-dec0", ve_dec_parents, 0xa8BIT (31 ),/* gate */ CLK_SET_RATE_PARENT); +static SUNXI_CCU_GATE_HWS(bus_ve_enc0_clk, "bus-ve-enc0", ahb_hws, 0xa8c, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_ve_dec0_clk, "bus-ve-dec0", ahb_hws, 0xa8c, BIT(2), 0); +static const struct clk_hw *ce_parents[] = { &sys_24M_clk.hw, &pll_periph0_400M_clk.hw,
@@ -649,6 +774,8 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0xac0,24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", ahb_hws, 0xac4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_ce_sys_clk, "bus-ce-sys", ahb_hws, 0xac4, BIT(1), 0);static const struct clk_hw *npu_parents[] = { &pll_npu_clk.common.hw,
@@ -664,6 +791,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(npu_clk, "npu", npu_parents, 0xb00,24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_npu_clk, "bus-npu", hosc, 0xb04, BIT(0), 0);/* * GPU_CLK = ClockSource * ((16 - M) / 16)
@@ -696,6 +824,7 @@ static struct ccu_div gpu0_clk = { &ccu_div_ops, 0), } }; +static SUNXI_CCU_GATE_HWS(bus_gpu0_clk, "bus-gpu0", ahb_hws, 0xb24, BIT(0), 0);static const struct clk_parent_data dram_parents[] = { { .hw = &pll_ddr_clk.common.hw, },
@@ -711,6 +840,8 @@ static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(dram0_clk, "dram0", dram_parents, 0xBIT (31 ),/* gate */ CLK_IS_CRITICAL , CCU_FEATURE_UPDATE_BIT); +static SUNXI_CCU_GATE_HWS(bus_dram0_clk, "bus-dram0", ahb_hws, 0xc0c, + BIT(0), CLK_IS_CRITICAL);static const struct clk_parent_data nand_mmc_parents[] = { { .hw = &sys_24M_clk.hw, },
@@ -729,6 +860,7 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(nand0_clk1_clk, "nand0-clk1", nand_mmc_par24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_nand0_clk, "bus-nand0", ahb_hws, 0xc8c, BIT(0), 0); static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc0_clk, "mmc0", nand_mmc_parents, 0xd00, 0, 5, /* M */
@@ -737,6 +869,8 @@ static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc0_clk, "mmc0", nand_mmc_parents,BIT (31 ),/* gate */ 2 ,/* post div */ 0); +static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", ahb_hws, 0xd0c, BIT(0), 0); + static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc1_clk, "mmc1", nand_mmc_parents, 0xd10,0 ,5 ,/* M */ 8, 5, /* P */
@@ -744,6 +878,7 @@ static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc1_clk, "mmc1", nand_mmc_parents,BIT (31 ),/* gate */ 2 ,/* post div */ 0); +static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", ahb_hws, 0xd1c, BIT(0), 0);static const struct clk_parent_data mmc2_mmc3_parents[] = { { .hw = &sys_24M_clk.hw, },
@@ -759,6 +894,8 @@ static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc2_clk, "mmc2", mmc2_mmc3_parentsBIT (31 ),/* gate */ 2 ,/* post div */ 0); +static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", ahb_hws, 0xd2c, BIT(0), 0); + static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc3_clk, "mmc3", mmc2_mmc3_parents, 0xd30,0 ,5 ,/* M */ 8, 5, /* P */
@@ -766,6 +903,7 @@ static SUNXI_CCU_MP_MUX_GATE_POSTDIV_DUALDIV(mmc3_clk, "mmc3", mmc2_mmc3_parentsBIT (31 ),/* gate */ 2 ,/* post div */ 0); +static SUNXI_CCU_GATE_HWS(bus_mmc3_clk, "bus-mmc3", ahb_hws, 0xd3c, BIT(0), 0);static const struct clk_hw *ufs_axi_parents[] = { &pll_periph0_300M_clk.hw,
@@ -786,6 +924,29 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ufs_cfg_clk, "ufs-cfg", ufs_cfg_parents, 0 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_ufs_clk, "bus-ufs", hosc, 0xd8c, BIT(0), 0); + +staticSUNXI_CCU_GATE_HWS (bus_uart0_clk,"bus-uart0" , apb_uart_hws,0xe00 ,BIT (0 ),0 ); +static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb_uart_hws, 0xe04, BIT(0), 0); +staticSUNXI_CCU_GATE_HWS (bus_uart2_clk,"bus-uart2" , apb_uart_hws,0xe08 ,BIT (0 ),0 ); +static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb_uart_hws, 0xe0c, BIT(0), 0); +staticSUNXI_CCU_GATE_HWS (bus_uart4_clk,"bus-uart4" , apb_uart_hws,0xe10 ,BIT (0 ),0 ); +static SUNXI_CCU_GATE_HWS(bus_uart5_clk, "bus-uart5", apb_uart_hws, 0xe14, BIT(0), 0); +staticSUNXI_CCU_GATE_HWS (bus_uart6_clk,"bus-uart6" , apb_uart_hws,0xe18 ,BIT (0 ),0 ); + +static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws, 0xe80, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws, 0xe84, BIT(0), 0); +staticSUNXI_CCU_GATE_HWS (bus_i2c2_clk,"bus-i2c2" , apb1_hws,0xe88 ,BIT (0 ),0 ); +static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws, 0xe8c, BIT(0), 0); +staticSUNXI_CCU_GATE_HWS (bus_i2c4_clk,"bus-i2c4" , apb1_hws,0xe90 ,BIT (0 ),0 ); +static SUNXI_CCU_GATE_HWS(bus_i2c5_clk, "bus-i2c5", apb1_hws, 0xe94, BIT(0), 0); +staticSUNXI_CCU_GATE_HWS (bus_i2c6_clk,"bus-i2c6" , apb1_hws,0xe98 ,BIT (0 ),0 ); +static SUNXI_CCU_GATE_HWS(bus_i2c7_clk, "bus-i2c7", apb1_hws, 0xe9c, BIT(0), 0); +staticSUNXI_CCU_GATE_HWS (bus_i2c8_clk,"bus-i2c8" , apb1_hws,0xea0 ,BIT (0 ),0 ); +static SUNXI_CCU_GATE_HWS(bus_i2c9_clk, "bus-i2c9", apb1_hws, 0xea4, BIT(0), 0); +staticSUNXI_CCU_GATE_HWS (bus_i2c10_clk,"bus-i2c10" , apb1_hws,0xea8 ,BIT (0 ),0 ); +static SUNXI_CCU_GATE_HWS(bus_i2c11_clk, "bus-i2c11", apb1_hws, 0xeac, BIT(0), 0); +staticSUNXI_CCU_GATE_HWS (bus_i2c12_clk,"bus-i2c12" , apb1_hws,0xeb0 ,BIT (0 ),0 );static const struct clk_parent_data spi_parents[] = { { .hw = &sys_24M_clk.hw },
@@ -803,18 +964,23 @@ static SUNXI_CCU_DUALDIV_MUX_GATE(spi0_clk, "spi0", spi_parents, 0xf00, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", ahb_hws, 0xf04, BIT(0), 0); + staticSUNXI_CCU_DUALDIV_MUX_GATE (spi1_clk,"spi1" , spi_parents,0xf08 ,0 ,5 ,/* M */ 8 ,5 ,/* N */ 24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0 ); +static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", ahb_hws, 0xf0c, BIT(0), 0); + staticSUNXI_CCU_DUALDIV_MUX_GATE (spi2_clk,"spi2" , spi_parents,0xf10 ,0 ,5 ,/* M */ 8 ,5 ,/* N */ 24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0 ); +static SUNXI_CCU_GATE_HWS(bus_spi2_clk, "bus-spi2", ahb_hws, 0xf14, BIT(0), 0); static const struct clk_parent_data spif_parents[] = { { .hw = &sys_24M_clk.hw },
@@ -832,12 +998,16 @@ static SUNXI_CCU_DUALDIV_MUX_GATE(spif_clk, "spif", spif_parents, 0xf18, 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_spif_clk, "bus-spif", ahb_hws, 0xf1c, BIT(0), 0); + staticSUNXI_CCU_DUALDIV_MUX_GATE (spi3_clk,"spi3" , spi_parents,0xf20 ,0 ,5 ,/* M */ 8 ,5 ,/* N */ 24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0 ); +static SUNXI_CCU_GATE_HWS(bus_spi3_clk, "bus-spi3", ahb_hws, 0xf24, BIT(0), 0); + /* Undocumented, taken from the vendor kernel. */ static SUNXI_CCU_DUALDIV_MUX_GATE(spi4_clk, "spi4", spi_parents, 0xf28, 0, 5, /* M */
@@ -845,6 +1015,7 @@ static SUNXI_CCU_DUALDIV_MUX_GATE(spi4_clk, "spi4", spi_parents, 0xf28,24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_spi4_clk, "bus-spi4", ahb_hws, 0xf2c, BIT(0), 0);static const struct clk_parent_data gpadc0_24m_parents[] = { { .hw = &sys_24M_clk.hw },
@@ -855,6 +1026,9 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(gpadc0_24m_clk, "gpadc0-24m", gpadc0_24m_p24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_gpadc0_clk, "bus-gpadc0", ahb_hws, 0xfc4, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_ths0_clk, "bus-ths0", apb0_hws, 0xfe4, BIT(0), 0);static const struct clk_parent_data irrx_parents[] = { { .fw_name ="losc" },
@@ -866,6 +1040,7 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irrx_clk, "irrx", irrx_parents, 0x1000,24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_irrx_clk, "bus-irrx", apb0_hws, 0x1004, BIT(0), 0);static const struct clk_parent_data irtx_parents[] = { { .fw_name ="losc" },
@@ -877,6 +1052,9 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(irtx_clk, "irtx", irtx_parents, 0x1008,24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_irtx_clk, "bus-irtx", apb0_hws, 0x100c, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_lradc_clk, "bus-lradc", apb0_hws, 0x1024, BIT(0), 0);/* Undocumented, taken from the vendor kernel. */ static const struct clk_parent_data sgpio_parents[] = {
@@ -888,6 +1066,7 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(sgpio_clk, "sgpio", sgpio_parents, 0x1060,24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_sgpio_clk, "bus-sgpio", hosc, 0x1064, BIT(0), 0); /* Undocumented, taken from the vendor kernel. */ static const struct clk_hw *lpc_parents[] = {
@@ -901,6 +1080,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(lpc_clk, "lpc", lpc_parents, 0x1080,24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_lpc_clk, "bus-lpc", hosc, 0x1084, BIT(0), 0);static const struct clk_hw *i2spcm_parents[] = { &pll_audio0_4x_clk.common.hw,
@@ -913,11 +1093,15 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm0_clk, "i2spcm0", i2spcm_parents, 0x12 24, 3, /* mux */ BIT(31), /* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_i2spcm0_clk, "bus-i2spcm0", hosc, 0x120c, BIT(0), 0); + staticSUNXI_CCU_M_HW_WITH_MUX_GATE (i2spcm1_clk,"i2spcm1" , i2spcm_parents,0x1210 ,0 ,5 ,/* M */ 24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0 ); +static SUNXI_CCU_GATE_DATA(bus_i2spcm1_clk, "bus-i2spcm1", hosc, 0x121c, BIT(0), 0); + static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_clk, "i2spcm2", i2spcm_parents, 0x1220, 0, 5, /* M */ 24, 3, /* mux */
@@ -936,16 +1120,22 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm2_asrc_clk, "i2spcm2_asrc", i2spcm2_as24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); + +static SUNXI_CCU_GATE_DATA(bus_i2spcm2_clk, "bus-i2spcm2", hosc, 0x122c, BIT(0), 0); + static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm3_clk, "i2spcm3", i2spcm_parents, 0x1230,0 ,5 ,/* M */ 24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_i2spcm3_clk, "bus-i2spcm3", hosc, 0x123c, BIT(0), 0); + static SUNXI_CCU_M_HW_WITH_MUX_GATE(i2spcm4_clk, "i2spcm4", i2spcm_parents, 0x1240,0 ,5 ,/* M */ 24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_i2spcm4_clk, "bus-i2spcm4", hosc, 0x124c, BIT(0), 0);static const struct clk_hw *spdif_tx_parents[] = { &pll_audio0_4x_clk.common.hw,
@@ -969,6 +1159,8 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(spdif_rx_clk, "spdif-rx", spdif_rx_parents,BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_spdif_clk, "bus-spdif", apb1_hws, 0x128c, BIT(0), 0); +static const struct clk_hw *dmic_parents[] = { &pll_audio0_4x_clk.common.hw, &pll_audio1_div2_clk.common.hw,
@@ -980,6 +1172,8 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(dmic_clk, "dmic", dmic_parents, 0x12c0,BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_dmic_clk, "bus-dmic", apb1_hws, 0x12cc, BIT(0), 0); +/* * The first parent is a 48 MHz input clock divided by 4. That 48 MHz clock is * a 2x multiplier from pll-ref synchronized by pll-periph0, and is also used by
@@ -1011,6 +1205,9 @@ static struct ccu_mux usb_ohci0_clk = { &ccu_mux_ops, 0), }, }; +static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", ahb_hws, 0x1304, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_ehci0_clk, "bus-ehci0", ahb_hws, 0x1304, BIT(4), 0); +static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", ahb_hws, 0x1304, BIT(8), 0);static struct ccu_mux usb_ohci1_clk = { .enable =BIT (31 ),
@@ -1027,6 +1224,8 @@ static struct ccu_mux usb_ohci1_clk = { &ccu_mux_ops, 0), }, }; +static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", ahb_hws, 0x130c, BIT(0), 0); +staticSUNXI_CCU_GATE_HWS (bus_ehci1_clk,"bus-ehci1" , ahb_hws,0x130c ,BIT (4 ),0 );static const struct clk_parent_data usb01_ref_parents[] = { { .hw = &sys_24M_clk.hw },
@@ -1129,11 +1328,14 @@ static SUNXI_CCU_M_HWS_WITH_GATE(gmac0_phy_clk, "gmac0-phy", pll_periph0_150M_hw0 ,5 ,/* M */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_gmac0_clk, "bus-gmac0", ahb_hws, 0x141c, BIT(0), 0); + /* Undocumented, taken from the vendor kernel. */ staticSUNXI_CCU_M_HWS_WITH_GATE (gmac1_phy_clk,"gmac1-phy" , pll_periph0_150M_hws,0x1420 ,0 ,5 ,/* M */ BIT (31 ),/* gate */ 0 ); +static SUNXI_CCU_GATE_HWS(bus_gmac1_clk, "bus-gmac1", ahb_hws, 0x142c, BIT(0), 0);static const struct clk_hw *tcon_lcd_parents[] = { &pll_video0_4x_clk.common.hw,
@@ -1146,17 +1348,22 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_lcd_parents24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_tcon_lcd0_clk, "bus-tcon-lcd0", ahb_hws, 0x1504, BIT(0), 0); + static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_lcd_parents, 0x1508,0 ,5 ,/* M */ 24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_tcon_lcd1_clk, "bus-tcon-lcd1", ahb_hws, 0x150c, BIT(0), 0); + /* Undocumented, taken from the vendor kernel. */ staticSUNXI_CCU_M_HW_WITH_MUX_GATE (tcon_lcd2_clk,"tcon-lcd2" , tcon_lcd_parents,0x1510 ,0 ,5 ,/* M */ 24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0 ); +static SUNXI_CCU_GATE_HWS(bus_tcon_lcd2_clk, "bus-tcon-lcd2", ahb_hws, 0x1514, BIT(0), 0);static const struct clk_hw *dsi_parents[] = { &sys_24M_clk.hw,
@@ -1168,11 +1375,14 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi0_clk, "dsi0", dsi_parents, 0x1580,24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_dsi0_clk, "bus-dsi0", ahb_hws, 0x1584, BIT(0), 0); + static SUNXI_CCU_M_HW_WITH_MUX_GATE(dsi1_clk, "dsi1", dsi_parents, 0x1588,0 ,5 ,/* M */ 24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_dsi1_clk, "bus-dsi1", ahb_hws, 0x158c, BIT(0), 0);static const struct clk_hw *combphy_parents[] = { &pll_video0_4x_clk.common.hw,
@@ -1192,6 +1402,9 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(combphy1_clk, "combphy1", combphy_parents, 0BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_tcon_tv0_clk, "bus-tcon-tv0", ahb_hws, 0x1604, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_tcon_tv1_clk, "bus-tcon-tv1", ahb_hws, 0x160c, BIT(0), 0); +static const struct clk_hw *edp_tv_parents[] = { &pll_video0_4x_clk.common.hw, &pll_video1_4x_clk.common.hw,
@@ -1203,6 +1416,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(edp_tv_clk, "edp-tv", edp_tv_parents, 0x164024 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_edp_tv_clk, "bus-edp-tv", ahb_hws, 0x164c, BIT(0), 0); static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k", pll_periph0_2x_hws, 0x1680, BIT(30), /* gate */
@@ -1230,6 +1444,7 @@ static SUNXI_CCU_DUALDIV_MUX_GATE(hdmi_tv_clk, "hdmi-tv", hdmi_tv_parents, 0x16824 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_hdmi_tv_clk, "bus-hdmi-tv", ahb_hws, 0x168c, BIT(0), 0);static const struct clk_parent_data hdmi_sfr_parents[] = { { .hw = &sys_24M_clk.hw },
@@ -1242,6 +1457,9 @@ static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_sfr_clk, "hdmi-sfr", hdmi_sfr_parents, static SUNXI_CCU_GATE_HWS(hdcp_esm_clk, "hdcp-esm", pll_periph0_300M_hws, 0x1694, BIT(31), 0); +static SUNXI_CCU_GATE_HWS(bus_dpss_top0_clk, "bus-dpss-top0", ahb_hws, 0x16c4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(bus_dpss_top1_clk, "bus-dpss-top1", ahb_hws, 0x16cc, BIT(0), 0); +static const struct clk_parent_data ledc_parents[] = { { .hw = &sys_24M_clk.hw }, { .hw = &pll_periph0_600M_clk.hw },
@@ -1252,6 +1470,9 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ledc_clk, "ledc", ledc_parents, 0x1700,24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_ledc_clk, "bus-ledc", apb0_hws, 0x1704, BIT(0), 0); + +static SUNXI_CCU_GATE_HWS(bus_dsc_clk, "bus-dsc", ahb_hws, 0x1744, BIT(0), 0);static const struct clk_parent_data csi_master_parents[] = { { .hw = &sys_24M_clk.hw },
@@ -1293,6 +1514,7 @@ static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_clk, "csi", csi_parents, 0x1840,24 ,3 ,/* mux */ BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", ahb_hws, 0x1844, BIT(0), 0);static const struct clk_hw *isp_parents[] = { &pll_video2_4x_clk.common.hw,
@@ -1422,7 +1644,60 @@ static struct ccu_common *sun60i_a733_ccu_clks[] = { &apb1_clk.common, &apb_uart_clk.common, &trace_clk.common, + &bus_its_pcie0_aclk_clk.common, &mbus_clk.common, + &mbus_iommu0_sys_clk.common, + &apb_iommu0_sys_clk.common, + &ahb_iommu0_sys_clk.common, + &bus_msi_lite0_clk.common, + &bus_msi_lite1_clk.common, + &bus_msi_lite2_clk.common, + &mbus_iommu1_sys_clk.common, + &apb_iommu1_sys_clk.common, + &ahb_iommu1_sys_clk.common, + &ahb_ve_dec_clk.common, + &ahb_ve_enc_clk.common, + &ahb_vid_in_clk.common, + &ahb_vid_cout0_clk.common, + &ahb_vid_cout1_clk.common, + &ahb_de_clk.common, + &ahb_npu_clk.common, + &ahb_gpu0_clk.common, + &ahb_serdes_clk.common, + &ahb_usb_sys_clk.common, + &ahb_msi_lite0_clk.common, + &ahb_store_clk.common, + &ahb_cpus_clk.common, + &mbus_iommu0_clk.common, + &mbus_iommu1_clk.common, + &mbus_desys_clk.common, + &mbus_ve_enc0_gate_clk.common, + &mbus_ve_dec0_gate_clk.common, + &mbus_gpu0_clk.common, + &mbus_npu_clk.common, + &mbus_vid_in_clk.common, + &mbus_serdes_clk.common, + &mbus_msi_lite0_clk.common, + &mbus_store_clk.common, + &mbus_msi_lite2_clk.common, + &mbus_dma0_clk.common, + &mbus_ve_enc0_clk.common, + &mbus_ce_clk.common, + &mbus_dma1_clk.common, + &mbus_nand_clk.common, + &mbus_csi_clk.common, + &mbus_isp_clk.common, + &mbus_gmac0_clk.common, + &mbus_gmac1_clk.common, + &mbus_ve_dec0_clk.common, + &bus_dma0_clk.common, + &bus_dma1_clk.common, + &bus_spinlock_clk.common, + &bus_msgbox0_clk.common, + &bus_pwm0_clk.common, + &bus_pwm1_clk.common, + &bus_dbg_clk.common, + &bus_sysdap_clk.common, &timer0_clk.common, &timer1_clk.common, &timer2_clk.common,
@@ -1433,48 +1708,111 @@ static struct ccu_common *sun60i_a733_ccu_clks[] = { &timer7_clk.common, &timer8_clk.common, &timer9_clk.common, + &bus_timer_clk.common, &avs_clk.common, &de0_clk.common, + &bus_de0_clk.common, &di_clk.common, + &bus_di_clk.common, &g2d_clk.common, + &bus_g2d_clk.common, &eink_clk.common, &eink_panel_clk.common, + &bus_eink_clk.common, &ve_enc0_clk.common, &ve_dec0_clk.common, + &bus_ve_enc0_clk.common, + &bus_ve_dec0_clk.common, &ce_clk.common, + &bus_ce_clk.common, + &bus_ce_sys_clk.common, &npu_clk.common, + &bus_npu_clk.common, &gpu0_clk.common, + &bus_gpu0_clk.common, &dram0_clk.common, + &bus_dram0_clk.common, &nand0_clk0_clk.common, &nand0_clk1_clk.common, + &bus_nand0_clk.common, &mmc0_clk.common, + &bus_mmc0_clk.common, &mmc1_clk.common, + &bus_mmc1_clk.common, &mmc2_clk.common, + &bus_mmc2_clk.common, &mmc3_clk.common, + &bus_mmc3_clk.common, &ufs_axi_clk.common, &ufs_cfg_clk.common, + &bus_ufs_clk.common, + &bus_uart0_clk.common, + &bus_uart1_clk.common, + &bus_uart2_clk.common, + &bus_uart3_clk.common, + &bus_uart4_clk.common, + &bus_uart5_clk.common, + &bus_uart6_clk.common, + &bus_i2c0_clk.common, + &bus_i2c1_clk.common, + &bus_i2c2_clk.common, + &bus_i2c3_clk.common, + &bus_i2c4_clk.common, + &bus_i2c5_clk.common, + &bus_i2c6_clk.common, + &bus_i2c7_clk.common, + &bus_i2c8_clk.common, + &bus_i2c9_clk.common, + &bus_i2c10_clk.common, + &bus_i2c11_clk.common, + &bus_i2c12_clk.common, &spi0_clk.common, + &bus_spi0_clk.common, &spi1_clk.common, + &bus_spi1_clk.common, &spi2_clk.common, + &bus_spi2_clk.common, &spif_clk.common, + &bus_spif_clk.common, &spi3_clk.common, + &bus_spi3_clk.common, &spi4_clk.common, + &bus_spi4_clk.common, &gpadc0_24m_clk.common, + &bus_gpadc0_clk.common, + &bus_ths0_clk.common, &irrx_clk.common, + &bus_irrx_clk.common, &irtx_clk.common, + &bus_irtx_clk.common, + &bus_lradc_clk.common, &sgpio_clk.common, + &bus_sgpio_clk.common, &lpc_clk.common, + &bus_lpc_clk.common, &i2spcm0_clk.common, + &bus_i2spcm0_clk.common, &i2spcm1_clk.common, + &bus_i2spcm1_clk.common, &i2spcm2_clk.common, &i2spcm2_asrc_clk.common, + &bus_i2spcm2_clk.common, &i2spcm3_clk.common, + &bus_i2spcm3_clk.common, &i2spcm4_clk.common, + &bus_i2spcm4_clk.common, &spdif_tx_clk.common, &spdif_rx_clk.common, + &bus_spdif_clk.common, &dmic_clk.common, + &bus_dmic_clk.common, &usb_ohci0_clk.common, + &bus_ohci0_clk.common, + &bus_ehci0_clk.common, + &bus_otg_clk.common, &usb_ohci1_clk.common, + &bus_ohci1_clk.common, + &bus_ehci1_clk.common, &usb01_ref_clk.common, &usb2_u2_ref_clk.common, &usb2_suspend_clk.common,
@@ -1486,25 +1824,41 @@ static struct ccu_common *sun60i_a733_ccu_clks[] = { &serdes_phy_clk.common, &gmac_ptp_clk.common, &gmac0_phy_clk.common, + &bus_gmac0_clk.common, &gmac1_phy_clk.common, + &bus_gmac1_clk.common, &tcon_lcd0_clk.common, + &bus_tcon_lcd0_clk.common, &tcon_lcd1_clk.common, + &bus_tcon_lcd1_clk.common, &tcon_lcd2_clk.common, + &bus_tcon_lcd2_clk.common, &dsi0_clk.common, + &bus_dsi0_clk.common, &dsi1_clk.common, + &bus_dsi1_clk.common, &combphy0_clk.common, &combphy1_clk.common, + &bus_tcon_tv0_clk.common, + &bus_tcon_tv1_clk.common, &edp_tv_clk.common, + &bus_edp_tv_clk.common, &hdmi_cec_32k_clk.common, &hdmi_cec_clk.common, &hdmi_tv_clk.common, + &bus_hdmi_tv_clk.common, &hdmi_sfr_clk.common, &hdcp_esm_clk.common, + &bus_dpss_top0_clk.common, + &bus_dpss_top1_clk.common, &ledc_clk.common, + &bus_ledc_clk.common, + &bus_dsc_clk.common, &csi_master0_clk.common, &csi_master1_clk.common, &csi_master2_clk.common, &csi_clk.common, + &bus_csi_clk.common, &isp_clk.common, &res_dcap_24m_clk.common, &apb2jtag_clk.common,
@@ -1570,7 +1924,60 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = { [CLK_APB1] = &apb1_clk.common.hw, [CLK_APB_UART] = &apb_uart_clk.common.hw, [CLK_TRACE] = &trace_clk.common.hw, + [CLK_BUS_ITS_PCIE0_ACLK] = &bus_its_pcie0_aclk_clk.common.hw, [CLK_MBUS] = &mbus_clk.common.hw, + [CLK_MBUS_IOMMU0_SYS] = &mbus_iommu0_sys_clk.common.hw, + [CLK_APB_IOMMU0_SYS] = &apb_iommu0_sys_clk.common.hw, + [CLK_AHB_IOMMU0_SYS] = &ahb_iommu0_sys_clk.common.hw, + [CLK_BUS_MSI_LITE0] = &bus_msi_lite0_clk.common.hw, + [CLK_BUS_MSI_LITE1] = &bus_msi_lite1_clk.common.hw, + [CLK_BUS_MSI_LITE2] = &bus_msi_lite2_clk.common.hw, + [CLK_MBUS_IOMMU1_SYS] = &mbus_iommu1_sys_clk.common.hw, + [CLK_APB_IOMMU1_SYS] = &apb_iommu1_sys_clk.common.hw, + [CLK_AHB_IOMMU1_SYS] = &ahb_iommu1_sys_clk.common.hw, + [CLK_AHB_VE_DEC] = &ahb_ve_dec_clk.common.hw, + [CLK_AHB_VE_ENC] = &ahb_ve_enc_clk.common.hw, + [CLK_AHB_VID_IN] = &ahb_vid_in_clk.common.hw, + [CLK_AHB_VID_COUT0] = &ahb_vid_cout0_clk.common.hw, + [CLK_AHB_VID_COUT1] = &ahb_vid_cout1_clk.common.hw, + [CLK_AHB_DE] = &ahb_de_clk.common.hw, + [CLK_AHB_NPU] = &ahb_npu_clk.common.hw, + [CLK_AHB_GPU0] = &ahb_gpu0_clk.common.hw, + [CLK_AHB_SERDES] = &ahb_serdes_clk.common.hw, + [CLK_AHB_USB_SYS] = &ahb_usb_sys_clk.common.hw, + [CLK_AHB_MSI_LITE0] = &ahb_msi_lite0_clk.common.hw, + [CLK_AHB_STORE] = &ahb_store_clk.common.hw, + [CLK_AHB_CPUS] = &ahb_cpus_clk.common.hw, + [CLK_MBUS_IOMMU0] = &mbus_iommu0_clk.common.hw, + [CLK_MBUS_IOMMU1] = &mbus_iommu1_clk.common.hw, + [CLK_MBUS_DESYS] = &mbus_desys_clk.common.hw, + [CLK_MBUS_VE_ENC0_GATE] = &mbus_ve_enc0_gate_clk.common.hw, + [CLK_MBUS_VE_DEC0_GATE] = &mbus_ve_dec0_gate_clk.common.hw, + [CLK_MBUS_GPU0] = &mbus_gpu0_clk.common.hw, + [CLK_MBUS_NPU] = &mbus_npu_clk.common.hw, + [CLK_MBUS_VID_IN] = &mbus_vid_in_clk.common.hw, + [CLK_MBUS_SERDES] = &mbus_serdes_clk.common.hw, + [CLK_MBUS_MSI_LITE0] = &mbus_msi_lite0_clk.common.hw, + [CLK_MBUS_STORE] = &mbus_store_clk.common.hw, + [CLK_MBUS_MSI_LITE2] = &mbus_msi_lite2_clk.common.hw, + [CLK_MBUS_DMA0] = &mbus_dma0_clk.common.hw, + [CLK_MBUS_VE_ENC0] = &mbus_ve_enc0_clk.common.hw, + [CLK_MBUS_CE] = &mbus_ce_clk.common.hw, + [CLK_MBUS_DMA1] = &mbus_dma1_clk.common.hw, + [CLK_MBUS_NAND] = &mbus_nand_clk.common.hw, + [CLK_MBUS_CSI] = &mbus_csi_clk.common.hw, + [CLK_MBUS_ISP] = &mbus_isp_clk.common.hw, + [CLK_MBUS_GMAC0] = &mbus_gmac0_clk.common.hw, + [CLK_MBUS_GMAC1] = &mbus_gmac1_clk.common.hw, + [CLK_MBUS_VE_DEC0] = &mbus_ve_dec0_clk.common.hw, + [CLK_BUS_DMA0] = &bus_dma0_clk.common.hw, + [CLK_BUS_DMA1] = &bus_dma1_clk.common.hw, + [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw, + [CLK_BUS_MSGBOX0] = &bus_msgbox0_clk.common.hw, + [CLK_BUS_PWM0] = &bus_pwm0_clk.common.hw, + [CLK_BUS_PWM1] = &bus_pwm1_clk.common.hw, + [CLK_BUS_DBG] = &bus_dbg_clk.common.hw, + [CLK_BUS_SYSDAP] = &bus_sysdap_clk.common.hw, [CLK_TIMER0] = &timer0_clk.common.hw, [CLK_TIMER1] = &timer1_clk.common.hw, [CLK_TIMER2] = &timer2_clk.common.hw,
@@ -1581,48 +1988,111 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = { [CLK_TIMER7] = &timer7_clk.common.hw, [CLK_TIMER8] = &timer8_clk.common.hw, [CLK_TIMER9] = &timer9_clk.common.hw, + [CLK_BUS_TIMER] = &bus_timer_clk.common.hw, [CLK_AVS] = &avs_clk.common.hw, [CLK_DE0] = &de0_clk.common.hw, + [CLK_BUS_DE0] = &bus_de0_clk.common.hw, [CLK_DI] = &di_clk.common.hw, + [CLK_BUS_DI] = &bus_di_clk.common.hw, [CLK_G2D] = &g2d_clk.common.hw, + [CLK_BUS_G2D] = &bus_g2d_clk.common.hw, [CLK_EINK] = &eink_clk.common.hw, [CLK_EINK_PANEL] = &eink_panel_clk.common.hw, + [CLK_BUS_EINK] = &bus_eink_clk.common.hw, [CLK_VE_ENC0] = &ve_enc0_clk.common.hw, [CLK_VE_DEC0] = &ve_dec0_clk.common.hw, + [CLK_BUS_VE_ENC0] = &bus_ve_enc0_clk.common.hw, + [CLK_BUS_VE_DEC0] = &bus_ve_dec0_clk.common.hw, [CLK_CE] = &ce_clk.common.hw, + [CLK_BUS_CE] = &bus_ce_clk.common.hw, + [CLK_BUS_CE_SYS] = &bus_ce_sys_clk.common.hw, [CLK_NPU] = &npu_clk.common.hw, + [CLK_BUS_NPU] = &bus_npu_clk.common.hw, [CLK_GPU0] = &gpu0_clk.common.hw, + [CLK_BUS_GPU0] = &bus_gpu0_clk.common.hw, [CLK_DRAM0] = &dram0_clk.common.hw, + [CLK_BUS_DRAM0] = &bus_dram0_clk.common.hw, [CLK_NAND0_CLK0] = &nand0_clk0_clk.common.hw, [CLK_NAND0_CLK1] = &nand0_clk1_clk.common.hw, + [CLK_BUS_NAND0] = &bus_nand0_clk.common.hw, [CLK_MMC0] = &mmc0_clk.common.hw, + [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw, [CLK_MMC1] = &mmc1_clk.common.hw, + [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw, [CLK_MMC2] = &mmc2_clk.common.hw, + [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw, [CLK_MMC3] = &mmc3_clk.common.hw, + [CLK_BUS_MMC3] = &bus_mmc3_clk.common.hw, [CLK_UFS_AXI] = &ufs_axi_clk.common.hw, [CLK_UFS_CFG] = &ufs_cfg_clk.common.hw, + [CLK_BUS_UFS] = &bus_ufs_clk.common.hw, + [CLK_BUS_UART0] = &bus_uart0_clk.common.hw, + [CLK_BUS_UART1] = &bus_uart1_clk.common.hw, + [CLK_BUS_UART2] = &bus_uart2_clk.common.hw, + [CLK_BUS_UART3] = &bus_uart3_clk.common.hw, + [CLK_BUS_UART4] = &bus_uart4_clk.common.hw, + [CLK_BUS_UART5] = &bus_uart5_clk.common.hw, + [CLK_BUS_UART6] = &bus_uart6_clk.common.hw, + [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw, + [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw, + [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw, + [CLK_BUS_I2C3] = &bus_i2c3_clk.common.hw, + [CLK_BUS_I2C4] = &bus_i2c4_clk.common.hw, + [CLK_BUS_I2C5] = &bus_i2c5_clk.common.hw, + [CLK_BUS_I2C6] = &bus_i2c6_clk.common.hw, + [CLK_BUS_I2C7] = &bus_i2c7_clk.common.hw, + [CLK_BUS_I2C8] = &bus_i2c8_clk.common.hw, + [CLK_BUS_I2C9] = &bus_i2c9_clk.common.hw, + [CLK_BUS_I2C10] = &bus_i2c10_clk.common.hw, + [CLK_BUS_I2C11] = &bus_i2c11_clk.common.hw, + [CLK_BUS_I2C12] = &bus_i2c12_clk.common.hw, [CLK_SPI0] = &spi0_clk.common.hw, + [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw, [CLK_SPI1] = &spi1_clk.common.hw, + [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw, [CLK_SPI2] = &spi2_clk.common.hw, + [CLK_BUS_SPI2] = &bus_spi2_clk.common.hw, [CLK_SPIF] = &spif_clk.common.hw, + [CLK_BUS_SPIF] = &bus_spif_clk.common.hw, [CLK_SPI3] = &spi3_clk.common.hw, + [CLK_BUS_SPI3] = &bus_spi3_clk.common.hw, [CLK_SPI4] = &spi4_clk.common.hw, + [CLK_BUS_SPI4] = &bus_spi4_clk.common.hw, [CLK_GPADC0_24M] = &gpadc0_24m_clk.common.hw, + [CLK_BUS_GPADC0] = &bus_gpadc0_clk.common.hw, + [CLK_BUS_THS0] = &bus_ths0_clk.common.hw, [CLK_IRRX] = &irrx_clk.common.hw, + [CLK_BUS_IRRX] = &bus_irrx_clk.common.hw, [CLK_IRTX] = &irtx_clk.common.hw, + [CLK_BUS_IRTX] = &bus_irtx_clk.common.hw, + [CLK_BUS_LRADC] = &bus_lradc_clk.common.hw, [CLK_SGPIO] = &sgpio_clk.common.hw, + [CLK_BUS_SGPIO] = &bus_sgpio_clk.common.hw, [CLK_LPC] = &lpc_clk.common.hw, + [CLK_BUS_LPC] = &bus_lpc_clk.common.hw, [CLK_I2SPCM0] = &i2spcm0_clk.common.hw, + [CLK_BUS_I2SPCM0] = &bus_i2spcm0_clk.common.hw, [CLK_I2SPCM1] = &i2spcm1_clk.common.hw, + [CLK_BUS_I2SPCM1] = &bus_i2spcm1_clk.common.hw, [CLK_I2SPCM2] = &i2spcm2_clk.common.hw, [CLK_I2SPCM2_ASRC] = &i2spcm2_asrc_clk.common.hw, + [CLK_BUS_I2SPCM2] = &bus_i2spcm2_clk.common.hw, [CLK_I2SPCM3] = &i2spcm3_clk.common.hw, + [CLK_BUS_I2SPCM3] = &bus_i2spcm3_clk.common.hw, [CLK_I2SPCM4] = &i2spcm4_clk.common.hw, + [CLK_BUS_I2SPCM4] = &bus_i2spcm4_clk.common.hw, [CLK_SPDIF_TX] = &spdif_tx_clk.common.hw, [CLK_SPDIF_RX] = &spdif_rx_clk.common.hw, + [CLK_BUS_SPDIF] = &bus_spdif_clk.common.hw, [CLK_DMIC] = &dmic_clk.common.hw, + [CLK_BUS_DMIC] = &bus_dmic_clk.common.hw, [CLK_USB_OHCI0] = &usb_ohci0_clk.common.hw, + [CLK_BUS_OHCI0] = &bus_ohci0_clk.common.hw, + [CLK_BUS_EHCI0] = &bus_ehci0_clk.common.hw, + [CLK_BUS_OTG] = &bus_otg_clk.common.hw, [CLK_USB_OHCI1] = &usb_ohci1_clk.common.hw, + [CLK_BUS_OHCI1] = &bus_ohci1_clk.common.hw, + [CLK_BUS_EHCI1] = &bus_ehci1_clk.common.hw, [CLK_USB01_REF] = &usb01_ref_clk.common.hw, [CLK_USB2_U2_REF] = &usb2_u2_ref_clk.common.hw, [CLK_USB2_SUSPEND] = &usb2_suspend_clk.common.hw,
@@ -1634,25 +2104,41 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = { [CLK_SERDES_PHY] = &serdes_phy_clk.common.hw, [CLK_GMAC_PTP] = &gmac_ptp_clk.common.hw, [CLK_GMAC0_PHY] = &gmac0_phy_clk.common.hw, + [CLK_BUS_GMAC0] = &bus_gmac0_clk.common.hw, [CLK_GMAC1_PHY] = &gmac1_phy_clk.common.hw, + [CLK_BUS_GMAC1] = &bus_gmac1_clk.common.hw, [CLK_TCON_LCD0] = &tcon_lcd0_clk.common.hw, + [CLK_BUS_TCON_LCD0] = &bus_tcon_lcd0_clk.common.hw, [CLK_TCON_LCD1] = &tcon_lcd1_clk.common.hw, + [CLK_BUS_TCON_LCD1] = &bus_tcon_lcd1_clk.common.hw, [CLK_TCON_LCD2] = &tcon_lcd2_clk.common.hw, + [CLK_BUS_TCON_LCD2] = &bus_tcon_lcd2_clk.common.hw, [CLK_DSI0] = &dsi0_clk.common.hw, + [CLK_BUS_DSI0] = &bus_dsi0_clk.common.hw, [CLK_DSI1] = &dsi1_clk.common.hw, + [CLK_BUS_DSI1] = &bus_dsi1_clk.common.hw, [CLK_COMBPHY0] = &combphy0_clk.common.hw, [CLK_COMBPHY1] = &combphy1_clk.common.hw, + [CLK_BUS_TCON_TV0] = &bus_tcon_tv0_clk.common.hw, + [CLK_BUS_TCON_TV1] = &bus_tcon_tv1_clk.common.hw, [CLK_EDP_TV] = &edp_tv_clk.common.hw, + [CLK_BUS_EDP_TV] = &bus_edp_tv_clk.common.hw, [CLK_HDMI_CEC_32K] = &hdmi_cec_32k_clk.common.hw, [CLK_HDMI_CEC] = &hdmi_cec_clk.common.hw, [CLK_HDMI_TV] = &hdmi_tv_clk.common.hw, + [CLK_BUS_HDMI_TV] = &bus_hdmi_tv_clk.common.hw, [CLK_HDMI_SFR] = &hdmi_sfr_clk.common.hw, [CLK_HDCP_ESM] = &hdcp_esm_clk.common.hw, + [CLK_BUS_DPSS_TOP0] = &bus_dpss_top0_clk.common.hw, + [CLK_BUS_DPSS_TOP1] = &bus_dpss_top1_clk.common.hw, [CLK_LEDC] = &ledc_clk.common.hw, + [CLK_BUS_LEDC] = &bus_ledc_clk.common.hw, + [CLK_BUS_DSC] = &bus_dsc_clk.common.hw, [CLK_CSI_MASTER0] = &csi_master0_clk.common.hw, [CLK_CSI_MASTER1] = &csi_master1_clk.common.hw, [CLK_CSI_MASTER2] = &csi_master2_clk.common.hw, [CLK_CSI] = &csi_clk.common.hw, + [CLK_BUS_CSI] = &bus_csi_clk.common.hw, [CLK_ISP] = &isp_clk.common.hw, [CLK_RES_DCAP_24M] = &res_dcap_24m_clk.common.hw, [CLK_APB2JTAG] = &apb2jtag_clk.common.hw,
Signature · 1 line
2.54.0
[email protected]
AI reviewRe: [PATCH v2 7/8] clk: sunxi-ng: a733: Add bus clock gates
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [High] Bus clock gates for multiple peripherals are incorrectly parented to the 24MHz external oscillator…
Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Bus clock gates for multiple peripherals are incorrectly parented to the 24MHz external oscillator (hosc) instead of their actual AHB/APB buses.
- [Low] Typographical error in the string names for the IOMMU1 system clocks, using an underscore instead of a hyphen.
--
--- Patch [7]: [PATCH v2 7/8] clk: sunxi-ng: a733: Add bus clock gates --- commit 92eebd6b3ec66a1f50b982f0effa98e2238c2a4d
Author: Junhui Liu <[email protected]>
clk: sunxi-ng: a733: Add bus clock gates
This commit adds the bus clock gates that control access to the devices' register interface on the Allwinner A733 SoC, including UARTs, SPI, I2C, and multimedia engines. It also marks ahb-store and mbus-store as critical to ensure boot/storage devices remain accessible.
drivers/clk/sunxi-ng/ccu-sun60i-a733.c static SUNXI_CCU_M_DATA_WITH_MUX_GATE(trace_clk, "trace", trace_parents, 0x540, · line 458
Quoted 10 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +2
-0@@ -448,6 +454,8 @@ static SUNXI_CCU_M_DATA_WITH_MUX_GATE(trace_clk, "trace", trace_parents, 0x540,BIT (31 ),/* gate */ 0); +static SUNXI_CCU_GATE_DATA(bus_its_pcie0_aclk_clk, "bus-its-pcie0-aclk", hosc, 0x574, BIT(1), 0); +
[Severity: High]
Are these bus clock gates correctly parented to hosc instead of their respective AHB or APB buses?
If the Common Clock Framework is misinformed about the hardware topology, it might dynamically disable the actual underlying bus clock if it believes it has no active children. Could this cause a synchronous external abort (bus hang) when drivers try to access the registers of these peripherals?
This same parenting to hosc also appears in several other bus gates added later in this patch, such as bus_msi_lite0_clk, bus_npu_clk, bus_ufs_clk, and the bus_i2spcm series of clocks.
[ ... ]
drivers/clk/sunxi-ng/ccu-sun60i-a733.c static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x58 · line 486
Quoted 3 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +3
-0+static SUNXI_CCU_GATE_HWS(mbus_iommu1_sys_clk, "mbus-iommu1-sys", mbus_hws, 0x5b4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(apb_iommu1_sys_clk, "apb_iommu1-sys", apb0_hws, 0x5b4, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(ahb_iommu1_sys_clk, "ahb_iommu1-sys", ahb_hws, 0x5b4, BIT(2), 0);
[Severity: Low]
This isn't a bug, but there's a typo in the string names for the iommu1 system clocks.
They use an underscore instead of a hyphen ("apb_iommu1-sys" instead of "apb-iommu1-sys"). Does this break the naming convention established by the iommu0 clocks just above it?
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=7
Re: [PATCH v2 7/8] clk: sunxi-ng: a733: Add bus clock gates
In reply to Junhui LiuOn Sat Jul 11, 2026 at 4:10 PM CST, Junhui Liu wrote:
[...]
drivers/clk/sunxi-ng/ccu-sun60i-a733.c static SUNXI_CCU_MP_DATA_WITH_MUX_GATE_FEAT(mbus_clk, "mbus", mbus_parents, 0x58 · line 486
Quoted 4 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +4
-0+ +static SUNXI_CCU_GATE_HWS(mbus_iommu1_sys_clk, "mbus-iommu1-sys", mbus_hws, 0x5b4, BIT(0), 0); +static SUNXI_CCU_GATE_HWS(apb_iommu1_sys_clk, "apb_iommu1-sys", apb0_hws, 0x5b4, BIT(1), 0); +static SUNXI_CCU_GATE_HWS(ahb_iommu1_sys_clk, "ahb_iommu1-sys", ahb_hws, 0x5b4, BIT(2), 0);
The clock names here should be "apb-iommu1-sys" and "ahb-iommu1-sys". I will update them in next version.
Signature · 2 lines
Best regards, Junhui Liu
PATCH v2 8/8 clk: sunxi-ng: a733: Add reset lines
In reply to Junhui LiuAdd the reset lines for the Allwinner A733 SoC. These reset control bits are integrated into the Bus Gate Reset (BGR) registers, typically sharing the same register address with their corresponding bus clock gates. Integrate them into the main CCU driver using the existing sunxi-ng ccu_reset framework, allowing the CCU to also function as a reset controller for the SoC.
Tested-by Jerome Brunet <[email protected]>
Signed-off-by Junhui Liu <[email protected]>
--- drivers/clk/sunxi-ng/ccu-sun60i-a733.c | 126 +++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+)
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +126 -0
@@ -17,6 +17,7 @@#include "../clk.h" #include "ccu_common.h" +#include "ccu_reset.h" #include "ccu_div.h" #include "ccu_gate.h"
@@ -2156,11 +2157,136 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = { .num = CLK_FANOUT3 + 1, }; +static struct ccu_reset_map sun60i_a733_ccu_resets[] = { + [RST_BUS_ITS_PCIE0 ] = {0x574 ,BIT (16 ) }, + [RST_BUS_IOMMU0_SYS ] = {0x58c ,BIT (16 ) }, + [RST_BUS_MSI_LITE0_AHB ] = {0x594 ,BIT (16 ) }, + [RST_BUS_MSI_LITE0_MBUS ] = {0x594 ,BIT (17 ) }, + [RST_BUS_MSI_LITE1_AHB ] = {0x59c ,BIT (16 ) }, + [RST_BUS_MSI_LITE1_MBUS ] = {0x59c ,BIT (17 ) }, + [RST_BUS_MSI_LITE2_AHB ] = {0x5a4 ,BIT (16 ) }, + [RST_BUS_MSI_LITE2_MBUS ] = {0x5a4 ,BIT (17 ) }, + [RST_BUS_IOMMU1_SYS ] = {0x5b4 ,BIT (16 ) }, + [RST_BUS_DMA0 ] = {0x704 ,BIT (16 ) }, + [RST_BUS_DMA1 ] = {0x70c ,BIT (16 ) }, + [RST_BUS_SPINLOCK ] = {0x724 ,BIT (16 ) }, + [RST_BUS_MSGBOX ] = {0x744 ,BIT (16 ) }, + [RST_BUS_PWM0 ] = {0x784 ,BIT (16 ) }, + [RST_BUS_PWM1 ] = {0x78c ,BIT (16 ) }, + [RST_BUS_DBG ] = {0x7a4 ,BIT (16 ) }, + [RST_BUS_SYSDAP ] = {0x7ac ,BIT (16 ) }, + [RST_BUS_TIMER0 ] = {0x850 ,BIT (16 ) }, + [RST_BUS_DE0 ] = {0xa04 ,BIT (16 ) }, + [RST_BUS_DI ] = {0xa24 ,BIT (16 ) }, + [RST_BUS_G2D ] = {0xa44 ,BIT (16 ) }, + [RST_BUS_EINK ] = {0xa6c ,BIT (16 ) }, + [RST_BUS_DE_SYS ] = {0xa74 ,BIT (16 ) }, + [RST_BUS_VE_ENC0 ] = {0xa8c ,BIT (16 ) }, + [RST_BUS_VE_DEC0 ] = {0xa8c ,BIT (18 ) }, + [RST_BUS_CE ] = {0xac4 ,BIT (16 ) }, + [RST_BUS_CE_SYS ] = {0xac4 ,BIT (17 ) }, + [RST_BUS_NPU_CORE ] = {0xb04 ,BIT (16 ) }, + [RST_BUS_NPU_AXI ] = {0xb04 ,BIT (17 ) }, + [RST_BUS_NPU_AHB ] = {0xb04 ,BIT (18 ) }, + [RST_BUS_NPU_SRAM ] = {0xb04 ,BIT (19 ) }, + [RST_BUS_GPU0 ] = {0xb24 ,BIT (16 ) }, + [RST_BUS_DRAM0 ] = {0xc0c ,BIT (16 ) }, + [RST_BUS_NAND0 ] = {0xc8c ,BIT (16 ) }, + [RST_BUS_MMC0 ] = {0xd0c ,BIT (16 ) }, + [RST_BUS_MMC1 ] = {0xd1c ,BIT (16 ) }, + [RST_BUS_MMC2 ] = {0xd2c ,BIT (16 ) }, + [RST_BUS_MMC3 ] = {0xd3c ,BIT (16 ) }, + [RST_BUS_UFS_AHB ] = {0xd8c ,BIT (16 ) }, + [RST_BUS_UFS_AXI ] = {0xd8c ,BIT (17 ) }, + [RST_BUS_UFS_PHY ] = {0xd8c ,BIT (18 ) }, + [RST_BUS_UFS_CORE ] = {0xd8c ,BIT (19 ) }, + [RST_BUS_UART0 ] = {0xe00 ,BIT (16 ) }, + [RST_BUS_UART1 ] = {0xe04 ,BIT (16 ) }, + [RST_BUS_UART2 ] = {0xe08 ,BIT (16 ) }, + [RST_BUS_UART3 ] = {0xe0c ,BIT (16 ) }, + [RST_BUS_UART4 ] = {0xe10 ,BIT (16 ) }, + [RST_BUS_UART5 ] = {0xe14 ,BIT (16 ) }, + [RST_BUS_UART6 ] = {0xe18 ,BIT (16 ) }, + [RST_BUS_I2C0 ] = {0xe80 ,BIT (16 ) }, + [RST_BUS_I2C1 ] = {0xe84 ,BIT (16 ) }, + [RST_BUS_I2C2 ] = {0xe88 ,BIT (16 ) }, + [RST_BUS_I2C3 ] = {0xe8c ,BIT (16 ) }, + [RST_BUS_I2C4 ] = {0xe90 ,BIT (16 ) }, + [RST_BUS_I2C5 ] = {0xe94 ,BIT (16 ) }, + [RST_BUS_I2C6 ] = {0xe98 ,BIT (16 ) }, + [RST_BUS_I2C7 ] = {0xe9c ,BIT (16 ) }, + [RST_BUS_I2C8 ] = {0xea0 ,BIT (16 ) }, + [RST_BUS_I2C9 ] = {0xea4 ,BIT (16 ) }, + [RST_BUS_I2C10 ] = {0xea8 ,BIT (16 ) }, + [RST_BUS_I2C11 ] = {0xeac ,BIT (16 ) }, + [RST_BUS_I2C12 ] = {0xeb0 ,BIT (16 ) }, + [RST_BUS_SPI0 ] = {0xf04 ,BIT (16 ) }, + [RST_BUS_SPI1 ] = {0xf0c ,BIT (16 ) }, + [RST_BUS_SPI2 ] = {0xf14 ,BIT (16 ) }, + [RST_BUS_SPIF ] = {0xf1c ,BIT (16 ) }, + [RST_BUS_SPI3 ] = {0xf24 ,BIT (16 ) }, + [RST_BUS_SPI4 ] = {0xf2c ,BIT (16 ) },/* From the vendor kernel. */ + [RST_BUS_GPADC0 ] = {0xfc4 ,BIT (16 ) }, + [RST_BUS_THS0 ] = {0xfe4 ,BIT (16 ) }, + [RST_BUS_IRRX ] = {0x1004 ,BIT (16 ) }, + [RST_BUS_IRTX ] = {0x100c ,BIT (16 ) }, + [RST_BUS_LRADC ] = {0x1024 ,BIT (16 ) }, + [RST_BUS_SGPIO ] = {0x1064 ,BIT (16 ) },/* From the vendor kernel. */ + [RST_BUS_LPC ] = {0x1084 ,BIT (16 ) },/* From the vendor kernel. */ + [RST_BUS_I2SPCM0 ] = {0x120c ,BIT (16 ) }, + [RST_BUS_I2SPCM1 ] = {0x121c ,BIT (16 ) }, + [RST_BUS_I2SPCM2 ] = {0x122c ,BIT (16 ) }, + [RST_BUS_I2SPCM3 ] = {0x123c ,BIT (16 ) }, + [RST_BUS_I2SPCM4 ] = {0x124c ,BIT (16 ) }, + [RST_BUS_SPDIF ] = {0x128c ,BIT (16 ) }, + [RST_BUS_DMIC ] = {0x12cc ,BIT (16 ) }, + [RST_USB_PHY0 ] = {0x1300 ,BIT (30 ) }, + [RST_BUS_OHCI0 ] = {0x1304 ,BIT (16 ) }, + [RST_BUS_EHCI0 ] = {0x1304 ,BIT (20 ) }, + [RST_BUS_OTG ] = {0x1304 ,BIT (24 ) }, + [RST_USB_PHY1 ] = {0x1308 ,BIT (30 ) }, + [RST_BUS_OHCI1 ] = {0x130c ,BIT (16 ) }, + [RST_BUS_EHCI1 ] = {0x130c ,BIT (20 ) }, + [RST_BUS_USB2 ] = {0x135c ,BIT (16 ) }, + [RST_BUS_PCIE_PWRUP ] = {0x138c ,BIT (16 ) }, + [RST_BUS_PCIE ] = {0x138c ,BIT (17 ) }, + [RST_BUS_SERDES ] = {0x13c4 ,BIT (16 ) }, + [RST_BUS_GMAC0 ] = {0x141c ,BIT (16 ) }, + [RST_BUS_GMAC0_AXI ] = {0x141c ,BIT (17 ) }, + [RST_BUS_GMAC1 ] = {0x142c ,BIT (16 ) },/* From the vendor kernel. */ + [RST_BUS_GMAC1_AXI ] = {0x142c ,BIT (17 ) },/* From the vendor kernel. */ + [RST_BUS_TCON_LCD0 ] = {0x1504 ,BIT (16 ) }, + [RST_BUS_TCON_LCD1 ] = {0x150c ,BIT (16 ) }, + [RST_BUS_TCON_LCD2 ] = {0x1514 ,BIT (16 ) },/* From the vendor kernel. */ + [RST_BUS_LVDS0 ] = {0x1544 ,BIT (16 ) }, + [RST_BUS_LVDS1 ] = {0x154c ,BIT (16 ) }, + [RST_BUS_DSI0 ] = {0x1584 ,BIT (16 ) }, + [RST_BUS_DSI1 ] = {0x158c ,BIT (16 ) }, + [RST_BUS_TCON_TV0 ] = {0x1604 ,BIT (16 ) }, + [RST_BUS_TCON_TV1 ] = {0x160c ,BIT (16 ) }, + [RST_BUS_EDP ] = {0x164c ,BIT (16 ) }, + [RST_BUS_HDMI_MAIN ] = {0x168c ,BIT (16 ) }, + [RST_BUS_HDMI_SUB ] = {0x168c ,BIT (17 ) }, + [RST_BUS_HDMI_HDCP ] = {0x168c ,BIT (18 ) }, + [RST_BUS_DPSS_TOP0 ] = {0x16c4 ,BIT (16 ) }, + [RST_BUS_DPSS_TOP1 ] = {0x16cc ,BIT (16 ) }, + [RST_BUS_VIDEO_OUT0 ] = {0x16e4 ,BIT (16 ) }, + [RST_BUS_VIDEO_OUT1 ] = {0x16ec ,BIT (16 ) }, + [RST_BUS_LEDC ] = {0x1704 ,BIT (16 ) }, + [RST_BUS_DSC ] = {0x1744 ,BIT (16 ) }, + [RST_BUS_CSI ] = {0x1844 ,BIT (16 ) }, + [RST_BUS_VIDEO_IN ] = {0x1884 ,BIT (16 ) }, + [RST_BUS_APB2JTAG ] = {0x1c04 ,BIT (16 ) }, +}; +static const struct sunxi_ccu_desc sun60i_a733_ccu_desc = { .ccu_clks = sun60i_a733_ccu_clks, .num_ccu_clks =ARRAY_SIZE (sun60i_a733_ccu_clks), .hw_clks = &sun60i_a733_hw_clks, + + .resets = sun60i_a733_ccu_resets, + .num_resets =ARRAY_SIZE (sun60i_a733_ccu_resets), };static const u32 pll_regs[] = {
Signature · 1 line
2.54.0
[email protected]
AI reviewRe: [PATCH v2 8/8] clk: sunxi-ng: a733: Add reset lines
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] The `sun60i_a733_ccu_resets` array is missing the `const` qualifier. --
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The sun60i_a733_ccu_resets array is missing the const qualifier. --
--- Patch [8]: [PATCH v2 8/8] clk: sunxi-ng: a733: Add reset lines --- commit 4ea86ec36599a9ad729bf576a38c2f6cad725b56
Author: Junhui Liu <[email protected]>
clk: sunxi-ng: a733: Add reset lines
This patch adds the reset lines for the Allwinner A733 SoC. The reset control bits are integrated into the main CCU driver using the sunxi-ng ccu_reset framework, enabling the CCU to function as a reset controller.
Quoted 4 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +0
-0
[ ... ]
drivers/clk/sunxi-ng/ccu-sun60i-a733.c static struct clk_hw_onecell_data sun60i_a733_hw_clks = { · line 2160
Quoted 5 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +1
-0@@ -2156,11 +2157,136 @@ static struct clk_hw_onecell_data sun60i_a733_hw_clks = { .num = CLK_FANOUT3 + 1, }; +static struct ccu_reset_map sun60i_a733_ccu_resets[] = {
[Severity: Low]
Is it possible to add the const qualifier to the sun60i_a733_ccu_resets array?
Without the const qualifier, this reset map array is placed in the mutable .data section instead of the read-only .rodata section. Because it is later assigned to the .resets member of sunxi_ccu_desc which expects a const pointer, adding const here would save mutable memory and slightly improve security hardening.
Quoted 2 lines
drivers/clk/sunxi-ng/ccu-sun60i-a733.c +2
-0+ [RST_BUS_ITS_PCIE0] = { 0x574, BIT(16) }, + [RST_BUS_IOMMU0_SYS] = { 0x58c, BIT(16) },
[ ... ]
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=8