pwm: Add Nuvoton MA35D1 PWM controller support
Subsystems (3)
v5 cover pwm: Add Nuvoton MA35D1 PWM controller support
From: Chi-Wen Weng <[email protected]>
This series adds the device tree binding and PWM framework driver for the Nuvoton MA35D1 EPWM controller.
The MA35D1 EPWM controller provides 6 PWM channels. The hardware supports up, down and up-down counter types, auto-reload and one-shot modes, and independent and complementary output modes.
The initial driver supports independent output mode only and configures a channel for up-counting and auto-reload operation when an explicit .apply() request is made. The waveform generator drives the output high at the zero point and low at the compare-up point.
In up-counting mode, the counter counts from 0 to PERIOD inclusive. With the selected waveform actions, CMPDAT = 0 generates a 0% duty cycle and CMPDAT > PERIOD generates a 100% duty cycle. The driver keeps PERIOD one count below the 16-bit field maximum so that CMPDAT can be programmed greater than PERIOD for the full-duty case.
PERIOD and CMPDAT updates are buffered by the hardware and take effect at the end of the current period because the driver selects period loading mode by clearing IMMLDENn,WINLDENn and CTRLDn. When a PWM is disabled, POENn and CNTENn are cleared, and the output pin is put into tri-state.
The driver does not modify the PWM controller during probe. This preserves PWM outputs that may have been configured and enabled by firmware, such as a display backlight. The counter and waveform configuration is changed only for the channel passed to .apply().
Since the independent/complementary mode selection is shared by each pair of channels, the driver refuses to change an active complementary pair to independent mode when the paired channel is already enabled.
Changes in v5:
- Remove the probe-time controller initialization to preserve PWM outputs configured by firmware.
- Configure the counter and waveform settings only for the channel passed to .apply().
- Keep the disable path limited to clearing POENn and CNTENn.
- Check for an active paired channel before changing a complementary pair to independent mode.
- Return -EBUSY when changing the shared output mode would disturb an active paired channel.
- Document that the initial driver supports independent output mode only.
- Remove the unnecessary <linux/mod_devicetable.h> include.
- Simplify the WGCTL action field handling and remove the associated static inline mask helpers.
- Rename the PWM field and period limits to clarify their different semantics.
- Configure period loading mode explicitly in .apply().
- Preserve the pair-shared clock prescaler and account for it in period and duty-cycle calculations.
- Limit the period to 0xffff counter cycles while reserving CMPDAT = 0xffff for the full-duty case.
Changes in v4:
- Add a Limitations section to describe the hardware capabilities and driver limitations.
- Add a link to the MA35D1 reference manual.
- Replace register address macros containing the base pointer with register offset macros.
- Add readl/writel/rmw helper functions.
- Rename TOTAL_CHANNELS to NUM_CHANNELS.
- Use unsigned long for the cached clock rate.
- Use devm_clk_rate_exclusive_get().
- Configure polarity before enabling the counter and output.
- Add controller initialization for up-counting, auto-reload and independent output mode.
- Configure the waveform generator for zero-point-high and compare-up-low output.
- Fix the period conversion because the hardware period is PERIOD + 1 cycles.
- Limit the maximum PERIOD value to 0xfffe so that CMPDAT = 0xffff can be used to generate 100% duty cycle.
- Use CNTEN and POEN bits to report the enabled state in .get_state().
- Disable the PWM by clearing POENn and CNTENn.
- Fix error message capitalization and trailing newlines.
- Fix coding style issues reported by review/checkpatch-style tools.
Changes in v3:
- Update nuvoton,ma35d1-pwm.yaml
- Add maintainers entry
- Increase "#pwm-cells" to 3
- Update ma35d1 pwm driver
- Make include header and macros definitions organized alphabetically
- Rename macros REG_PWM_XXXX to MA35D1_REG_PWM_XXXX
- Add macros for register address
v2 resend:
- Remove wrong 'Reviewed-by' tags.
Changes in v2:
- Update nuvoton,ma35d1-pwm.yaml
- Fix 'maxItems' of 'reg' to 1.
- Remove unused label
- Update ma35d1 pwm driver
- Remove MODULE_ALIAS()
- Add chip->atomic = true
Chi-Wen Weng (2):
dt-bindings: pwm: Add Nuvoton MA35D1 PWM controller
pwm: Add Nuvoton MA35D1 PWM controller support
.../bindings/pwm/nuvoton,ma35d1-pwm.yaml | 45 +++ drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ma35d1.c | 380 ++++++++++++++++++ 4 files changed, 436 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/nuvoton,ma35d1-pwm.yaml create mode 100644 drivers/pwm/pwm-ma35d1.c
Signature · 1 line
2.25.1
PATCH v5 1/2 dt-bindings: pwm: Add Nuvoton MA35D1 PWM controller
From: Chi-Wen Weng <[email protected]>
Add device tree binding for the Nuvoton MA35D1 PWM controller.
The MA35D1 PWM controller provides 6 PWM channels and uses one register region and one functional clock. The binding uses the standard PWM binding with three PWM cells.
--- .../bindings/pwm/nuvoton,ma35d1-pwm.yaml | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/nuvoton,ma35d1-pwm.yaml
Documentation/devicetree/bindings/pwm/nuvoton,ma35d1-pwm.yaml new file +45 -0
@@ -0,0 +1,45 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/nuvoton,ma35d1-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 PWM controller + +maintainers: + - Chi-Wen Weng <[email protected]> + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - nuvoton,ma35d1-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/nuvoton,ma35d1-clk.h> + + pwm@40580000 { + compatible = "nuvoton,ma35d1-pwm"; + reg = <0x40580000 0x400>; + clocks = <&clk EPWM0_GATE>; + #pwm-cells = <3>; + };
Signature · 1 line
2.25.1
PATCH v5 2/2 pwm: Add Nuvoton MA35D1 PWM controller support
In reply to Chi-Wen WengFrom: Chi-Wen Weng <[email protected]>
Add a PWM framework driver for the Nuvoton MA35D1 EPWM controller.
The controller provides 6 PWM channels and supports up, down and up-down counter types, auto-reload and one-shot counter modes, and independent and complementary output modes.
The initial driver supports up-counting, auto-reload and independent output modes. It uses period loading mode and configures the waveform generator to drive the output high at the zero point and low at the compare-up point.
In up-counting mode, the counter counts from 0 to PERIOD inclusive. With the selected waveform actions, CMPDAT = 0 generates a 0% duty cycle and CMPDAT > PERIOD generates a 100% duty cycle. Limit the period to 0xffff counter cycles so that PERIOD is at most 0xfffe and CMPDAT = 0xffff remains available for the full-duty case.
The clock prescaler is shared by each pair of PWM channels. Preserve its existing value and account for CLKPSC + 1 when calculating and reporting the period and duty cycle.
Do not modify the controller during probe, preserving PWM outputs that may already have been configured by firmware. Configure only the requested channel from the apply callback. Refuse to change an active complementary pair to independent mode when doing so would disturb the paired output.
When disabling a channel, clear its output-enable and counter-enable bits. The output pin is then placed in tri-state by the hardware.
--- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ma35d1.c | 380 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 391 insertions(+) create mode 100644 drivers/pwm/pwm-ma35d1.c
drivers/pwm/Kconfig +10 -0
@@ -463,6 +463,16 @@ config PWM_LPSS_PLATFORM To compile this driver as a module, choose M here: the module will be called pwm-lpss-platform. +config PWM_MA35D1 + tristate "Nuvoton MA35D1 PWM support" + depends on ARCH_MA35 || COMPILE_TEST + help + Generic PWM framework driver for the Nuvoton MA35D1 PWM + controller, which provides 6 PWM outputs. + + To compile this driver as a module, choose M here: the module + will be called pwm-ma35d1. + config PWM_MAX7360 tristate "MAX7360 PWMs" depends on MFD_MAX7360
drivers/pwm/Makefile +1 -0
@@ -40,6 +40,7 @@ obj-$(CONFIG_PWM_LPC32XX) += pwm-lpc32xx.o obj-$(CONFIG_PWM_LPSS) += pwm-lpss.o obj-$(CONFIG_PWM_LPSS_PCI) += pwm-lpss-pci.o obj-$(CONFIG_PWM_LPSS_PLATFORM) += pwm-lpss-platform.o +obj-$(CONFIG_PWM_MA35D1) += pwm-ma35d1.o obj-$(CONFIG_PWM_MAX7360) += pwm-max7360.o obj-$(CONFIG_PWM_MC33XS2410) += pwm-mc33xs2410.o obj-$(CONFIG_PWM_MEDIATEK) += pwm-mediatek.o
drivers/pwm/pwm-ma35d1.c new file +380 -0
380 lines not on this page · raw message
Signature · 1 line
2.25.1
[email protected]
AI reviewThank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] The apply callback returns early when !state->enabled, dropping updates to polarity, period, and…
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The apply callback returns early when !state->enabled, dropping updates to polarity, period, and duty_cycle. --
--- Patch [2]: [PATCH v5 2/2] pwm: Add Nuvoton MA35D1 PWM controller support --- commit cacbb01a99a86c07f6c67c4f1ef4d561c3481e94
Author: Chi-Wen Weng <[email protected]>
pwm: Add Nuvoton MA35D1 PWM controller support
Adds a PWM framework driver for the Nuvoton MA35D1 EPWM controller. The driver supports 6 PWM channels, utilizing up-counting, auto-reload, and independent output modes.
Quoted 5 lines
drivers/pwm/pwm-ma35d1.c new file +0
-0
[ ... ]
Quoted 8 lines
drivers/pwm/pwm-ma35d1.c new file +8
-0+static int nuvoton_pwm_apply (struct pwm_chip *chip,struct pwm_device *pwm, +const struct pwm_state *state) +{ +struct nuvoton_pwm *nvtpwm =nuvoton_pwm_from_chip (chip); +unsigned int ch = pwm->hwpwm; +u64 duty_cycles, period_cycles; +u64 divisor; +u32 cmpdat, period, prescale;
drivers/pwm/pwm-ma35d1.c line 215
Quoted 10 lines
drivers/pwm/pwm-ma35d1.c new file +10
-0+int ret; + +if (!state->enabled) { +nuvoton_pwm_rmw (nvtpwm,MA35D1_REG_PWM_POEN , +MA35D1_PWM_POEN_EN (ch),0 ); +nuvoton_pwm_rmw (nvtpwm,MA35D1_REG_PWM_CNTEN , +MA35D1_PWM_CNTEN_EN (ch),0 ); + +return 0 ; + }
[Severity: Medium]
Does this early return violate the PWM framework API contract by failing to apply the full requested state?
If a consumer calls pwm_apply_state() with state->enabled = false but includes updated polarity, period, or duty_cycle parameters, those changes appear to be silently dropped because of this early return.
Since nuvoton_pwm_get_state() reads the configuration directly from hardware registers, wouldn't subsequent state reads return stale values and desynchronize the PWM core's cached state from the actual hardware configuration?
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2
Quoted 2 lines · On Tue, Jul 21, 2026 at 06:33:43AM +0000, [email protected] wrote:
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The apply callback returns early when !state->enabled, dropping updates to polarity, period, andduty_cycle.
FTR: This is fine.
Best regards
Uwe
Uwe Kleine-König
maintainerHello,
drivers/pwm/pwm-ma35d1.c line 210
Quoted 13 lines · Chi-Wen Weng
drivers/pwm/pwm-ma35d1.c new file +13
-0+static int nuvoton_pwm_apply (struct pwm_chip *chip,struct pwm_device *pwm, +const struct pwm_state *state) +{ +struct nuvoton_pwm *nvtpwm =nuvoton_pwm_from_chip (chip); +unsigned int ch = pwm->hwpwm; +u64 duty_cycles, period_cycles; +u64 divisor; +u32 cmpdat, period, prescale; +int ret; + +if (!state->enabled) { +nuvoton_pwm_rmw (nvtpwm,MA35D1_REG_PWM_POEN , +MA35D1_PWM_POEN_EN (ch),0 );
Does this mean the output pin goes High-Z on disable?
Quoted 38 lines
drivers/pwm/pwm-ma35d1.c new file +38
-0+nuvoton_pwm_rmw (nvtpwm,MA35D1_REG_PWM_CNTEN , +MA35D1_PWM_CNTEN_EN (ch),0 ); + +return 0 ; + } + + prescale =nuvoton_pwm_get_prescale (nvtpwm, ch); + divisor = (u64 )NSEC_PER_SEC * (prescale +1 ); + + period_cycles =mul_u64_u64_div_u64 (nvtpwm->clkrate, + state->period, divisor); +if (!period_cycles) +return -EINVAL ; + +if (period_cycles >MA35D1_PWM_MAX_CYCLES ) + period_cycles =MA35D1_PWM_MAX_CYCLES ; + + duty_cycles =mul_u64_u64_div_u64 (nvtpwm->clkrate, + state->duty_cycle, divisor); +if (duty_cycles > period_cycles) + duty_cycles = period_cycles; + + ret =nuvoton_pwm_config_channel (nvtpwm, ch); +if (ret) +return ret; + +if (state->polarity ==PWM_POLARITY_NORMAL ) +nuvoton_pwm_rmw (nvtpwm,MA35D1_REG_PWM_POLCTL , +MA35D1_PWM_POLCTL_INV (ch),0 ); +else +nuvoton_pwm_rmw (nvtpwm,MA35D1_REG_PWM_POLCTL , +MA35D1_PWM_POLCTL_INV (ch), +MA35D1_PWM_POLCTL_INV (ch)); + +/* +* In up-counting mode the counter counts from 0 to PERIOD inclusive. +* With zero point high and compare-up point low actions: +* - CMPDAT = 0 produces 0% duty.
drivers/pwm/pwm-ma35d1.c line 258
Quoted 10 lines
drivers/pwm/pwm-ma35d1.c new file +10
-0+* - CMPDAT > PERIOD produces 100% duty. +* +* period_cycles is limited to 0xffff, so PERIOD is at most 0xfffe +* and a 100% duty cycle can be represented by CMPDAT = 0xffff. +*/ + period = period_cycles -1 ; + cmpdat = duty_cycles; + +nuvoton_pwm_writel (nvtpwm,MA35D1_REG_PWM_PERIOD (ch), period); +nuvoton_pwm_writel (nvtpwm,MA35D1_REG_PWM_CMPDAT (ch), cmpdat);
This is racy, right? (i.e. if a period end happens between these two writes, we see (probably) one period with the new period length and the old duty_cycle.
The result of the two questions should be a comment describing the behaviour, otherwise the code looks fine on a quick glance.
Best regards
Uwe