Enable ICE for UFS on Hamoa IoT EVK

This series enables the Inline Crypto Engine (ICE) hardware for UFS storage on the Qualcomm X1E80100 (Hamoa IoT EVK) platform.

The ICE hardware provides AES-256-XTS inline encryption/decryption for UFS storage, offloading cryptographic operations from the CPU. The hardware version on this platform is ICE v4.0.1 with HWKM v2 support.

Validation:
- Probe successfully
- Standard key work well

Patch 1 adds the new compatible string to the DT binding documentation. Patch 2 adds the ICE device node to the Hamoa DTSI.

Note: The allOf conditional block enforcement for power-domains and clock-names is handled by the prerequisite series.

---
Changes in v2:
- Improve commit messages for both patches.
- Link to v1: https://lore.kernel.org/r/[email protected]

---
Wenjia Zhang (2):
dt-bindings: crypto: qcom,inline-crypto-engine: Add x1e80100 support
arm64: dts: qcom: hamoa: Add ICE node for UFS inline encryption

 .../bindings/crypto/qcom,inline-crypto-engine.yaml          |  1 +
 arch/arm64/boot/dts/qcom/hamoa.dtsi                         | 13 +++++++++++++
 2 files changed, 14 insertions(+)

---
base-commit: 49362394dad7df66c274c867a271394c10ca2bb8
change-id: 20260714-devtool-5093900ac51a
prerequisite-change-id: 20260701-b4-shikra_crypto_changse-f2d6d5bf04b5:v4
prerequisite-patch-id: d5bc84db11dfa16371755109d32bafa6325a7706
prerequisite-patch-id: f653bca04deb0f4fe7d51b3064644c8e6b0d9c99
prerequisite-patch-id: 615f80abf57c155bbc190c1a70fe615a783755cf
prerequisite-patch-id: 59d8102674ce98be1a0e9b4d7939ffd8a7289ab1
prerequisite-patch-id: 691ec3b8a386d2c5b991a4311236f7f06adfc5b1
prerequisite-patch-id: 5b949e801e9bf4b5593a1f7cb8f02709eb3e869a

Best regards,

Wenjia Zhang <[email protected]>

Document the compatible string for inline crypto engine found on the Qualcomm X1E80100 SoC, used by the Hamoa IoT EVK board.

---
 Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml | 1 +
 1 file changed, 1 insertion(+)

index 92c3ba6eae13dbd8a6a448057e942a08cc3a3ea7..07d6778a287631262282d75c0d233919f4241edd 100644
@@ -25,6 +25,7 @@ properties:
           - qcom,sm8550-inline-crypto-engine
           - qcom,sm8650-inline-crypto-engine
           - qcom,sm8750-inline-crypto-engine
+          - qcom,x1e80100-inline-crypto-engine
       - const: qcom,inline-crypto-engine
 
   reg:

2.43.0

This is incomplete, although maybe you based this on Kuldeep's work but nothing explains that here nor in the cover letter.

Best regards,
Krzysztof

I added the prerequisites and note information in the cover letter. Here is the linkage of the prerequisite [PATCH v4 1/6] dt-bindings: crypto: <https://lore.kernel.org/lkml/20260714-b4-shikra_crypto_changse-v4-1-06a4ea97c209@oss.qualcomm.com/>
qcom,inline-crypto-engine: Fix legacy/new SoC strictness split - Kuldeep Singh <https://lore.kernel.org/lkml/20260714-b4-shikra_crypto_changse-v4-1-06a4ea97c209@oss.qualcomm.com/>

Best regards,
Wenjia Zhang

That does not count as it is pointless.

Which maintainer should include these prerequisities? Both? Then patch is NAKed as DTS cannot depend on driver patches.

Best regards,
Krzysztof

Hi Krzysztof,
Seems Wenjia rebased his hamoa effort on top of my work[1] and as per latest update, Herbert has applied the dependent binding change to his tree[2] and should be part of linux-next soon.

Please note, only [1] is prerequisite and not the entire series there.

With this, the dependency will be resolved and rebasing to latest linux-next(with [2] as part of it) should make this series as standalone. Will let Wenjia drop v3.

[1]
https://lore.kernel.org/lkml/20260714-b4-shikra_crypto_changse-v4-1-06a4ea97c209@oss.qualcomm.com/
[2]
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git/commit/?id=3360fa7604259a0341a9bdbb0a8cb0fd7f3109de

Regards
Kuldeep

Add the Inline Crypto Engine (ICE) device node to describe the hardware-accelerated inline encryption for UFS storage on the Hamoa IoT EVK board (Qualcomm X1E80100 SoC).

---
 arch/arm64/boot/dts/qcom/hamoa.dtsi | 13 +++++++++++++
 1 file changed, 13 insertions(+)

index 0840eb2f884f98d76442fac7888ed49a07780898..0c9b459055d720a528a319272161d1d7446daefd 100644
@@ -4176,6 +4176,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
 			phys = <&ufs_mem_phy>;
 			phy-names = "ufsphy";
 
+			qcom,ice = <&ice>;
+
 			#reset-cells = <1>;
 
 			status = "disabled";

@@ -4221,6 +4223,17 @@ opp-300000000 {
 			};
 		};
 
+		ice: crypto@1d88000 {
+			compatible = "qcom,x1e80100-inline-crypto-engine",
+				     "qcom,inline-crypto-engine";
+			reg = <0x0 0x01d88000 0x0 0x18000>;
+			clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
+				 <&gcc GCC_UFS_PHY_AHB_CLK>;
+			clock-names = "core",
+				      "iface";
+			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
+		};
+
 		cryptobam: dma-controller@1dc4000 {
 			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
 			reg = <0x0 0x01dc4000 0x0 0x28000>;

2.43.0

Regards,
Harshal