arm64: qcom: add Ayaneo Pocket DS gaming console

This series adds initial support for the Ayaneo Pocket DS, a handheld gaming console built around the Qualcomm QCS8550 SoC. It has UFS storage, WiFi/Bluetooth, gaming buttons, microSD, and USB-C with DisplayPort. Game controls are exposed through a Renesas uPD720201 PCIe USB 3.0 host controller hung off PCIe1, while a dedicated gamepad MCU is reached over UART11.

The series is structured as:

1. dt-bindings entry for the new ayaneo,pocket-ds compatible.
2. sm8550.dtsi: add the QUP2 SE3 (UART11) controller node and its default pinctrl, so the board can enable it as &uart11.
3. The Pocket DS board device tree itself, together with thermal_* labels for the cpuss/cpu/gpuss thermal zones added to sm8550.dtsi so the board has a real user of them in the same patch.

Only the basics are wired up at this stage (boot to console, core peripherals, USB-C with DP and SBU AUX muxing, microSD, WiFi/BT, gaming controls, volume keys and PWM-fan cooling); the DSI display panel and the secondary panel rail will follow in a later submission once the upstream panel binding lands.

---
Changes in v4:
- Reordered the series so the sm8550.dtsi UART11 patch comes before the board dts that consumes &uart11, keeping the tree bisectable (Dmitry).
- Renamed the board compatible from "ayaneo,pocketds" to "ayaneo,pocket-ds", matching the hyphenated "ayaneo,pocket-s2" already in qcom.yaml and the DT compatible naming convention (Sashiko). The Acked-by on the bindings patch was given for the unhyphenated string; kept it since the change is a one-word rename, please shout if you would rather re-ack it.
- uart11: switched operating-points-v2 to &qup_opp_table_120mhz, which is what i2c11 and spi11 use for the very same serial engine at 0x88c000; the 100 MHz table was simply wrong (Sashiko).
- uart11: use bias-pull-up rather than bias-disable on TX/RX, matching qup_uart14_default, the other high-speed UART on this SoC (Sashiko).
- Reworded the UART11 commit message, which implied that open-coding the controller in a board dts was a viable alternative (Konrad).
- Squashed the sm8550.dtsi thermal-zone labels patch into the board dts patch so the labels gain their consumer in the same change (Krzysztof).
- Renamed the sm8550.dtsi thermal-zone labels from
cpuss[0-3]_thermal / cpu7_top_thermal / gpuss[0-7]_thermal to thermal_cpuss[0-3] / thermal_cpu7_top / thermal_gpuss[0-7] so all thermal-related overrides cluster alphabetically in the consuming board dts (Dmitry).
- Dropped the &gpu_opp_table override until upstream gains proper speed-bin detection (Dmitry).
- Switched remoteproc_adsp firmware-name from the downstream .mdt suffix to the upstream .mbn convention (Dmitry).
- Replaced the /delete-node/ overrides on &remoteproc_mpss / &remoteproc_cdsp with /delete-property/ memory-region (Dmitry). Both are already status="disabled" in sm8550.dtsi, so the nodes never needed deleting; only their now-dangling memory-region phandles did. The reserved-memory regions for the unused modem, CDSP, camera and IPA firmware stay /delete-node/-ed so that memory is handed back to Linux, matching what sm8550-samsung-q5q and sm8550-sony-xperia-yodo-pdx234 already do on this SoC.
- Dropped the downstream rocknix-u-boot-dt-id root property (Neil).
- Switched the deprecated "gpio" property to "gpios" on all fixed regulators (Neil).
- Reworked the audio-routing DAPM table to drop the bogus
"VA DMIC0/1, vdd-micb" routes (Neil).
- Reshaped the per-zone thermal-zones overrides to a single "active" trip point bound to &pwm_fan via cooling-maps, mirroring the
Ayaneo Pocket S2 style (Neil).
- Added a pinctrl-1 sleep state for pwm_fan and the corresponding fan_pwm_sleep PMIC pinctrl entry (Neil).
- Added a gpio-keys node wiring up the Volume Up button via the previously-unreferenced volume_up_n pinctrl (Neil).
- Dropped every output-high in the &tlmm pinctrl states (Neil).
- Dropped the incomplete DSI/panel bring-up (display_panel, &mdss_dsi0, &mdss_dsi0_phy, &mdss_dsi1, &mdss_dsi1_out, &mdss_dsi1_phy and the sde_dsi*/sde_te*/panel_pwr_active pinctrl) until the panel bindings are reviewed (Neil).
- Added the missing SBU AUX endpoint between the pmic-glink connector and the NB7VPQ904M redriver port@2 to complete the DP altmode
signal path (Neil).
- Normalised the last fixed-regulator node name to the "<name>-regulator" convention (vph_pwr) (Krzysztof).
- Reauthored the bindings patch under Alexandre alone (no co-developed needed for the trivial DT entry) and picked up Krzysztof's Acked-by.
- Fixed the sign-off chain on the board dts patch: the From: author's Signed-off-by now comes first and the submitter's last (Krzysztof).
- No qup_uart11_cts_rts pinctrl state was added: nothing in-tree references it, and hardware flow control is not wired on this board. It can be added together with its first user (Sashiko).
- Built with "make CHECK_DTBS=yes qcom/qcs8550-ayaneo-pocket-ds.dtb":
no errors, no warnings. With W=1 dtc additionally reports avoid_unnecessary_addr_size on sm8550.dtsi's dsi@ae94000/dsi@ae96000, because no panel child is added while display support is deferred; qcs8550-aim300-aiot already reports the same for dsi@ae96000.
- board dts: enabled &pcie0_phy and added the &pcieport0 wifi@0 supply node for the WCN7850. Without the PCIe0 PHY and the vddpcie0p9 / vddpcie1p8 rails the WiFi link never trained; the wifi@0 supply node follows sm8650-ayaneo-pocket-s2 and the sm8550/sm8650 QRD/HDK boards.
- board dts: dropped &i2c4 to 100 kHz. The FT5426 touchscreen clock-stretches past the GENI controller's timeout at 400 kHz, and the qcom-geni-i2c controller has no i2c_bus_recovery, so a stuck SCL can only be cleared by an FSM reset that is itself the operation timing out. Standard mode is within the FT5426's clock-stretch spec.
- board dts: pinned &pcie0 to max-link-speed = <2> (Gen2), the link speed validated for the WCN7850 on this board.
- board dts: dropped the undocumented sdhci-caps-mask = <0x3 0x0> on &sdhc_2 (it masked the SDR50/SDR104 capability bits that the board's own sd-uhs-sdr50 / sd-uhs-sdr104 properties enable). qcom,dll-config is kept, with its derivation now recorded in the commit message.
- Renamed the board dts to qcs8550-ayaneo-pocket-ds.dts to match the hyphenated compatible and the sibling sm8650-ayaneo-pocket-s2.dts; the Makefile entry and the CHECK_DTBS target were updated to suit.
- Note on the UART11 Reviewed-by: Konrad's tag was given on v3, before the operating-points-v2 (&qup_opp_table_120mhz) and bias-pull-up changes above. It is retained here; happy to drop it for a re-review.
- Link to v3: https://patch.msgid.link/[email protected]

Changes in v3:
- New prerequisite patch adding the QUP2 SE3 (UART11) controller node and the qup_uart11_default pinctrl state to sm8550.dtsi, so the board can enable the gamepad MCU UART via &uart11 instead of duplicating the controller node in the board dts.
- Alphabetised the root-level nodes in the board dts and renamed the fixed regulators to the "<name>-regulator" node-name convention.
- Link to v2: https://patch.msgid.link/[email protected]

Changes in v2:
- Inlined the board into a single qcs8550-ayaneo-pocketds.dts, matching the sm8650-ayaneo-pocket-s2 layout
- Added qcom,qcs8550 to the compatible chain
- Prerequisite patch labelling the sm8550 thermal zones so the board can extend them via &label overrides (and refactored the board's thermal-zones to use them)
- Added the Renesas uPD720201 USB 3.0 controller as a child of pcie1 with proper avdd33 / vdd10 / vdd33 regulators
- Moved gamepad_pwr_en off &pcie1's pinctrl-0 and onto the usb-controller node
- Split the lumped upd720201_active pinctrl into per-regulator states
- Fixed mdss_dp0_out data-lanes to <0 1 2 3> (all four wired)
- Fixed gpio-reserved-ranges to <32 4> (gpio 38-39 drive the Goodix touchscreen)
- Renamed nodes with underscores (llcc-lpi-region, splash-region, gpio@20) per DT conventions
- Reordered pinctrl-names after pinctrl-N file-wide
- Dropped the unused cont_splash_region label
- Link to v1: https://patch.msgid.link/[email protected]

To: Bjorn Andersson <[email protected]>
To: Konrad Dybcio <[email protected]>
To: Rob Herring <[email protected]>
To: Krzysztof Kozlowski <[email protected]>
To: Conor Dooley <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]

---
Alexandre Hamamdjian (2):
dt-bindings: arm: qcom: document the Ayaneo Pocket DS
arm64: dts: qcom: sm8550: add UART11 node

Teguh Sobirin (1):
arm64: dts: qcom: add basic devicetree for Ayaneo Pocket DS gaming console

 Documentation/devicetree/bindings/arm/qcom.yaml    |    6 +
 arch/arm64/boot/dts/qcom/Makefile                  |    1 +
 .../boot/dts/qcom/qcs8550-ayaneo-pocket-ds.dts     | 1617 ++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sm8550.dtsi               |   52 +-
 4 files changed, 1663 insertions(+), 13 deletions(-)

---
base-commit: e98d21c170b01ddef366f023bbfcf6b31509fa83
change-id: 20260510-pocketds-e0e7b99cf369

Best regards,

Alexandre Hamamdjian <[email protected]>

Document the Qualcomm QCS8550 based Ayaneo Pocket DS gaming console.

---
 Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

index 2741c07e9f41..b5dad29a8606 100644
@@ -1107,6 +1107,12 @@ properties:
           - const: qcom,qcs8550
           - const: qcom,sm8550
 
+      - items:
+          - enum:
+              - ayaneo,pocket-ds
+          - const: qcom,qcs8550
+          - const: qcom,sm8550
+
       - items:
           - enum:
               - ayaneo,pocket-s2

2.55.0

Add the QUPv3_2 SE3 UART (UART11) controller node and its default pinctrl state to sm8550.dtsi, so boards with a peripheral wired to that serial engine can enable it through &uart11.

The serial engine at 0x88c000 is already described as i2c11 and spi11, so the UART node takes the same qup_opp_table_120mhz they use: it is the same block behind the same GCC_QUPV3_WRAP2_S3_CLK, and its core clock tops out at 120 MHz rather than the 100 MHz the other table allows. TX and RX are biased pull-up, matching qup_uart14_default, so the lines idle high on boards that do not fit external pull-ups.

---
 arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

index 912525e9bca6..165c0248da53 100644
@@ -1084,6 +1084,24 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
 				status = "disabled";
 			};
 
+			uart11: serial@88c000 {
+				compatible = "qcom,geni-uart";
+				reg = <0 0x0088c000 0 0x4000>;
+				clock-names = "se";
+				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
+				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&qup_uart11_default>;
+				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
+						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
+						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
+				interconnect-names = "qup-core", "qup-config";
+				operating-points-v2 = <&qup_opp_table_120mhz>;
+				power-domains = <&rpmhpd RPMHPD_CX>;
+				status = "disabled";
+			};
+
 			i2c12: i2c@890000 {
 				compatible = "qcom,geni-i2c";
 				reg = <0 0x00890000 0 0x4000>;

@@ -5102,6 +5120,14 @@ qup_uart7_default: qup-uart7-default-state {
 				bias-disable;
 			};
 
+			qup_uart11_default: qup-uart11-default-state {
+				/* TX, RX */
+				pins = "gpio70", "gpio71";
+				function = "qup2_se3";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+
 			qup_uart14_default: qup-uart14-default-state {
 				/* TX, RX */
 				pins = "gpio78", "gpio79";

2.55.0

From: Teguh Sobirin <[email protected]>

Add initial Device Tree for the Ayaneo Pocket DS gaming console based on the Qualcomm QCS8550 platform.

The design is similar to a phone without the modem: game controls are exposed through a Renesas uPD720201 PCIe USB 3.0 host controller hung off PCIe1, while a dedicated gamepad MCU is reached over UART11. DisplayPort is muxed over the USB-C connector with all four lanes wired, with an ON Semi NB7VPQ904M redriver handling SS and SBU AUX muxing.

Only the basics are wired up at this stage (boot to console, core peripherals, USB-C and DP, microSD, WiFi/BT, gaming controls); DSI panel support will follow in a later submission once the panel bindings are reviewed.

The FT5426 touchscreen on i2c4 clock-stretches past the GENI controller's timeout at 400 kHz. The qcom-geni-i2c controller implements no i2c_bus_recovery, so a stuck SCL can only be cleared by an FSM reset, which is itself the operation that times out. i2c4 is therefore run at 100 kHz, well within the FT5426's clock-stretch tolerance and with ample bandwidth for its sub-256-byte reports.

PCIe0 hosts the WCN7850 WiFi and is pinned to Gen2 (max-link-speed = <2>), the link speed validated on this board.

sdhc_2 sets qcom,dll-config to 0x0007442c, the DLL_CONFIG value the QCS8550 vendor device tree ships for this SDCC2 instance, in place of the generic sm8550 default of 0x0007642c; the vendor value is the one validated for SDR104 operation on this board.

The board uses the &thermal_cpuss[0-3], &thermal_cpu7_top and &thermal_gpuss[0-7] labels to extend the SoC thermal zones with an active trip point and a cooling map driving the on-board PWM fan; those labels are added to sm8550.dtsi as part of this change so the board has a real user from the same patch.

---
 arch/arm64/boot/dts/qcom/Makefile                  |    1 +
 .../boot/dts/qcom/qcs8550-ayaneo-pocket-ds.dts     | 1617 ++++++++++++++++++++
 arch/arm64/boot/dts/qcom/sm8550.dtsi               |   26 +-
 3 files changed, 1631 insertions(+), 13 deletions(-)

index cc42829f92eb..81abb05529ec 100644
@@ -185,6 +185,7 @@ qcs8300-ride-el2-dtbs := qcs8300-ride.dtb monaco-el2.dtbo
 
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs8300-ride-el2.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-aim300-aiot.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= qcs8550-ayaneo-pocket-ds.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= qcs9100-ride-r3.dtb
 

index 165c0248da53..26797e9668f2 100644
@@ -5790,7 +5790,7 @@ reset-mon-config {
 			};
 		};
 
-		cpuss0-thermal {
+		thermal_cpuss0: cpuss0-thermal {
 			thermal-sensors = <&tsens0 1>;
 
 			trips {

@@ -5808,7 +5808,7 @@ reset-mon-config {
 			};
 		};
 
-		cpuss1-thermal {
+		thermal_cpuss1: cpuss1-thermal {
 			thermal-sensors = <&tsens0 2>;
 
 			trips {

@@ -5826,7 +5826,7 @@ reset-mon-config {
 			};
 		};
 
-		cpuss2-thermal {
+		thermal_cpuss2: cpuss2-thermal {
 			thermal-sensors = <&tsens0 3>;
 
 			trips {

@@ -5844,7 +5844,7 @@ reset-mon-config {
 			};
 		};
 
-		cpuss3-thermal {
+		thermal_cpuss3: cpuss3-thermal {
 			thermal-sensors = <&tsens0 4>;
 
 			trips {

@@ -6054,7 +6054,7 @@ cpu6_bottom_crit: cpu-critical {
 			};
 		};
 
-		cpu7-top-thermal {
+		thermal_cpu7_top: cpu7-top-thermal {
 			thermal-sensors = <&tsens0 13>;
 
 			trips {

@@ -6562,7 +6562,7 @@ reset-mon-config {
 			};
 		};
 
-		gpuss-0-thermal {
+		thermal_gpuss0: gpuss-0-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 1>;

@@ -6595,7 +6595,7 @@ trip-point2 {
 			};
 		};
 
-		gpuss-1-thermal {
+		thermal_gpuss1: gpuss-1-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 2>;

@@ -6628,7 +6628,7 @@ trip-point2 {
 			};
 		};
 
-		gpuss-2-thermal {
+		thermal_gpuss2: gpuss-2-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 3>;

@@ -6661,7 +6661,7 @@ trip-point2 {
 			};
 		};
 
-		gpuss-3-thermal {
+		thermal_gpuss3: gpuss-3-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 4>;

@@ -6694,7 +6694,7 @@ trip-point2 {
 			};
 		};
 
-		gpuss-4-thermal {
+		thermal_gpuss4: gpuss-4-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 5>;

@@ -6727,7 +6727,7 @@ trip-point2 {
 			};
 		};
 
-		gpuss-5-thermal {
+		thermal_gpuss5: gpuss-5-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 6>;

@@ -6760,7 +6760,7 @@ trip-point2 {
 			};
 		};
 
-		gpuss-6-thermal {
+		thermal_gpuss6: gpuss-6-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 7>;

@@ -6793,7 +6793,7 @@ trip-point2 {
 			};
 		};
 
-		gpuss-7-thermal {
+		thermal_gpuss7: gpuss-7-thermal {
 			polling-delay-passive = <10>;
 
 			thermal-sensors = <&tsens2 8>;

2.55.0