FAILED: patch "[PATCH] drm/xe/uapi: Reject coh_none PAT index for CPU_ADDR_MIRROR" failed to apply to 7.1-stable tree

-----Original Message-----
From: [email protected] <[email protected]>
Sent: Wednesday, July 29, 2026 3:37 AM
To: Yao, Jia <[email protected]>; Mathew, Alwin <[email protected]>; Auld, Matthew <[email protected]>; Brost, Matthew <[email protected]>; Mrozek, Michal <[email protected]>; Lin, Shuicheng <[email protected]>; [email protected]
Cc: [email protected]
Subject: FAILED: patch "[PATCH] drm/xe/uapi: Reject coh_none PAT index for CPU_ADDR_MIRROR" failed to apply to 7.1-stable tree

The patch below does not apply to the 7.1-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

To reproduce the conflict and resubmit, you may use the following commands:

git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/
linux-7.1.y git checkout FETCH_HEAD git cherry-pick -x 4d58d7535e826a3175527b6174502f0db319d7f6
# <resolve conflicts, build, test, etc.> git commit -s git send-email --to '<[email protected]>' --in-reply-to '2026072909-boil-smartness- 3be9@gregkh' --subject-prefix 'PATCH 7.1.y' 'HEAD^..'

Possible dependencies:

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 4d58d7535e826a3175527b6174502f0db319d7f6 Mon Sep 17 00:00:00 2001
From: Jia Yao <[email protected]>
Date: Fri, 17 Apr 2026 05:59:17 +0000
Subject: [PATCH] drm/xe/uapi: Reject coh_none PAT index for CPU_ADDR_MIRROR

Add validation in xe_vm_bind_ioctl() to reject PAT indices with XE_COH_NONE coherency mode when used with DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR.

CPU address mirror mappings use system memory that is CPU cached, which makes them incompatible with COH_NONE PAT indices. Allowing COH_NONE with CPU cached buffers is a security risk, as the GPU may bypass CPU caches and read stale sensitive data from DRAM.

Although CPU_ADDR_MIRROR does not create an immediate mapping, the backing system memory is still CPU cached.
Apply the same PAT coherency restrictions as DRM_XE_VM_BIND_OP_MAP_USERPTR.

v2:
- Correct fix tag

v6:
- No change

v7:
- Correct fix tag

v8:
- Rebase

v9:
- Limit the restrictions to iGPU

v10:
- Just add the iGPU logic but keep dGPU logic

Fixes b43e864af0d4 ("drm/xe/uapi: Add

DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR")

Cc <[email protected]> # v6.15+

Cc Shuicheng Lin <[email protected]>

Cc Mathew Alwin <[email protected]>

Cc Michal Mrozek <[email protected]>

Cc Matthew Brost <[email protected]>

Cc Matthew Auld <[email protected]>

Signed-off-by Jia Yao <[email protected]>

Reviewed-by Matthew Auld <[email protected]>

Acked-by Michal Mrozek <[email protected]>

Signed-off-by Matthew Auld <[email protected]>

Link https://patch.msgid.link/20260417055917.2027459-3-

[email protected]

drivers/gpu/drm/xe/xe_vm.c index renamed from drivers/gpu/drm/xe/xe_vm.c +0 -0

5f4220125c76..c3836f6eab35 100644

drivers/gpu/drm/xe/xe_vm.c +0 -0

@@ -3658,6 +3658,8 @@ static int vm_bind_ioctl_check_args(struct
 xe_device *xe, struct xe_vm *vm,
 				 op ==

DRM_XE_VM_BIND_OP_MAP_USERPTR) ||

drivers/gpu/drm/xe/xe_vm.c +0 -0

 		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
 				 op ==

DRM_XE_VM_BIND_OP_MAP_USERPTR) ||

drivers/gpu/drm/xe/xe_vm.c +1 -0

+		    XE_IOCTL_DBG(xe, !IS_DGFX(xe) && coh_mode ==

XE_COH_NONE &&

drivers/gpu/drm/xe/xe_vm.c +1 -0

+				 is_cpu_addr_mirror) ||
 		    XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
 				 (op ==

DRM_XE_VM_BIND_OP_MAP_USERPTR ||
is_cpu_addr_mirror) &&