FAILED: patch "[PATCH] ASoC: fsl_sai: Fix spurious BCLK on resume by clearing BYP" failed to apply to 6.6-stable tree
Subsystems (4)
[email protected]
maintainerThe patch below does not apply to the 6.6-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.6.y
git checkout FETCH_HEAD
git cherry-pick -x d091132889c1378dd0944a72f86eae3e4da1e4fa
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2026072959-timid-mortify-1131@gregkh' --subject-prefix 'PATCH 6.6.y' 'HEAD^..'
Possible dependencies:
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From d091132889c1378dd0944a72f86eae3e4da1e4fa Mon Sep 17 00:00:00 2001
From: Chancel Liu <[email protected]>
Date: Fri, 10 Jul 2026 16:08:35 +0900
Subject: [PATCH] ASoC: fsl_sai: Fix spurious BCLK on resume by clearing BYP
When the BCLK divider ratio is 1:1, fsl_sai_set_bclk() enables bypass mode by setting BYP, but never clears the bit. The BYP=1 value remains in the regcache, and is restored by regcache_sync() on the next runtime resume.
Since BYP=1 combined with BCD=1 immediately outputs the ungated MCLK as BCLK without waiting for BCE/TE/RE to be enabled, the clock is driven prematurely before the stream is fully configured, causing noise on some codecs.
Fix this by clearing BYP and BCI in fsl_sai_hw_free() taking into account sync mode and the opposite stream's state, so that the regcache holds BYP=0 before runtime suspend and regcache_sync() on resume will not restore bypass mode prematurely.
sound/soc/fsl/fsl_sai.c +25 -4
@@ -808,6 +808,8 @@ static int fsl_sai_hw_free(struct snd_pcm_substream *substream,struct fsl_sai *sai =snd_soc_dai_get_drvdata (cpu_dai);bool tx = substream->stream ==SNDRV_PCM_STREAM_PLAYBACK ;unsigned int ofs = sai->soc_data->reg_offset; +int adir = tx ?RX :TX ; +int dir = tx ?TX :RX ;/* Clear xMR to avoid channel swap with mclk_with_tere enabled case */ regmap_write (sai->regmap,FSL_SAI_xMR (tx),0 );
@@ -815,10 +817,29 @@ static int fsl_sai_hw_free(struct snd_pcm_substream *substream,regmap_update_bits (sai->regmap,FSL_SAI_xCR3 (tx, ofs),FSL_SAI_CR3_TRCE_MASK ,0 ); -if (!sai->is_consumer_mode[tx] && - sai->mclk_streams &BIT (substream->stream)) { -clk_disable_unprepare (sai->mclk_clk[sai->mclk_id[tx]]); - sai->mclk_streams &= ~BIT (substream->stream); +if (!sai->is_consumer_mode[tx]) { +bool adir_active = !!(sai->mclk_streams &BIT (!substream->stream)); +/* +* If opposite stream provides clocks for synchronous mode and +* it is inactive, Clear BYP and BCI +*/ +if (fsl_sai_dir_is_synced (sai, adir) && !adir_active) +regmap_update_bits (sai->regmap,FSL_SAI_xCR2 (!tx, ofs), +FSL_SAI_CR2_BCI |FSL_SAI_CR2_BYP ,0 ); +/* +* Clear BYP and BCI of current stream if either of: +* 1. current stream doesn't provide clocks for synchronous mode +* 2. current stream provides clocks for synchronous mode but no +* more stream is active. +*/ +if (!fsl_sai_dir_is_synced (sai, dir) || !adir_active) +regmap_update_bits (sai->regmap,FSL_SAI_xCR2 (tx, ofs), +FSL_SAI_CR2_BCI |FSL_SAI_CR2_BYP ,0 ); + +if (sai->mclk_streams &BIT (substream->stream)) { +clk_disable_unprepare (sai->mclk_clk[sai->mclk_id[tx]]); + sai->mclk_streams &= ~BIT (substream->stream); + } }return 0 ;
Sasha Levin
maintainerPATCH 1/1 ASoC: fsl_sai: Fix spurious BCLK on resume by clearing BYP
From: Chancel Liu <[email protected]>
[ Upstream commit d091132889c1378dd0944a72f86eae3e4da1e4fa ]
When the BCLK divider ratio is 1:1, fsl_sai_set_bclk() enables bypass mode by setting BYP, but never clears the bit. The BYP=1 value remains in the regcache, and is restored by regcache_sync() on the next runtime resume.
Since BYP=1 combined with BCD=1 immediately outputs the ungated MCLK as BCLK without waiting for BCE/TE/RE to be enabled, the clock is driven prematurely before the stream is fully configured, causing noise on some codecs.
Fix this by clearing BYP and BCI in fsl_sai_hw_free() taking into account sync mode and the opposite stream's state, so that the regcache holds BYP=0 before runtime suspend and regcache_sync() on resume will not restore bypass mode prematurely.
--- sound/soc/fsl/fsl_sai.c | 29 +++++++++++++++++++++++++---- 1 file changed, 25 insertions(+), 4 deletions(-)
sound/soc/fsl/fsl_sai.c +25 -4
@@ -716,6 +716,8 @@ static int fsl_sai_hw_free(struct snd_pcm_substream *substream,struct fsl_sai *sai =snd_soc_dai_get_drvdata (cpu_dai);bool tx = substream->stream ==SNDRV_PCM_STREAM_PLAYBACK ;unsigned int ofs = sai->soc_data->reg_offset; +int adir = tx ?RX :TX ; +int dir = tx ?TX :RX ;/* Clear xMR to avoid channel swap with mclk_with_tere enabled case */ regmap_write (sai->regmap,FSL_SAI_xMR (tx),0 );
@@ -723,10 +725,29 @@ static int fsl_sai_hw_free(struct snd_pcm_substream *substream,regmap_update_bits (sai->regmap,FSL_SAI_xCR3 (tx, ofs),FSL_SAI_CR3_TRCE_MASK ,0 ); -if (!sai->is_consumer_mode && - sai->mclk_streams &BIT (substream->stream)) { -clk_disable_unprepare (sai->mclk_clk[sai->mclk_id[tx]]); - sai->mclk_streams &= ~BIT (substream->stream); +if (!sai->is_consumer_mode) { +bool adir_active = !!(sai->mclk_streams &BIT (!substream->stream)); +/* +* If opposite stream provides clocks for synchronous mode and +* it is inactive, Clear BYP and BCI +*/ +if (fsl_sai_dir_is_synced (sai, adir) && !adir_active) +regmap_update_bits (sai->regmap,FSL_SAI_xCR2 (!tx, ofs), +FSL_SAI_CR2_BCI |FSL_SAI_CR2_BYP ,0 ); +/* +* Clear BYP and BCI of current stream if either of: +* 1. current stream doesn't provide clocks for synchronous mode +* 2. current stream provides clocks for synchronous mode but no +* more stream is active. +*/ +if (!fsl_sai_dir_is_synced (sai, dir) || !adir_active) +regmap_update_bits (sai->regmap,FSL_SAI_xCR2 (tx, ofs), +FSL_SAI_CR2_BCI |FSL_SAI_CR2_BYP ,0 ); + +if (sai->mclk_streams &BIT (substream->stream)) { +clk_disable_unprepare (sai->mclk_clk[sai->mclk_id[tx]]); + sai->mclk_streams &= ~BIT (substream->stream); + } }return 0 ;
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