dt-bindings: pinctrl: tegra264: fix DAP2 DIN/DOUT pin names

PATCH RESEND In review Prathamesh Shete 6 participants 12 messages Jul 27 – Aug 6

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Device tree bindings GPIO Tegra architecture support Pin control

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Prathamesh Shete

author

2026-07-27 14:11 UTC #0 lore raw

PATCH RESEND v2 1/2 dt-bindings: pinctrl: tegra264: fix DAP2 DIN/DOUT pin names

The DAP2_DIN and DAP2_DOUT pins were listed with swapped ball suffixes:
DAP2_DIN as PV7 and DAP2_DOUT as PW0. On silicon DAP2_DIN is on ball PW0 and DAP2_DOUT is on ball PV7. Correct the pin and drive group names to dap2_din_pw0 and dap2_dout_pv7.

Fixes 30a9d5162f25 ("dt-bindings: pinctrl: Document Tegra264 pin controllers")

Signed-off-by Prathamesh Shete <[email protected]>

---
 .../bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml       | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml +3 -3

index c40409d3263c..01db762e82bc 100644
@@ -44,7 +44,7 @@ patternProperties:
                     soc_gpio173_pu3, soc_gpio174_pu4, soc_gpio175_pu5,
                     soc_gpio176_pu6, soc_gpio177_pu7, soc_gpio178_pv0,
                     pwm10_pv1, uart4_tx_pv2, uart4_rx_pv3, uart4_rts_n_pv4,
-                    uart4_cts_n_pv5, dap2_clk_pv6, dap2_din_pv7, dap2_dout_pw0,
+                    uart4_cts_n_pv5, dap2_clk_pv6, dap2_din_pw0, dap2_dout_pv7,
                     dap2_fs_pw1, gen1_i2c_scl_pw2, gen1_i2c_sda_pw3,
                     gen0_i2c_scl_pw4, gen0_i2c_sda_pw5, pwr_i2c_scl_pw6,
                     pwr_i2c_sda_pw7, soc_gpio138_pp0, soc_gpio139_pp1,

@@ -111,8 +111,8 @@ patternProperties:
                     drive_soc_gpio351_ps1, drive_gen0_i2c_scl_pw4,
                     drive_gen0_i2c_sda_pw5, drive_gen1_i2c_scl_pw2,
                     drive_gen1_i2c_sda_pw3, drive_dap2_fs_pw1,
-                    drive_dap2_clk_pv6, drive_dap2_din_pv7,
-                    drive_dap2_dout_pw0, drive_pwm10_pv1,
+                    drive_dap2_clk_pv6, drive_dap2_din_pw0,
+                    drive_dap2_dout_pv7, drive_pwm10_pv1,
                     drive_soc_gpio170_pu0, drive_soc_gpio171_pu1,
                     drive_soc_gpio172_pu2, drive_soc_gpio173_pu3,
                     drive_soc_gpio174_pu4, drive_soc_gpio175_pu5,

Signature · 1 line

2.17.1

Prathamesh Shete

author

2026-07-27 14:11 UTC #1 lore raw

PATCH RESEND v2 2/2 pinctrl: tegra264: fix DAP2 DIN/DOUT pin assignment

The dap2_din and dap2_dout pin groups were given swapped ball suffixes:
DAP2_DIN was described as ball PV7 and DAP2_DOUT as ball PW0. On silicon DAP2_DIN is on ball PW0 (mux register 0x6050, drive register 0x6054) and DAP2_DOUT is on ball PV7 (mux register 0x6058, drive register 0x605c), as reflected by the board pinmux.

Because the ball suffixes were swapped, the groups were also assigned the wrong primary mux functions (dap2_din -> I2S2_SDATA_OUT and dap2_dout -> I2S2_SDATA_IN), routing the I2S2 data-in and data-out signals to the wrong pins and breaking DAP2 audio.

Rename the groups to dap2_din_pw0 and dap2_dout_pv7 and give each pad its correct function (dap2_din_pw0 -> I2S2_SDATA_IN, dap2_dout_pv7 -> I2S2_SDATA_OUT). The register offsets are already correct and are left unchanged. This matches the board pinmux.

Fixes c98506206912 ("pinctrl: tegra: Add Tegra264 pinmux driver")

Signed-off-by Prathamesh Shete <[email protected]>

---
Changes in v2:
- Rename the pin groups to dap2_din_pw0 and dap2_dout_pv7 and assign the correct mux function to each pad in a single driver patch.

---
 drivers/pinctrl/tegra/pinctrl-tegra264.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

drivers/pinctrl/tegra/pinctrl-tegra264.c +12 ~~-12~~

index be64fba34dce..f8afb0bdb68a 100644
@@ -96,8 +96,8 @@ enum {
 	TEGRA_PIN_UART4_RTS_N_PV4,
 	TEGRA_PIN_UART4_CTS_N_PV5,
 	TEGRA_PIN_DAP2_CLK_PV6,
-	TEGRA_PIN_DAP2_DIN_PV7,
-	TEGRA_PIN_DAP2_DOUT_PW0,
+	TEGRA_PIN_DAP2_DIN_PW0,
+	TEGRA_PIN_DAP2_DOUT_PV7,
 	TEGRA_PIN_DAP2_FS_PW1,
 	TEGRA_PIN_GEN1_I2C_SCL_PW2,
 	TEGRA_PIN_GEN1_I2C_SDA_PW3,

@@ -329,8 +329,8 @@ static const struct pinctrl_pin_desc tegra264_main_pins[] = {
 	PINCTRL_PIN(TEGRA_PIN_UART4_RTS_N_PV4, "UART4_RTS_N_PV4"),
 	PINCTRL_PIN(TEGRA_PIN_UART4_CTS_N_PV5, "UART4_CTS_N_PV5"),
 	PINCTRL_PIN(TEGRA_PIN_DAP2_CLK_PV6, "DAP2_CLK_PV6"),
-	PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PV7, "DAP2_DIN_PV7"),
-	PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PW0, "DAP2_DOUT_PW0"),
+	PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PW0, "DAP2_DIN_PW0"),
+	PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PV7, "DAP2_DOUT_PV7"),
 	PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PW1, "DAP2_FS_PW1"),
 	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PW2, "GEN1_I2C_SCL_PW2"),
 	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PW3, "GEN1_I2C_SDA_PW3"),

@@ -827,12 +827,12 @@ static const unsigned int dap2_clk_pv6_pins[] = {
 	TEGRA_PIN_DAP2_CLK_PV6,
 };
 
-static const unsigned int dap2_din_pv7_pins[] = {
-	TEGRA_PIN_DAP2_DIN_PV7,
+static const unsigned int dap2_din_pw0_pins[] = {
+	TEGRA_PIN_DAP2_DIN_PW0,
 };
 
-static const unsigned int dap2_dout_pw0_pins[] = {
-	TEGRA_PIN_DAP2_DOUT_PW0,
+static const unsigned int dap2_dout_pv7_pins[] = {
+	TEGRA_PIN_DAP2_DOUT_PV7,
 };
 
 static const unsigned int dap2_fs_pw1_pins[] = {

@@ -1834,8 +1834,8 @@ static const char * const tegra264_functions[] = {
 #define drive_gen1_i2c_sda_pw3 DRV_PINGROUP_ENTRY_Y(0x601c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
 #define drive_dap2_fs_pw1 DRV_PINGROUP_ENTRY_Y(0x6044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
 #define drive_dap2_clk_pv6 DRV_PINGROUP_ENTRY_Y(0x604c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
-#define drive_dap2_din_pv7 DRV_PINGROUP_ENTRY_Y(0x6054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
-#define drive_dap2_dout_pw0 DRV_PINGROUP_ENTRY_Y(0x605c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap2_din_pw0 DRV_PINGROUP_ENTRY_Y(0x6054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap2_dout_pv7 DRV_PINGROUP_ENTRY_Y(0x605c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
 #define drive_pwm10_pv1 DRV_PINGROUP_ENTRY_Y(0x6064, 12, 4, 20, 4, -1, -1, -1, -1, 0)
 #define drive_soc_gpio170_pu0 DRV_PINGROUP_ENTRY_Y(0x606c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
 #define drive_soc_gpio171_pu1 DRV_PINGROUP_ENTRY_Y(0x6074, 12, 4, 20, 4, -1, -1, -1, -1, 0)

@@ -2051,8 +2051,8 @@ static const struct tegra_pingroup tegra264_main_groups[] = {
 	PINGROUP(gen1_i2c_sda_pw3, I2C1_DAT, RSVD1, RSVD2, RSVD3, 0x6018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
 	PINGROUP(dap2_fs_pw1, I2S2_LRCK, RSVD1, RSVD2, RSVD3, 0x6040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
 	PINGROUP(dap2_clk_pv6, I2S2_SCLK, RSVD1, RSVD2, RSVD3, 0x6048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
-	PINGROUP(dap2_din_pv7, I2S2_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
-	PINGROUP(dap2_dout_pw0, I2S2_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+	PINGROUP(dap2_din_pw0, I2S2_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+	PINGROUP(dap2_dout_pv7, I2S2_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
 	PINGROUP(pwm10_pv1, GP_PWM10, SDMMC1_CD, I2S7_LRCK, RSVD3, 0x6060, 0, Y, 5, 7, 6, 8, -1, 10, 11),
 	PINGROUP(soc_gpio170_pu0, RSVD0, I2S7_SDATA_IN, CCLA_LA_TRIGGER_MUX, RSVD3, 0x6068, 0, Y, 5, 7, 6, 8, -1, 10, 11),
 	PINGROUP(soc_gpio171_pu1, RSVD0, SPI4_SCK, RSVD2, RSVD3, 0x6070, 0, Y, 5, 7, 6, 8, -1, 10, 11),

Signature · 1 line

2.17.1

Jon Hunter

maintainer Reviewed-by Tested-by on v2 2/2

2026-07-30 09:18 UTC #2 lore raw

Re: [RESEND V2 2/2] pinctrl: tegra264: fix DAP2 DIN/DOUT pin assignment

Quoted 81 lines · Prathamesh Shete

Fixes c98506206912 ("pinctrl: tegra: Add Tegra264 pinmux driver")

Signed-off-by Prathamesh Shete <[email protected]>

---
Changes in v2:
- Rename the pin groups to dap2_din_pw0 and dap2_dout_pv7 and assign the correct mux function to each pad in a single driver patch.

---
  drivers/pinctrl/tegra/pinctrl-tegra264.c | 24 ++++++++++++------------
  1 file changed, 12 insertions(+), 12 deletions(-)

drivers/pinctrl/tegra/pinctrl-tegra264.c +10 ~~-10~~

index be64fba34dce..f8afb0bdb68a 100644
@@ -96,8 +96,8 @@ enum {
  	TEGRA_PIN_UART4_RTS_N_PV4,
  	TEGRA_PIN_UART4_CTS_N_PV5,
  	TEGRA_PIN_DAP2_CLK_PV6,
-	TEGRA_PIN_DAP2_DIN_PV7,
-	TEGRA_PIN_DAP2_DOUT_PW0,
+	TEGRA_PIN_DAP2_DIN_PW0,
+	TEGRA_PIN_DAP2_DOUT_PV7,
  	TEGRA_PIN_DAP2_FS_PW1,
  	TEGRA_PIN_GEN1_I2C_SCL_PW2,
  	TEGRA_PIN_GEN1_I2C_SDA_PW3,

@@ -329,8 +329,8 @@ static const struct pinctrl_pin_desc tegra264_main_pins[] = {
  	PINCTRL_PIN(TEGRA_PIN_UART4_RTS_N_PV4, "UART4_RTS_N_PV4"),
  	PINCTRL_PIN(TEGRA_PIN_UART4_CTS_N_PV5, "UART4_CTS_N_PV5"),
  	PINCTRL_PIN(TEGRA_PIN_DAP2_CLK_PV6, "DAP2_CLK_PV6"),
-	PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PV7, "DAP2_DIN_PV7"),
-	PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PW0, "DAP2_DOUT_PW0"),
+	PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PW0, "DAP2_DIN_PW0"),
+	PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PV7, "DAP2_DOUT_PV7"),
  	PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PW1, "DAP2_FS_PW1"),
  	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PW2, "GEN1_I2C_SCL_PW2"),
  	PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PW3, "GEN1_I2C_SDA_PW3"),

@@ -827,12 +827,12 @@ static const unsigned int dap2_clk_pv6_pins[] = {
  	TEGRA_PIN_DAP2_CLK_PV6,
  };
 
-static const unsigned int dap2_din_pv7_pins[] = {
-	TEGRA_PIN_DAP2_DIN_PV7,
+static const unsigned int dap2_din_pw0_pins[] = {
+	TEGRA_PIN_DAP2_DIN_PW0,
  };
 
-static const unsigned int dap2_dout_pw0_pins[] = {
-	TEGRA_PIN_DAP2_DOUT_PW0,
+static const unsigned int dap2_dout_pv7_pins[] = {
+	TEGRA_PIN_DAP2_DOUT_PV7,
  };
 
  static const unsigned int dap2_fs_pw1_pins[] = {

@@ -1834,8 +1834,8 @@ static const char * const tegra264_functions[] = {
  #define drive_gen1_i2c_sda_pw3 DRV_PINGROUP_ENTRY_Y(0x601c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
  #define drive_dap2_fs_pw1 DRV_PINGROUP_ENTRY_Y(0x6044, 12, 4, 20, 4, -1, -1, -1, -1, 0)
  #define drive_dap2_clk_pv6 DRV_PINGROUP_ENTRY_Y(0x604c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
-#define drive_dap2_din_pv7 DRV_PINGROUP_ENTRY_Y(0x6054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
-#define drive_dap2_dout_pw0 DRV_PINGROUP_ENTRY_Y(0x605c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap2_din_pw0 DRV_PINGROUP_ENTRY_Y(0x6054, 12, 4, 20, 4, -1, -1, -1, -1, 0)
+#define drive_dap2_dout_pv7 DRV_PINGROUP_ENTRY_Y(0x605c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
  #define drive_pwm10_pv1 DRV_PINGROUP_ENTRY_Y(0x6064, 12, 4, 20, 4, -1, -1, -1, -1, 0)
  #define drive_soc_gpio170_pu0 DRV_PINGROUP_ENTRY_Y(0x606c, 12, 4, 20, 4, -1, -1, -1, -1, 0)
  #define drive_soc_gpio171_pu1 DRV_PINGROUP_ENTRY_Y(0x6074, 12, 4, 20, 4, -1, -1, -1, -1, 0)

drivers/pinctrl/tegra/pinctrl-tegra264.c static const struct tegra_pingroup tegra264_main_groups[] = { · line 2058

Quoted 10 lines

drivers/pinctrl/tegra/pinctrl-tegra264.c +2 -2

@@ -2051,8 +2051,8 @@ static const struct tegra_pingroup tegra264_main_groups[] = {
  	PINGROUP(gen1_i2c_sda_pw3, I2C1_DAT, RSVD1, RSVD2, RSVD3, 0x6018, 0, Y, 5, 7, 6, 8, -1, 10, 11),
  	PINGROUP(dap2_fs_pw1, I2S2_LRCK, RSVD1, RSVD2, RSVD3, 0x6040, 0, Y, 5, 7, 6, 8, -1, 10, 11),
  	PINGROUP(dap2_clk_pv6, I2S2_SCLK, RSVD1, RSVD2, RSVD3, 0x6048, 0, Y, 5, 7, 6, 8, -1, 10, 11),
-	PINGROUP(dap2_din_pv7, I2S2_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
-	PINGROUP(dap2_dout_pw0, I2S2_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+	PINGROUP(dap2_din_pw0, I2S2_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x6050, 0, Y, 5, 7, 6, 8, -1, 10, 11),
+	PINGROUP(dap2_dout_pv7, I2S2_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x6058, 0, Y, 5, 7, 6, 8, -1, 10, 11),
  	PINGROUP(pwm10_pv1, GP_PWM10, SDMMC1_CD, I2S7_LRCK, RSVD3, 0x6060, 0, Y, 5, 7, 6, 8, -1, 10, 11),
  	PINGROUP(soc_gpio170_pu0, RSVD0, I2S7_SDATA_IN, CCLA_LA_TRIGGER_MUX, RSVD3, 0x6068, 0, Y, 5, 7, 6, 8, -1, 10, 11),
  	PINGROUP(soc_gpio171_pu1, RSVD0, SPI4_SCK, RSVD2, RSVD3, 0x6070, 0, Y, 5, 7, 6, 8, -1, 10, 11),

Reviewed-by Jon Hunter <[email protected]>

Tested-by Jon Hunter <[email protected]>

Thanks!
Jon

Signature · 1 line

nvpublic

Thierry Reding

maintainer Acked-by on v2 2/2

2026-07-31 08:06 UTC #3 lore raw

Re: [RESEND V2 2/2] pinctrl: tegra264: fix DAP2 DIN/DOUT pin assignment

In reply to Prathamesh Shete

Quoted 18 lines · Prathamesh Shete

The dap2_din and dap2_dout pin groups were given swapped ball suffixes:
DAP2_DIN was described as ball PV7 and DAP2_DOUT as ball PW0. On silicon DAP2_DIN is on ball PW0 (mux register 0x6050, drive register 0x6054) and DAP2_DOUT is on ball PV7 (mux register 0x6058, drive register 0x605c), as reflected by the board pinmux.
Because the ball suffixes were swapped, the groups were also assigned the wrong primary mux functions (dap2_din -> I2S2_SDATA_OUT and dap2_dout -> I2S2_SDATA_IN), routing the I2S2 data-in and data-out signals to the wrong pins and breaking DAP2 audio.
Rename the groups to dap2_din_pw0 and dap2_dout_pv7 and give each pad its correct function (dap2_din_pw0 -> I2S2_SDATA_IN, dap2_dout_pv7 -> I2S2_SDATA_OUT). The register offsets are already correct and are left unchanged. This matches the board pinmux.
Fixes c98506206912 ("pinctrl: tegra: Add Tegra264 pinmux driver")
Signed-off-by Prathamesh Shete <[email protected]>

Quoted 7 lines

---
Changes in v2:
- Rename the pin groups to dap2_din_pw0 and dap2_dout_pv7 and assign the correct mux function to each pad in a single driver patch.
---
 drivers/pinctrl/tegra/pinctrl-tegra264.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

Acked-by Thierry Reding <[email protected]>

Linus Walleij

maintainer

2026-08-06 21:48 UTC #4 lore raw

Re: [RESEND V2 2/2] pinctrl: tegra264: fix DAP2 DIN/DOUT pin assignment

In reply to Prathamesh Shete

Quoted 11 lines · Prathamesh Shete

The dap2_din and dap2_dout pin groups were given swapped ball suffixes:
DAP2_DIN was described as ball PV7 and DAP2_DOUT as ball PW0. On silicon DAP2_DIN is on ball PW0 (mux register 0x6050, drive register 0x6054) and DAP2_DOUT is on ball PV7 (mux register 0x6058, drive register 0x605c), as reflected by the board pinmux.
Because the ball suffixes were swapped, the groups were also assigned the wrong primary mux functions (dap2_din -> I2S2_SDATA_OUT and dap2_dout -> I2S2_SDATA_IN), routing the I2S2 data-in and data-out signals to the wrong pins and breaking DAP2 audio.

Quoted 7 lines

Rename the groups to dap2_din_pw0 and dap2_dout_pv7 and give each pad its correct function (dap2_din_pw0 -> I2S2_SDATA_IN, dap2_dout_pv7 -> I2S2_SDATA_OUT). The register offsets are already correct and are left unchanged. This matches the board pinmux.
Fixes c98506206912 ("pinctrl: tegra: Add Tegra264 pinmux driver")
Signed-off-by Prathamesh Shete <[email protected]>

Patch applied!

Yours,
Linus Walleij

[email protected]

AI review

2026-07-27 14:20 UTC #5 lore raw

In reply to Prathamesh Shete

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] The dt-bindings update renames the pins dap2_din_pv7 and dap2_dout_pw0 to dap2_din_pw0 and…

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The dt-bindings update renames the pins dap2_din_pv7 and dap2_dout_pw0 to dap2_din_pw0 and dap2_dout_pv7, but fails to update the corresponding string names in the pinctrl driver, breaking device tree parsing at runtime. --

--- Patch [1]: [RESEND V2 1/2] dt-bindings: pinctrl: tegra264: fix DAP2 DIN/DOUT pin names --- commit 467f2064204e431cbe2d5bcbda6fbbde377327d8
Author: Prathamesh Shete <[email protected]>

dt-bindings: pinctrl: tegra264: fix DAP2 DIN/DOUT pin names

This commit corrects the ball suffixes for the DAP2 DIN and DOUT pins in the Tegra264 pinctrl dt-bindings. It renames dap2_din_pv7 and dap2_dout_pw0 to dap2_din_pw0 and dap2_dout_pv7 in both the pin properties and drive groups.

Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml patternProperties: · line 47

Quoted 10 lines

Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml +1 -1

index c40409d3263c2..01db762e82bc0 100644
@@ -44,7 +44,7 @@ patternProperties:
                     soc_gpio173_pu3, soc_gpio174_pu4, soc_gpio175_pu5,
                     soc_gpio176_pu6, soc_gpio177_pu7, soc_gpio178_pv0,
                     pwm10_pv1, uart4_tx_pv2, uart4_rx_pv3, uart4_rts_n_pv4,
-                    uart4_cts_n_pv5, dap2_clk_pv6, dap2_din_pv7, dap2_dout_pw0,
+                    uart4_cts_n_pv5, dap2_clk_pv6, dap2_din_pw0, dap2_dout_pv7,

[Severity: High]
Does this change break device tree parsing at runtime?

While the binding is updated to enforce the correct pin names, it appears the corresponding pinctrl driver was not updated to match.

Looking at tegra264_main_groups() in drivers/pinctrl/tegra/pinctrl-tegra264.c, the driver still registers the pin groups using the old names:

    PINGROUP(dap2_din_pv7, I2S2_SDATA_OUT, RSVD1, RSVD2, RSVD3, 0x6050, ...
    PINGROUP(dap2_dout_pw0, I2S2_SDATA_IN, RSVD1, RSVD2, RSVD3, 0x6058, ...

Because the binding now requires dap2_din_pw0 and dap2_dout_pv7, device trees adhering to the new binding will fail to match the driver's string identifiers.

Will this cause the pinctrl core to fail to configure the DAP2 interface because it cannot find the updated names in the driver?

Signature · 1 line

Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1

Jon Hunter

maintainer Reviewed-by on v2 1/2

2026-07-30 09:17 UTC #6 lore raw

In reply to Prathamesh Shete

Quoted 25 lines · Prathamesh Shete

Fixes 30a9d5162f25 ("dt-bindings: pinctrl: Document Tegra264 pin controllers")

Signed-off-by Prathamesh Shete <[email protected]>

---
  .../bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml       | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml +1 -1

index c40409d3263c..01db762e82bc 100644
@@ -44,7 +44,7 @@ patternProperties:
                      soc_gpio173_pu3, soc_gpio174_pu4, soc_gpio175_pu5,
                      soc_gpio176_pu6, soc_gpio177_pu7, soc_gpio178_pv0,
                      pwm10_pv1, uart4_tx_pv2, uart4_rx_pv3, uart4_rts_n_pv4,
-                    uart4_cts_n_pv5, dap2_clk_pv6, dap2_din_pv7, dap2_dout_pw0,
+                    uart4_cts_n_pv5, dap2_clk_pv6, dap2_din_pw0, dap2_dout_pv7,
                      dap2_fs_pw1, gen1_i2c_scl_pw2, gen1_i2c_sda_pw3,
                      gen0_i2c_scl_pw4, gen0_i2c_sda_pw5, pwr_i2c_scl_pw6,
                      pwr_i2c_sda_pw7, soc_gpio138_pp0, soc_gpio139_pp1,

Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml patternProperties: · line 118

Quoted 10 lines

Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml +2 -2

@@ -111,8 +111,8 @@ patternProperties:
                      drive_soc_gpio351_ps1, drive_gen0_i2c_scl_pw4,
                      drive_gen0_i2c_sda_pw5, drive_gen1_i2c_scl_pw2,
                      drive_gen1_i2c_sda_pw3, drive_dap2_fs_pw1,
-                    drive_dap2_clk_pv6, drive_dap2_din_pv7,
-                    drive_dap2_dout_pw0, drive_pwm10_pv1,
+                    drive_dap2_clk_pv6, drive_dap2_din_pw0,
+                    drive_dap2_dout_pv7, drive_pwm10_pv1,
                      drive_soc_gpio170_pu0, drive_soc_gpio171_pu1,
                      drive_soc_gpio172_pu2, drive_soc_gpio173_pu3,
                      drive_soc_gpio174_pu4, drive_soc_gpio175_pu5,

Reviewed-by Jon Hunter <[email protected]>

Thanks!
Jon

Signature · 1 line

nvpublic

Thierry Reding

maintainer Acked-by on v2 1/2

2026-07-31 08:06 UTC #7 lore raw

In reply to Prathamesh Shete

Quoted 10 lines · Prathamesh Shete

The DAP2_DIN and DAP2_DOUT pins were listed with swapped ball suffixes:
DAP2_DIN as PV7 and DAP2_DOUT as PW0. On silicon DAP2_DIN is on ball PW0 and DAP2_DOUT is on ball PV7. Correct the pin and drive group names to dap2_din_pw0 and dap2_dout_pv7.
Fixes 30a9d5162f25 ("dt-bindings: pinctrl: Document Tegra264 pin controllers")
Signed-off-by Prathamesh Shete <[email protected]>
---
 .../bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml       | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Acked-by Thierry Reding <[email protected]>

Krzysztof Kozlowski

2026-08-04 07:37 UTC #8 lore raw

In reply to Prathamesh Shete

Quoted 7 lines · Prathamesh Shete

The DAP2_DIN and DAP2_DOUT pins were listed with swapped ball suffixes:
DAP2_DIN as PV7 and DAP2_DOUT as PW0. On silicon DAP2_DIN is on ball PW0 and DAP2_DOUT is on ball PV7. Correct the pin and drive group names to dap2_din_pw0 and dap2_dout_pv7.
Fixes 30a9d5162f25 ("dt-bindings: pinctrl: Document Tegra264 pin controllers")
Signed-off-by Prathamesh Shete <[email protected]>

This will break the users and only for fixing naming style? Are you sure it is worth beraking ABI?

Best regards,
Krzysztof

Thierry Reding

maintainer

2026-08-05 07:27 UTC #9 lore raw

Quoted 11 lines · Krzysztof Kozlowski

Quoted 7 lines · Prathamesh Shete
The DAP2_DIN and DAP2_DOUT pins were listed with swapped ball suffixes:
DAP2_DIN as PV7 and DAP2_DOUT as PW0. On silicon DAP2_DIN is on ball PW0 and DAP2_DOUT is on ball PV7. Correct the pin and drive group names to dap2_din_pw0 and dap2_dout_pv7.
Fixes 30a9d5162f25 ("dt-bindings: pinctrl: Document Tegra264 pin controllers")
Signed-off-by Prathamesh Shete <[email protected]>
This will break the users and only for fixing naming style? Are you sure it is worth beraking ABI?

This isn't just fixing the naming style, it's fixing the name of the pins as they are referred to in a number of different places. With the wrong ball suffix people might easily be confused as to what pin they should be using.

So yes, I'd consider this a bug fix and worth an ABI break. The ABI break is theoretical, too. This pin is currently not listed in any upstream DTS files and all of the downstream ones I've seen use the corrected suffix already.

Thierry

Krzysztof Kozlowski

Acked-by on v2 1/2

2026-08-05 07:45 UTC #10 lore raw

In reply to Prathamesh Shete

Quoted 8 lines · Prathamesh Shete

The DAP2_DIN and DAP2_DOUT pins were listed with swapped ball suffixes:
DAP2_DIN as PV7 and DAP2_DOUT as PW0. On silicon DAP2_DIN is on ball PW0 and DAP2_DOUT is on ball PV7. Correct the pin and drive group names to dap2_din_pw0 and dap2_dout_pv7.
Fixes 30a9d5162f25 ("dt-bindings: pinctrl: Document Tegra264 pin controllers")
Signed-off-by Prathamesh Shete <[email protected]>
---

Acked-by Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof

Linus Walleij

maintainer

2026-08-06 21:47 UTC #11 lore raw

In reply to Prathamesh Shete

Quoted 7 lines · Prathamesh Shete

The DAP2_DIN and DAP2_DOUT pins were listed with swapped ball suffixes:
DAP2_DIN as PV7 and DAP2_DOUT as PW0. On silicon DAP2_DIN is on ball PW0 and DAP2_DOUT is on ball PV7. Correct the pin and drive group names to dap2_din_pw0 and dap2_dout_pv7.
Fixes 30a9d5162f25 ("dt-bindings: pinctrl: Document Tegra264 pin controllers")
Signed-off-by Prathamesh Shete <[email protected]>

Patch applied!

Yours,
Linus Walleij