ASoC: codec drivers: sort the reg_defaults tables

PATCH In review Peter Ujfalusi 3 participants 7 messages Aug 5 – Aug 10

Subsystems (4)

Stable branch Sound ASoC MAX9860 mono audio voice codec driver

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Peter Ujfalusi

author

2026-08-05 12:28 UTC #0 lore raw

cover ASoC: codec drivers: sort the reg_defaults tables

reg_defaults must be sorted by ascending register address, since regcache_lookup_reg() locates entries in it with bsearch(). When a table is not sorted, bsearch() cannot find the entries which follow a descending step, so regcache_reg_needs_sync() falls back to reporting that a sync is needed for them. Those registers are then written to the device on every regcache_sync() even when they were never touched.

See commit fd80df352ba1 ("regcache: Add support for sorting defaults arrays") for the same problem in a different context.

The series is based on broonie/for-linus (05eebef3c7b2).

Affected tables:
ml26124_reg 1 of 79 entries unreachable
cx2072x_reg_defaults 75 of 132 entries unreachable
max9860_reg_defaults 1 of 14 entries unreachable
stih407_sas_reg_defaults 1 of 2 entries unreachable

Peter Ujfalusi (4):
ASoC: ml26124: sort the register default table
ASoC: cx2072x: sort the register default table
ASoC: max9860: sort the register default table
ASoC: sti-sas: sort the register default table

 sound/soc/codecs/cx2072x.c | 122 ++++++++++++++++++-------------------
 sound/soc/codecs/max9860.c |   2 +-
 sound/soc/codecs/ml26124.c |   4 +-
 sound/soc/codecs/sti-sas.c |   2 +-
 4 files changed, 66 insertions(+), 64 deletions(-)

Signature · 1 line

2.55.0

Peter Ujfalusi

author

2026-08-05 12:28 UTC #1 lore raw

PATCH 1/4 ASoC: ml26124: sort the register default table

reg_defaults must be sorted by ascending register address, as regcache_lookup_reg() locates entries in it with bsearch(). See commit fd80df352ba1 ("regcache: Add support for sorting defaults arrays").

The Mic Select Control register (0xe8) is listed in the analog path control group, between 0x5a and 0x60, which makes it unreachable. regcache_reg_needs_sync() then cannot compare it against its default and reports that a sync is needed, so it is written to the device on every regcache_sync() even when it was never touched.

Move the entry to the end of the table, where it belongs by address.

Fixes d808fe9f3e7f ("ASoC: Add LAPIS Semiconductor ML26124 driver")

Cc [email protected]

Signed-off-by Peter Ujfalusi <[email protected]>

---
 sound/soc/codecs/ml26124.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

sound/soc/codecs/ml26124.c +3 -1

index 8a14626d43ff..7209b47c2029 100644
@@ -224,7 +224,6 @@ static const struct reg_default ml26124_reg[] = {
 	/* Analog Path Control Register */
 	{0x54, 0x00},	/* Speaker AMP Output Control */
 	{0x5a, 0x00},	/* Mic IF Control */
-	{0xe8, 0x01},	/* Mic Select Control */
 
 	/* Audio Interface Control Register */
 	{0x60, 0x00},	/* SAI-Trans Control */

@@ -287,6 +286,9 @@ static const struct reg_default ml26124_reg[] = {
 	{0xd0, 0x01},	/* VIDEO AMP Gain Control */
 	{0xd2, 0x01},	/* VIDEO AMP Setup 1 */
 	{0xd4, 0x01},	/* VIDEO AMP Control2 */
+
+	/* Analog Path Control Register */
+	{0xe8, 0x01},	/* Mic Select Control */
 };
 
 /* Get sampling rate value of sampling rate setting register (0x0) */

Signature · 1 line

2.55.0

Peter Ujfalusi

author

2026-08-05 12:28 UTC #2 lore raw

PATCH 2/4 ASoC: cx2072x: sort the register default table

In reply to Peter Ujfalusi

The table is grouped by function rather than by address: for every node the amplifier gain registers (0x41c0, 0x45c0, ...) are listed before the power state and stream format registers of the same node (0x4014, 0x4414, ...). This leaves 75 of the 132 entries unreachable. regcache_reg_needs_sync() then cannot compare them against their default and reports that a sync is needed, so they are written to the device on every regcache_sync() even when they were never touched.

Sort the table by register address.

Fixes a497a4363706 ("ASoC: Add support for Conexant CX2072X CODEC")

Cc [email protected]

Signed-off-by Peter Ujfalusi <[email protected]>

---
 sound/soc/codecs/cx2072x.c | 122 ++++++++++++++++++-------------------
 1 file changed, 61 insertions(+), 61 deletions(-)

sound/soc/codecs/cx2072x.c +61 ~~-61~~

index 83c6cbd40804..ffd6a5119f5e 100644
@@ -96,51 +96,60 @@ static const struct reg_default cx2072x_reg_defaults[] = {
 	{ CX2072X_GPIO_WAKE, 0x00000000 },
 	{ CX2072X_GPIO_UM_ENABLE, 0x00000000 },
 	{ CX2072X_GPIO_STICKY_MASK, 0x00000000 },
-	{ CX2072X_DAC1_CONVERTER_FORMAT, 0x00000031 },
-	{ CX2072X_DAC1_AMP_GAIN_RIGHT, 0x0000004a },
-	{ CX2072X_DAC1_AMP_GAIN_LEFT, 0x0000004a },
 	{ CX2072X_DAC1_POWER_STATE, 0x00000433 },
 	{ CX2072X_DAC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
 	{ CX2072X_DAC1_EAPD_ENABLE, 0x00000000 },
-	{ CX2072X_DAC2_CONVERTER_FORMAT, 0x00000031 },
-	{ CX2072X_DAC2_AMP_GAIN_RIGHT, 0x0000004a },
-	{ CX2072X_DAC2_AMP_GAIN_LEFT, 0x0000004a },
+	{ CX2072X_DAC1_AMP_GAIN_RIGHT, 0x0000004a },
+	{ CX2072X_DAC1_AMP_GAIN_LEFT, 0x0000004a },
+	{ CX2072X_DAC1_CONVERTER_FORMAT, 0x00000031 },
 	{ CX2072X_DAC2_POWER_STATE, 0x00000433 },
 	{ CX2072X_DAC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
-	{ CX2072X_ADC1_CONVERTER_FORMAT, 0x00000031 },
+	{ CX2072X_DAC2_AMP_GAIN_RIGHT, 0x0000004a },
+	{ CX2072X_DAC2_AMP_GAIN_LEFT, 0x0000004a },
+	{ CX2072X_DAC2_CONVERTER_FORMAT, 0x00000031 },
+	{ CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 0x00000000 },
+	{ CX2072X_ADC1_POWER_STATE, 0x00000433 },
+	{ CX2072X_ADC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
 	{ CX2072X_ADC1_AMP_GAIN_RIGHT_0, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_LEFT_0, 0x0000004a },
 	{ CX2072X_ADC1_AMP_GAIN_RIGHT_1, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_LEFT_1, 0x0000004a },
 	{ CX2072X_ADC1_AMP_GAIN_RIGHT_2, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_LEFT_2, 0x0000004a },
 	{ CX2072X_ADC1_AMP_GAIN_RIGHT_3, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_LEFT_3, 0x0000004a },
 	{ CX2072X_ADC1_AMP_GAIN_RIGHT_4, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_LEFT_4, 0x0000004a },
 	{ CX2072X_ADC1_AMP_GAIN_RIGHT_5, 0x0000004a },
-	{ CX2072X_ADC1_AMP_GAIN_LEFT_5, 0x0000004a },
 	{ CX2072X_ADC1_AMP_GAIN_RIGHT_6, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_LEFT_0, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_LEFT_1, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_LEFT_2, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_LEFT_3, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_LEFT_4, 0x0000004a },
+	{ CX2072X_ADC1_AMP_GAIN_LEFT_5, 0x0000004a },
 	{ CX2072X_ADC1_AMP_GAIN_LEFT_6, 0x0000004a },
-	{ CX2072X_ADC1_CONNECTION_SELECT_CONTROL, 0x00000000 },
-	{ CX2072X_ADC1_POWER_STATE, 0x00000433 },
-	{ CX2072X_ADC1_CONVERTER_STREAM_CHANNEL, 0x00000000 },
-	{ CX2072X_ADC2_CONVERTER_FORMAT, 0x00000031 },
+	{ CX2072X_ADC1_CONVERTER_FORMAT, 0x00000031 },
+	{ CX2072X_ADC2_CONNECTION_SELECT_CONTROL, 0x00000000 },
+	{ CX2072X_ADC2_POWER_STATE, 0x00000433 },
+	{ CX2072X_ADC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
 	{ CX2072X_ADC2_AMP_GAIN_RIGHT_0, 0x0000004a },
-	{ CX2072X_ADC2_AMP_GAIN_LEFT_0, 0x0000004a },
 	{ CX2072X_ADC2_AMP_GAIN_RIGHT_1, 0x0000004a },
-	{ CX2072X_ADC2_AMP_GAIN_LEFT_1, 0x0000004a },
 	{ CX2072X_ADC2_AMP_GAIN_RIGHT_2, 0x0000004a },
+	{ CX2072X_ADC2_AMP_GAIN_LEFT_0, 0x0000004a },
+	{ CX2072X_ADC2_AMP_GAIN_LEFT_1, 0x0000004a },
 	{ CX2072X_ADC2_AMP_GAIN_LEFT_2, 0x0000004a },
-	{ CX2072X_ADC2_CONNECTION_SELECT_CONTROL, 0x00000000 },
-	{ CX2072X_ADC2_POWER_STATE, 0x00000433 },
-	{ CX2072X_ADC2_CONVERTER_STREAM_CHANNEL, 0x00000000 },
+	{ CX2072X_ADC2_CONVERTER_FORMAT, 0x00000031 },
+	{ CX2072X_MIXER_POWER_STATE, 0x00000433 },
+	{ CX2072X_MIXER_GAIN_RIGHT_0, 0x0000004a },
+	{ CX2072X_MIXER_GAIN_RIGHT_1, 0x0000004a },
+	{ CX2072X_MIXER_GAIN_LEFT_0, 0x0000004a },
+	{ CX2072X_MIXER_GAIN_LEFT_1, 0x0000004a },
 	{ CX2072X_PORTA_CONNECTION_SELECT_CTRL, 0x00000000 },
 	{ CX2072X_PORTA_POWER_STATE, 0x00000433 },
 	{ CX2072X_PORTA_PIN_CTRL, 0x000000c0 },
 	{ CX2072X_PORTA_UNSOLICITED_RESPONSE, 0x00000000 },
 	{ CX2072X_PORTA_PIN_SENSE, 0x00000000 },
 	{ CX2072X_PORTA_EAPD_BTL, 0x00000002 },
+	{ CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0x00000000 },
+	{ CX2072X_PORTG_POWER_STATE, 0x00000433 },
+	{ CX2072X_PORTG_PIN_CTRL, 0x00000040 },
+	{ CX2072X_PORTG_EAPD_BTL, 0x00000002 },
 	{ CX2072X_PORTB_POWER_STATE, 0x00000433 },
 	{ CX2072X_PORTB_PIN_CTRL, 0x00000000 },
 	{ CX2072X_PORTB_UNSOLICITED_RESPONSE, 0x00000000 },

@@ -148,43 +157,16 @@ static const struct reg_default cx2072x_reg_defaults[] = {
 	{ CX2072X_PORTB_EAPD_BTL, 0x00000002 },
 	{ CX2072X_PORTB_GAIN_RIGHT, 0x00000000 },
 	{ CX2072X_PORTB_GAIN_LEFT, 0x00000000 },
-	{ CX2072X_PORTC_POWER_STATE, 0x00000433 },
-	{ CX2072X_PORTC_PIN_CTRL, 0x00000000 },
-	{ CX2072X_PORTC_GAIN_RIGHT, 0x00000000 },
-	{ CX2072X_PORTC_GAIN_LEFT, 0x00000000 },
 	{ CX2072X_PORTD_POWER_STATE, 0x00000433 },
 	{ CX2072X_PORTD_PIN_CTRL, 0x00000020 },
 	{ CX2072X_PORTD_UNSOLICITED_RESPONSE, 0x00000000 },
 	{ CX2072X_PORTD_PIN_SENSE, 0x00000000 },
 	{ CX2072X_PORTD_GAIN_RIGHT, 0x00000000 },
 	{ CX2072X_PORTD_GAIN_LEFT, 0x00000000 },
-	{ CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0x00000000 },
-	{ CX2072X_PORTE_POWER_STATE, 0x00000433 },
-	{ CX2072X_PORTE_PIN_CTRL, 0x00000040 },
-	{ CX2072X_PORTE_UNSOLICITED_RESPONSE, 0x00000000 },
-	{ CX2072X_PORTE_PIN_SENSE, 0x00000000 },
-	{ CX2072X_PORTE_EAPD_BTL, 0x00000002 },
-	{ CX2072X_PORTE_GAIN_RIGHT, 0x00000000 },
-	{ CX2072X_PORTE_GAIN_LEFT, 0x00000000 },
-	{ CX2072X_PORTF_POWER_STATE, 0x00000433 },
-	{ CX2072X_PORTF_PIN_CTRL, 0x00000000 },
-	{ CX2072X_PORTF_UNSOLICITED_RESPONSE, 0x00000000 },
-	{ CX2072X_PORTF_PIN_SENSE, 0x00000000 },
-	{ CX2072X_PORTF_GAIN_RIGHT, 0x00000000 },
-	{ CX2072X_PORTF_GAIN_LEFT, 0x00000000 },
-	{ CX2072X_PORTG_POWER_STATE, 0x00000433 },
-	{ CX2072X_PORTG_PIN_CTRL, 0x00000040 },
-	{ CX2072X_PORTG_CONNECTION_SELECT_CTRL, 0x00000000 },
-	{ CX2072X_PORTG_EAPD_BTL, 0x00000002 },
-	{ CX2072X_PORTM_POWER_STATE, 0x00000433 },
-	{ CX2072X_PORTM_PIN_CTRL, 0x00000000 },
-	{ CX2072X_PORTM_CONNECTION_SELECT_CTRL, 0x00000000 },
-	{ CX2072X_PORTM_EAPD_BTL, 0x00000002 },
-	{ CX2072X_MIXER_POWER_STATE, 0x00000433 },
-	{ CX2072X_MIXER_GAIN_RIGHT_0, 0x0000004a },
-	{ CX2072X_MIXER_GAIN_LEFT_0, 0x0000004a },
-	{ CX2072X_MIXER_GAIN_RIGHT_1, 0x0000004a },
-	{ CX2072X_MIXER_GAIN_LEFT_1, 0x0000004a },
+	{ CX2072X_PORTC_POWER_STATE, 0x00000433 },
+	{ CX2072X_PORTC_PIN_CTRL, 0x00000000 },
+	{ CX2072X_PORTC_GAIN_RIGHT, 0x00000000 },
+	{ CX2072X_PORTC_GAIN_LEFT, 0x00000000 },
 	{ CX2072X_SPKR_DRC_ENABLE_STEP, 0x040065a4 },
 	{ CX2072X_SPKR_DRC_CONTROL, 0x007b0024 },
 	{ CX2072X_SPKR_DRC_TEST, 0x00000000 },

@@ -195,12 +177,15 @@ static const struct reg_default cx2072x_reg_defaults[] = {
 	{ CX2072X_I2SPCM_CONTROL3, 0x00000000 },
 	{ CX2072X_I2SPCM_CONTROL4, 0x00000000 },
 	{ CX2072X_I2SPCM_CONTROL5, 0x00000000 },
-	{ CX2072X_I2SPCM_CONTROL6, 0x00000000 },
 	{ CX2072X_UM_INTERRUPT_CRTL_E, 0x00000000 },
+	{ CX2072X_I2SPCM_CONTROL6, 0x00000000 },
+	{ CX2072X_DIGITAL_TEST16, 0x00000021 },
+	{ CX2072X_DIGITAL_TEST17, 0x00000018 },
+	{ CX2072X_DIGITAL_TEST18, 0x00000024 },
+	{ CX2072X_DIGITAL_TEST19, 0x00000001 },
+	{ CX2072X_DIGITAL_TEST20, 0x00000002 },
 	{ CX2072X_CODEC_TEST2, 0x00000000 },
 	{ CX2072X_CODEC_TEST9, 0x00000004 },
-	{ CX2072X_CODEC_TEST20, 0x00000600 },
-	{ CX2072X_CODEC_TEST26, 0x00000208 },
 	{ CX2072X_ANALOG_TEST4, 0x00000000 },
 	{ CX2072X_ANALOG_TEST5, 0x00000000 },
 	{ CX2072X_ANALOG_TEST6, 0x0000059a },

@@ -215,11 +200,26 @@ static const struct reg_default cx2072x_reg_defaults[] = {
 	{ CX2072X_DIGITAL_TEST11, 0x00000000 },
 	{ CX2072X_DIGITAL_TEST12, 0x00000084 },
 	{ CX2072X_DIGITAL_TEST15, 0x00000077 },
-	{ CX2072X_DIGITAL_TEST16, 0x00000021 },
-	{ CX2072X_DIGITAL_TEST17, 0x00000018 },
-	{ CX2072X_DIGITAL_TEST18, 0x00000024 },
-	{ CX2072X_DIGITAL_TEST19, 0x00000001 },
-	{ CX2072X_DIGITAL_TEST20, 0x00000002 },
+	{ CX2072X_CODEC_TEST20, 0x00000600 },
+	{ CX2072X_CODEC_TEST26, 0x00000208 },
+	{ CX2072X_PORTE_CONNECTION_SELECT_CTRL, 0x00000000 },
+	{ CX2072X_PORTE_POWER_STATE, 0x00000433 },
+	{ CX2072X_PORTE_PIN_CTRL, 0x00000040 },
+	{ CX2072X_PORTE_UNSOLICITED_RESPONSE, 0x00000000 },
+	{ CX2072X_PORTE_PIN_SENSE, 0x00000000 },
+	{ CX2072X_PORTE_EAPD_BTL, 0x00000002 },
+	{ CX2072X_PORTE_GAIN_RIGHT, 0x00000000 },
+	{ CX2072X_PORTE_GAIN_LEFT, 0x00000000 },
+	{ CX2072X_PORTF_POWER_STATE, 0x00000433 },
+	{ CX2072X_PORTF_PIN_CTRL, 0x00000000 },
+	{ CX2072X_PORTF_UNSOLICITED_RESPONSE, 0x00000000 },
+	{ CX2072X_PORTF_PIN_SENSE, 0x00000000 },
+	{ CX2072X_PORTF_GAIN_RIGHT, 0x00000000 },
+	{ CX2072X_PORTF_GAIN_LEFT, 0x00000000 },
+	{ CX2072X_PORTM_CONNECTION_SELECT_CTRL, 0x00000000 },
+	{ CX2072X_PORTM_POWER_STATE, 0x00000433 },
+	{ CX2072X_PORTM_PIN_CTRL, 0x00000000 },
+	{ CX2072X_PORTM_EAPD_BTL, 0x00000002 },
 };
 
 /*

Signature · 1 line

2.55.0

Peter Ujfalusi

author

2026-08-05 12:28 UTC #3 lore raw

PATCH 3/4 ASoC: max9860: sort the register default table

In reply to Peter Ujfalusi

MAX9860_PWRMAN (0x10) is listed as the first entry, before MAX9860_INTEN (0x02), which makes MAX9860_INTEN unreachable. regcache_reg_needs_sync() then cannot compare it against its default and reports that a sync is needed, so it is written to the device on every regcache_sync() even when it was never touched.

Sort the table by register address.

Fixes 3b2af7f79968 ("ASoC: max9860: new driver")

Cc [email protected]

Signed-off-by Peter Ujfalusi <[email protected]>

---
 sound/soc/codecs/max9860.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

sound/soc/codecs/max9860.c +1 -1

index 0d7ac37850bb..20e288e38669 100644
@@ -48,7 +48,6 @@ static int max9860_dvddio_event(struct notifier_block *nb,
 }
 
 static const struct reg_default max9860_reg_defaults[] = {
-	{ MAX9860_PWRMAN,       0x00 },
 	{ MAX9860_INTEN,        0x00 },
 	{ MAX9860_SYSCLK,       0x00 },
 	{ MAX9860_AUDIOCLKHIGH, 0x00 },

@@ -62,6 +61,7 @@ static const struct reg_default max9860_reg_defaults[] = {
 	{ MAX9860_MICGAIN,      0x00 },
 	{ MAX9860_MICADC,       0x00 },
 	{ MAX9860_NOISEGATE,    0x00 },
+	{ MAX9860_PWRMAN,       0x00 },
 };
 
 static bool max9860_readable(struct device *dev, unsigned int reg)

Signature · 1 line

2.55.0

Peter Ujfalusi

author

2026-08-05 12:28 UTC #4 lore raw

PATCH 4/4 ASoC: sti-sas: sort the register default table

In reply to Peter Ujfalusi

STIH407_AUDIO_DAC_CTRL (0xa8) is listed before STIH407_AUDIO_GLUE_CTRL (0xa4), which makes the latter unreachable. regcache_reg_needs_sync() then cannot compare it against its default and reports that a sync is needed, so it is written to the device on every regcache_sync() even when it was never touched.

Sort the table by register address.

Fixes 165a57a3df02 ("ASoC: sti-sas: clean legacy in sti-sas")

Cc [email protected]

Signed-off-by Peter Ujfalusi <[email protected]>

---
 sound/soc/codecs/sti-sas.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

sound/soc/codecs/sti-sas.c +1 -1

index 4ab15be69f3a..b7eaf4795d8b 100644
@@ -44,8 +44,8 @@ enum {
 };
 
 static const struct reg_default stih407_sas_reg_defaults[] = {
-	{ STIH407_AUDIO_DAC_CTRL, 0x000000000 },
 	{ STIH407_AUDIO_GLUE_CTRL, 0x00000040 },
+	{ STIH407_AUDIO_DAC_CTRL, 0x000000000 },
 };
 
 struct sti_dac_audio {

Signature · 1 line

2.55.0

Patrice CHOTARD

Reviewed-by on v1 4/4

2026-08-10 07:24 UTC #5 lore raw

Re: [PATCH 4/4] ASoC: sti-sas: sort the register default table

Quoted 24 lines · Peter Ujfalusi

reg_defaults must be sorted by ascending register address, as regcache_lookup_reg() locates entries in it with bsearch(). See commit fd80df352ba1 ("regcache: Add support for sorting defaults arrays").
STIH407_AUDIO_DAC_CTRL (0xa8) is listed before STIH407_AUDIO_GLUE_CTRL (0xa4), which makes the latter unreachable. regcache_reg_needs_sync() then cannot compare it against its default and reports that a sync is needed, so it is written to the device on every regcache_sync() even when it was never touched.
Sort the table by register address.
Fixes 165a57a3df02 ("ASoC: sti-sas: clean legacy in sti-sas")
Cc [email protected]
Signed-off-by Peter Ujfalusi <[email protected]>
---
 sound/soc/codecs/sti-sas.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
sound/soc/codecs/sti-sas.c +0 -0
index 4ab15be69f3a..b7eaf4795d8b 100644

sound/soc/codecs/sti-sas.c enum { · line 51

Quoted 9 lines

sound/soc/codecs/sti-sas.c +1 -1

@@ -44,8 +44,8 @@ enum {
 };
 
 static const struct reg_default stih407_sas_reg_defaults[] = {
-	{ STIH407_AUDIO_DAC_CTRL, 0x000000000 },
 	{ STIH407_AUDIO_GLUE_CTRL, 0x00000040 },
+	{ STIH407_AUDIO_DAC_CTRL, 0x000000000 },
 };
 
 struct sti_dac_audio {

Hi Peter

Reviewed-by Patrice Chotard <[email protected]>

Thanks
Patrice

Mark Brown

maintainer

2026-08-08 12:49 UTC #6 lore raw

In reply to Peter Ujfalusi

Quoted 10 lines · Peter Ujfalusi

ASoC: codec drivers: sort the reg_defaults tables
reg_defaults must be sorted by ascending register address, since regcache_lookup_reg() locates entries in it with bsearch(). When a table is not sorted, bsearch() cannot find the entries which follow a descending step, so regcache_reg_needs_sync() falls back to reporting that a sync is needed for them. Those registers are then written to the device on every regcache_sync() even when they were never touched.
[...]

Applied to

https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-7.3

Thanks!

[1/4] ASoC: ml26124: sort the register default table

      https://git.kernel.org/broonie/sound/c/d4d0e6e2355a
[2/4] ASoC: cx2072x: sort the register default table
      https://git.kernel.org/broonie/sound/c/b927853f7007
[3/4] ASoC: max9860: sort the register default table
      https://git.kernel.org/broonie/sound/c/5c4cf173b7eb
[4/4] ASoC: sti-sas: sort the register default table
      https://git.kernel.org/broonie/sound/c/bbd73fb224ca

All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

Thanks,
Mark