arm64: dts: qcom: clean up PCI function nodes

While working on upstream support for the Toshiba TC9564 SoC I learned that its PCIe endpoint function nodes included the device_type property, indicating each is a "pci" device. Herve Codina pointed out that this is not correct; only a PCI device "that implements a PCI bus" should define that property.

I looked at other upstream devicetree files and I found four other places with this same mistake. (All are for Qualcomm platforms, and all are for platforms using a TC956x SoC.)

This series removes the device_type property where it is defined for a PCI endpoint function.

It also removes the #address-cells, #size-cells, and ranges properties in these cases, with a plan to restore them only when they are known to be needed (to implement pci-ep-bus sub-nodes).

-Alex

Alex Elder (5):
arm64: dts: qcom: qcs6490-rb3gen2: clean up PCI function nodes
arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: clean up PCI
function nodes
arm64: dts: qcom: lemans-evk-ifp-mezzanine: clean up PCI function
nodes
arm64: dts: qcom: monaco-evk: clean up PCI function nodes
arm64: dts: qcom: qcs6490-thundercomm-minipc-g1iot: clean up PCI
function nodes

 .../boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso  |  8 --------
 .../boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso  |  8 --------
 .../qcs6490-rb3gen2-industrial-mezzanine.dtso    | 16 ----------------
 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts     |  8 --------
 .../qcom/qcs6490-thundercomm-minipc-g1iot.dts    |  8 --------
 5 files changed, 48 deletions(-)

base-commit: 064935ef6be39d086f4c40766d2b76181b70b3e1

2.53.0

The TC9564 SoC contains a PCIe switch with three downstream ports. The third downstream port connects to an embedded PCI endpoint, and that endpoint implements two PCI functions.

The devicetree node describing those functions incorrectly includes this property:

    device_type = "pci";

That property should only be used for a PCI device "that implements a PCI bus", but not a PCIe function. So remove the device_type property from the nodes representing the two embedded PCI functions.

Additionally, those properties contain #address-cells, #size-cells, and ranges properties. And although these properties *will* be appropriate for these functions on an RB3gen2, they are not normally used for PCI functions. So remove these properties as well; we'll include them in the commit that actually adds the pci-ep-bus sub-node to each of these PCI function nodes.

---
 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 8 --------
 1 file changed, 8 deletions(-)

index a13315bf0fb07..db6578f7fba51 100644
@@ -956,18 +956,10 @@ pcie@3,0 {
 
 			pcie@0,0 {
 				reg = <0x50000 0x0 0x0 0x0 0x0>;
-				#address-cells = <3>;
-				#size-cells = <2>;
-				device_type = "pci";
-				ranges;
 			};
 
 			pcie@0,1 {
 				reg = <0x50100 0x0 0x0 0x0 0x0>;
-				#address-cells = <3>;
-				#size-cells = <2>;
-				device_type = "pci";
-				ranges;
 			};
 		};
 	};

2.53.0

The qcs6490-rb3gen2-industrial-mezzanine overlay defines two nodes representing TC956x chips, each of which contains a PCIe switch and an embedded endpoint that implements two PCIe functions.

The devicetree nodes erroneously include a "pci" device_type property for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes.

In addition, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove properties as well; they can be added back once they are actually needed/used.

---
 .../qcs6490-rb3gen2-industrial-mezzanine.dtso    | 16 ----------------
 1 file changed, 16 deletions(-)

index 46bb52c667a4d..82c4d47fc2aaa 100644
@@ -132,18 +132,10 @@ pcie@3,0 {
 
 			pcie@0,0 {
 				reg = <0x50000 0x0 0x0 0x0 0x0>;
-				#address-cells = <3>;
-				#size-cells = <2>;
-				device_type = "pci";
-				ranges;
 			};
 
 			pcie@0,1 {
 				reg = <0x50100 0x0 0x0 0x0 0x0>;
-				#address-cells = <3>;
-				#size-cells = <2>;
-				device_type = "pci";
-				ranges;
 			};
 		};
 

@@ -227,18 +219,10 @@ pcie@3,0 {
 
 			pcie@0,0 {
 				reg = <0x50000 0x0 0x0 0x0 0x0>;
-				#address-cells = <3>;
-				#size-cells = <2>;
-				device_type = "pci";
-				ranges;
 			};
 
 			pcie@0,1 {
 				reg = <0x50100 0x0 0x0 0x0 0x0>;
-				#address-cells = <3>;
-				#size-cells = <2>;
-				device_type = "pci";
-				ranges;
 			};
 		};
 	};

2.53.0

The lemans-evk-ifp-mezzanine overlay defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions.

The devicetree nodes erroneously include a "pci" device_type property for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes.

In addition, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove these properties as well; they can be added back once they are actually needed/used.

---
 arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso | 8 --------
 1 file changed, 8 deletions(-)

index 6cfa0bc1440e9..9edb447ee990d 100644
@@ -273,18 +273,10 @@ pcie@3,0 {
 
 			pcie@0,0 {
 				reg = <0x50000 0x0 0x0 0x0 0x0>;
-				#address-cells = <3>;
-				#size-cells = <2>;
-				device_type = "pci";
-				ranges;
 			};
 
 			pcie@0,1 {
 				reg = <0x50100 0x0 0x0 0x0 0x0>;
-				#address-cells = <3>;
-				#size-cells = <2>;
-				device_type = "pci";
-				ranges;
 			};
 		};
 	};

2.53.0

The monaco-evk-ifp-mezzanine overlay defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions.

The devicetree nodes erroneously include a "pci" device_type property for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes.

In addition, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove properties as well; they can be added back once they are actually needed/used.

---
 arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso | 8 --------
 1 file changed, 8 deletions(-)

index ca5bf0fe5ec6e..9b5e911b83210 100644
@@ -119,18 +119,10 @@ pcie@3,0 {
 
 			pcie@0,0 {
 				reg = <0x50000 0x0 0x0 0x0 0x0>;
-				#address-cells = <3>;
-				#size-cells = <2>;
-				device_type = "pci";
-				ranges;
 			};
 
 			pcie@0,1 {
 				reg = <0x50100 0x0 0x0 0x0 0x0>;
-				#address-cells = <3>;
-				#size-cells = <2>;
-				device_type = "pci";
-				ranges;
 			};
 		};
 	};

2.53.0

The Thundercomm AI Mini PC G1 IoT devicetree source file defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions.

The devicetree nodes erroneously include a "pci" device_type property for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes.

In addition, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove properties as well; they can be added back once they are actually needed/used.

---
 .../boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts    | 8 --------
 1 file changed, 8 deletions(-)

index 31bafa2cf51db..3e8d144f57b00 100644
@@ -792,18 +792,10 @@ pcie@3,0 {
 
 			pcie@0,0 {
 				reg = <0x50000 0x0 0x0 0x0 0x0>;
-				#address-cells = <3>;
-				#size-cells = <2>;
-				device_type = "pci";
-				ranges;
 			};
 
 			pcie@0,1 {
 				reg = <0x50100 0x0 0x0 0x0 0x0>;
-				#address-cells = <3>;
-				#size-cells = <2>;
-				device_type = "pci";
-				ranges;
 			};
 		};
 	};

2.53.0

Thanks for cleaning the mess!

- Mani

மணிவண்ணன் சதாசிவம்

For the series:

Konrad