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mtd: spi-nor-ids: Add XMC XM25QH128C

PATCH Superseded Fabio Estevam 2 participants 5 messages Aug 13

Subsystems (3)
Arm (32-bit) Memory technology devices (MTD) Arm Rockchip

v5 of 6 Superseded Latest is v6 →

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Fabio Estevam

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#0 lore raw

PATCH v5 1/4 mtd: spi-nor-ids: Add XMC XM25QH128C

From: Fabio Estevam <[email protected]>

Add the JEDEC ID for the XMC XM25QH128C SPI NOR flash.

This is a 128Mbit device using 64KiB sectors and supporting 4KiB erase, dual read and quad read, matching the other XM25QH128 variants.

Link https://www.xmcwh.com/uploads/435/XM25QH128C.pdf
Cc Vignesh Raghavendra <[email protected]>
Cc Takahiro Kuwano <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>
Reviewed-by Takahiro Kuwano <[email protected]>

---
Changes since v4:
- Added Link and Takahiro's Reviewed-by tags.

 drivers/mtd/spi/spi-nor-ids.c | 1 +
 1 file changed, 1 insertion(+)
drivers/mtd/spi/spi-nor-ids.c +1 -0
index 31a2ba49a87..90aa1025176 100644
@@ -673,6 +673,7 @@ const struct flash_info spi_nor_ids[] = {
 	{ INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+	{ INFO("XM25QH128C", 0x204018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ INFO("XM25QH256C", 0x204019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
 	{ INFO("XM25QU256C", 0x204119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
Signature · 1 line
2.43.0
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#1 lore raw

PATCH v5 2/4 rockchip: rk3399: Remove ROC-PC regulator overrides

From: Fabio Estevam <[email protected]>

The upstream devicetree already describes dc_12v as the output of the MP8859 regulator and drives the USB hub reset through the vcc5v0_host regulator pinctrl state.

Remove the legacy fixed-regulator overrides and rely on the upstream regulator descriptions.

Signed-off-by Fabio Estevam <[email protected]>
Reviewed-by Quentin Schulz <[email protected]>

---
Changes since v4:
- None.

 arch/arm/dts/rk3399-roc-pc-u-boot.dtsi | 24 ------------------------
 1 file changed, 24 deletions(-)
arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +0 -24
index 883d399a06a..a85e9549c83 100644
@@ -10,30 +10,6 @@
 	config {
 		sysreset-gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
 	};
-
-	vcc_hub_en: vcc_hub_en-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&hub_rst>;
-		regulator-name = "vcc_hub_en";
-		regulator-always-on;
-	};
-};
-
-/*
- * should be placed inside mp8859, but not until mp8859 has
- * its own dt-binding.
- */
-&dc_12v {
-	compatible = "regulator-fixed";
-	regulator-name = "dc_12v";
-	regulator-always-on;
-	regulator-boot-on;
-	regulator-min-microvolt = <12000000>;
-	regulator-max-microvolt = <12000000>;
-	vin-supply = <&vcc_vbus_typec0>;
 };
 
 &gpio4 {
Signature · 1 line
2.43.0
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#2 lore raw

PATCH v5 3/4 rockchip: rk3399: Add ROC-PC-PLUS board detection

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

The ROC-RK3399-PC has an MP8859 regulator on I2C7 at address 0x66, while the ROC-RK3399-PC-PLUS does not. Probe for the regulator in SPL and use the result to select the matching devicetree from the U-Boot FIT. Fall back to the original board if the I2C bus cannot be probed.

Build both devicetrees from the existing roc-pc-rk3399_defconfig and enable the XMC SPI NOR driver used by the Plus variant. Set fdtfile from the selected U-Boot devicetree so the matching Linux devicetree is used as well.

Signed-off-by Fabio Estevam <[email protected]>
Reviewed-by Quentin Schulz <[email protected]>

---
Changes since v4:
- Fixed mezzanine build error.

 arch/arm/dts/rk3399-roc-pc-u-boot.dtsi      |  8 ++++
 board/firefly/roc-pc-rk3399/roc-pc-rk3399.c | 42 +++++++++++++++++++++
 configs/roc-pc-rk3399_defconfig             |  3 ++
 doc/board/rockchip/rockchip.rst             |  2 +-
 4 files changed, 54 insertions(+), 1 deletion(-)
arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +8 -0
index a85e9549c83..e7e4a2c8907 100644
@@ -12,6 +12,14 @@
 	};
 };
 
+&i2c7 {
+	bootph-pre-ram;
+};
+
+&i2c7_xfer {
+	bootph-pre-ram;
+};
+
 &gpio4 {
 	bootph-pre-ram;
 };
board/firefly/roc-pc-rk3399/roc-pc-rk3399.c +42 -0

60 lines not on this page · raw message

configs/roc-pc-rk3399_defconfig +3 -0
index 1df5cb03adb..53182dc8251 100644
@@ -26,6 +26,7 @@ CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_MAX_SIZE=0x40000
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_I2C=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0xE0000
 CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y

@@ -37,6 +38,7 @@ CONFIG_CMD_USB=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="rockchip/rk3399-roc-pc rockchip/rk3399-roc-pc-plus"
 CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
 CONFIG_ENV_RELOC_GD_ENV_ADDR=y

@@ -49,6 +51,7 @@ CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
 CONFIG_DM_ETH_PHY=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
doc/board/rockchip/rockchip.rst +1 -1
index de2df3046e2..d9c4b753949 100644
@@ -81,7 +81,7 @@ List of mainline supported Rockchip boards:
      - 96boards RK3399 Ficus (ficus-rk3399)
      - 96boards Rock960 (rock960-rk3399)
      - Firefly-RK3399 (firefly_rk3399)
-     - Firefly ROC-RK3399-PC
+     - Firefly ROC-RK3399-PC/ROC-RK3399-PC-PLUS (roc-pc-rk3399)
      - FriendlyElec NanoPC-T4 (nanopc-t4-rk3399)
      - FriendlyElec NanoPi M4 (nanopi-m4-rk3399)
      - FriendlyElec NanoPi M4B (nanopi-m4b-rk3399)
Signature · 1 line
2.43.0
#3 lore raw

Re: [PATCH v5 3/4] rockchip: rk3399: Add ROC-PC-PLUS board detection

Hi Fabio,

Quoted 77 lines · Fabio Estevam

From: Fabio Estevam <[email protected]>

The ROC-RK3399-PC has an MP8859 regulator on I2C7 at address 0x66, while the ROC-RK3399-PC-PLUS does not. Probe for the regulator in SPL and use the result to select the matching devicetree from the U-Boot FIT. Fall back to the original board if the I2C bus cannot be probed.

Build both devicetrees from the existing roc-pc-rk3399_defconfig and enable the XMC SPI NOR driver used by the Plus variant. Set fdtfile from the selected U-Boot devicetree so the matching Linux devicetree is used as well.

Signed-off-by Fabio Estevam <[email protected]>
Reviewed-by Quentin Schulz <[email protected]>

---
Changes since v4:
- Fixed mezzanine build error.

  arch/arm/dts/rk3399-roc-pc-u-boot.dtsi      |  8 ++++
  board/firefly/roc-pc-rk3399/roc-pc-rk3399.c | 42 +++++++++++++++++++++
  configs/roc-pc-rk3399_defconfig             |  3 ++
  doc/board/rockchip/rockchip.rst             |  2 +-
  4 files changed, 54 insertions(+), 1 deletion(-)
arch/arm/dts/rk3399-roc-pc-u-boot.dtsi +8 -0
index a85e9549c83..e7e4a2c8907 100644
@@ -12,6 +12,14 @@
  	};
  };
 
+&i2c7 {
+	bootph-pre-ram;
+};
+
+&i2c7_xfer {
+	bootph-pre-ram;
+};
+
  &gpio4 {
  	bootph-pre-ram;
  };
board/firefly/roc-pc-rk3399/roc-pc-rk3399.c +11 -0
index 6937a27176f..8f54e526c19 100644
@@ -5,14 +5,24 @@
 
  #include <dm.h>
  #include <env.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <image.h>
  #include <log.h>
  #include <spl_gpio.h>
+#include <asm/global_data.h>
  #include <asm/io.h>
 
  #include <asm/arch-rockchip/cru.h>
  #include <asm/arch-rockchip/gpio.h>
  #include <asm/arch-rockchip/grf_rk3399.h>
 
+#define ROC_PC_MP8859_BUS	"i2c@ff160000"
+#define ROC_PC_MP8859_ADDR	0x66
+#define ROC_PC_PLUS_FDTFILE	"rockchip/rk3399-roc-pc-plus.dtb"
+
+DECLARE_GLOBAL_DATA_PTR;
+
  #ifdef CONFIG_XPL_BUILD
 
  #define PMUGRF_BASE	0xff320000

@@ -54,4 +64,36 @@ void led_setup(void)
  	spl_gpio_output(gpio0, GPIO(BANK_B, 5), 1);
  }
 
+static bool is_roc_pc_plus(void)

board/firefly/roc-pc-rk3399/roc-pc-rk3399.c void led_setup(void) · line 77

Quoted 10 lines
board/firefly/roc-pc-rk3399/roc-pc-rk3399.c +10 -0
+{
+	struct udevice *bus, *dev;
+
+	if (!(CONFIG_IS_ENABLED(I2C) && CONFIG_IS_ENABLED(DM_I2C)))
+		return false;
+
+	if (uclass_get_device_by_name(UCLASS_I2C, ROC_PC_MP8859_BUS, &bus))
+		return false;
+
+	return !dm_i2c_probe(bus, ROC_PC_MP8859_ADDR, 0, &dev);

Between v4 and v5, the exclamation point now inverts the result of dm_i2c_probe and I believe this is incorrect.

dm_i2c_probe returns 0 if a chip was found, -ve otherwise. The ROC-RK3399-PC-PLUS does NOT have this chip, therefore is_roc_pc_plus() should return false (0) when the chip is NOT detected, meaning we should NOT invert dm_i2c_probe(). Is this correct?

Cheers,
Quentin

author
#4 lore raw

PATCH v5 4/4 rockchip: roc-pc-rk3399: Enable redundant environment

In reply to Fabio Estevam

From: Fabio Estevam <[email protected]>

Keep the primary U-Boot environment at its existing 0x3f8000 offset and use the preceding 32 KiB region at 0x3f0000 for the redundant copy.

Both copies are aligned to the 4 KiB erase size and together occupy 0x3f0000 through 0x3fffff. Redundancy protects the environment against power loss or an interrupted update.

Signed-off-by Fabio Estevam <[email protected]>
Reviewed-by Quentin Schulz <[email protected]>

---
Changes since v4:
- None. Only added Quentin's Reviewed-by tag.

 configs/roc-pc-rk3399_defconfig | 2 ++
 1 file changed, 2 insertions(+)
configs/roc-pc-rk3399_defconfig +2 -0
index 53182dc8251..4347bab598a 100644
@@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800
 CONFIG_SF_DEFAULT_BUS=1
 CONFIG_DEBUG_UART_BASE=0xFF1A0000
 CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_ENV_OFFSET_REDUND=0x3F0000
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
 CONFIG_SPL_SPI=y
 CONFIG_DEBUG_UART=y

@@ -41,6 +42,7 @@ CONFIG_SPL_OF_CONTROL=y
 CONFIG_OF_LIST="rockchip/rk3399-roc-pc rockchip/rk3399-roc-pc-plus"
 CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
 CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_ENV_REDUNDANT=y
 CONFIG_ENV_RELOC_GD_ENV_ADDR=y
 CONFIG_ROCKCHIP_GPIO=y
 CONFIG_SYS_I2C_ROCKCHIP=y
Signature · 1 line
2.43.0