drm/msm/dpu: clear pending peripheral flush state
Subsystems (4)
PATCH 1/1 drm/msm/dpu: clear pending peripheral flush state
dpu_hw_ctl_clear_pending_flush() resets the cached per-block state after a flush transaction, but misses pending_periph_flush_mask.
The peripheral flush updater accumulates interface bits in this mask. A later transaction which sets the top-level peripheral flush bit can write stale interface bits to CTL_PERIPH_FLUSH together with the current state.
Peripheral flush support was added after the helper started clearing every individual pending flush mask. Clear the peripheral mask together with the other cached child masks.
--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 1 + 1 file changed, 1 insertion(+)
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +1 -0
@@ -118,6 +118,7 @@ static inline void dpu_hw_ctl_clear_pending_flush(struct dpu_hw_ctl *ctx) ctx->pending_intf_flush_mask =0 ; ctx->pending_wb_flush_mask =0 ; ctx->pending_cwb_flush_mask =0 ; + ctx->pending_periph_flush_mask =0 ; ctx->pending_merge_3d_flush_mask =0 ; ctx->pending_dsc_flush_mask =0 ; ctx->pending_cdm_flush_mask =0 ;
Signature · 1 line
2.55.0
Quoted 11 lines · Saim Shujah
dpu_hw_ctl_clear_pending_flush()resets the cached per-block state after a flush transaction, but missespending_periph_flush_mask.The peripheral flush updater accumulates interface bits in this mask. A later transaction which sets the top-level peripheral flush bit can write stale interface bits to
CTL_PERIPH_FLUSHtogether with the current state.Peripheral flush support was added after the helper started clearing every individual pending flush mask. Clear the peripheral mask together with the other cached child masks.
Quoted 7 lines
Fixes 64f7b81f0358 ("drm/msm/dpu: add support of new peripheral flush mechanism")Signed-off-by Saim Shujah <[email protected]>--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 1 + 1 file changed, 1 insertion(+)
Quoted 1 line
Signature · 2 lines
With best wishes Dmitry