arm64: dts: qcom: clean up PCI function nodes
v2 cover arm64: dts: qcom: clean up PCI function nodes
While working on upstream support for the Toshiba TC9564 SoC I learned that its PCIe endpoint function nodes included the device_type property, indicating each is a "pci" device. Herve Codina pointed out that this is not correct; only a PCI device "that implements a PCI bus" should define that property.
I looked at other upstream devicetree files and I found four other places with this same mistake. (All are for Qualcomm platforms, and all are for platforms using a TC956x SoC.)
This series removes the device_type property where it is defined for a PCI endpoint function.
It also removes the #address-cells, #size-cells, and ranges properties in these cases, with a plan to restore them only when they are known to be needed (to implement pci-ep-bus sub-nodes).
-Alex
Between version 1 and version 2:
- Added Reviewed-by from Mani and Konrad
- Added a patch that updates "qcs8550-rb5gen2.dts" as well
Version 1 is available here:
https://lore.kernel.org/lkml/[email protected]/
Alex Elder (6):
arm64: dts: qcom: qcs6490-rb3gen2: clean up PCI function nodes
arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: clean up PCI
function nodes
arm64: dts: qcom: lemans-evk-ifp-mezzanine: clean up PCI function
nodes
arm64: dts: qcom: monaco-evk-ifp-mezzanine: clean up PCI function
nodes
arm64: dts: qcom: qcs6490-thundercomm-minipc-g1iot: clean up PCI
function nodes
arm64: dts: qcom: qcs8550-rb5gen2: clean up PCI function nodes
.../boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso | 8 -------- .../boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso | 8 -------- .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 16 ---------------- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 8 -------- .../qcom/qcs6490-thundercomm-minipc-g1iot.dts | 8 -------- arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts | 8 -------- 6 files changed, 56 deletions(-)
base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
Signature · 1 line
2.53.0
PATCH v2 1/6 arm64: dts: qcom: qcs6490-rb3gen2: clean up PCI function nodes
The TC9564 SoC contains a PCIe switch with three downstream ports. The third downstream port connects to an embedded PCI endpoint, and that endpoint implements two PCI functions.
The devicetree node describing those functions incorrectly includes this property:
device_type = "pci";
That property should only be used for a PCI device "that implements a PCI bus", but not a PCIe function. So remove the device_type property from the nodes representing the two embedded PCI functions.
Additionally, those properties contain #address-cells, #size-cells, and ranges properties. And although these properties *will* be appropriate for these functions on an RB3gen2, they are not normally used for PCI functions. So remove these properties as well; we'll include them in the commit that actually adds the pci-ep-bus sub-node to each of these PCI function nodes.
--- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 8 -------- 1 file changed, 8 deletions(-)
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +0 -8
@@ -956,18 +956,10 @@ pcie@3,0 { pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; }; };
Signature · 1 line
2.53.0
Re: [PATCH v2 1/6] arm64: dts: qcom: qcs6490-rb3gen2: clean up PCI function nodes
Quoted 20 lines · Alex Elder
The TC9564 SoC contains a PCIe switch with three downstream ports. The third downstream port connects to an embedded PCI endpoint, and that endpoint implements two PCI functions.
The devicetree node describing those functions incorrectly includes this property:
device_type = "pci";That property should only be used for a PCI device "that implements a PCI bus", but not a PCIe function. So remove the
device_typeproperty from the nodes representing the two embedded PCI functions.Additionally, those properties contain #address-cells, #size-cells, and ranges properties. And although these properties *will* be appropriate for these functions on an RB3gen2, they are not normally used for PCI functions. So remove these properties as well; we'll include them in the commit that actually adds the pci-ep-bus sub-node to each of these PCI function nodes.
Quoted 4 lines
Reviewed-by Manivannan Sadhasivam <[email protected]>Reviewed-by Konrad Dybcio <[email protected]>Fixes aa7b4bbcb3a1d ("arm64: dts: qcom: qcs6490-rb3gen2: Add TC9563 PCIe switch node")Signed-off-by Alex Elder <[email protected]>
PATCH v2 2/6 arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: clean up PCI function nodes
In reply to Alex ElderThe qcs6490-rb3gen2-industrial-mezzanine overlay defines two nodes representing TC956x chips, each of which contains a PCIe switch and an embedded endpoint that implements two PCIe functions.
The devicetree nodes erroneously include a "pci" device_type property for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes.
In addition, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove properties as well; they can be added back once they are actually needed/used.
--- .../qcs6490-rb3gen2-industrial-mezzanine.dtso | 16 ---------------- 1 file changed, 16 deletions(-)
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso +0 -16
@@ -132,18 +132,10 @@ pcie@3,0 { pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; };
@@ -227,18 +219,10 @@ pcie@3,0 { pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; }; };
Signature · 1 line
2.53.0
Re: [PATCH v2 2/6] arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: clean up PCI function nodes
Quoted 14 lines · Alex Elder
The qcs6490-rb3gen2-industrial-mezzanine overlay defines two nodes representing TC956x chips, each of which contains a PCIe switch and an embedded endpoint that implements two PCIe functions.
The devicetree nodes erroneously include a "pci"
device_typeproperty for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes.In addition, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove properties as well; they can be added back once they are actually needed/used.
Quoted 4 lines
Reviewed-by Manivannan Sadhasivam <[email protected]>Reviewed-by Konrad Dybcio <[email protected]>Fixes 4559b435f741b ("arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add TC9563 PCIe switch node for PCIe0")Signed-off-by Alex Elder <[email protected]>
PATCH v2 3/6 arm64: dts: qcom: lemans-evk-ifp-mezzanine: clean up PCI function nodes
In reply to Alex ElderThe lemans-evk-ifp-mezzanine overlay defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions.
The devicetree nodes erroneously include a "pci" device_type property for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes.
In addition, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove these properties as well; they can be added back once they are actually needed/used.
--- arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso | 8 -------- 1 file changed, 8 deletions(-)
arch/arm64/boot/dts/qcom/lemans-evk-ifp-mezzanine.dtso +0 -8
@@ -273,18 +273,10 @@ pcie@3,0 { pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; }; };
Signature · 1 line
2.53.0
Re: [PATCH v2 3/6] arm64: dts: qcom: lemans-evk-ifp-mezzanine: clean up PCI function nodes
Quoted 14 lines · Alex Elder
The lemans-evk-ifp-mezzanine overlay defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions.
The devicetree nodes erroneously include a "pci"
device_typeproperty for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes.In addition, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove these properties as well; they can be added back once they are actually needed/used.
Quoted 4 lines
Reviewed-by Manivannan Sadhasivam <[email protected]>Reviewed-by Konrad Dybcio <[email protected]>Fixes b64abb26a2916 ("arm64: dts: qcom: lemans-evk: Add IFP Mezzanine")Signed-off-by Alex Elder <[email protected]>
PATCH v2 4/6 arm64: dts: qcom: monaco-evk-ifp-mezzanine: clean up PCI function nodes
In reply to Alex ElderThe monaco-evk-ifp-mezzanine overlay defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions.
The devicetree nodes erroneously include a "pci" device_type property for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes.
In addition, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove properties as well; they can be added back once they are actually needed/used.
--- arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso | 8 -------- 1 file changed, 8 deletions(-)
arch/arm64/boot/dts/qcom/monaco-evk-ifp-mezzanine.dtso +0 -8
@@ -119,18 +119,10 @@ pcie@3,0 { pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; }; };
Signature · 1 line
2.53.0
Re: [PATCH v2 4/6] arm64: dts: qcom: monaco-evk-ifp-mezzanine: clean up PCI function nodes
Quoted 14 lines · Alex Elder
The monaco-evk-ifp-mezzanine overlay defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions.
The devicetree nodes erroneously include a "pci"
device_typeproperty for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes.In addition, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove properties as well; they can be added back once they are actually needed/used.
Quoted 4 lines
Reviewed-by Manivannan Sadhasivam <[email protected]>Reviewed-by Konrad Dybcio <[email protected]>Fixes 5a67924d2fc57 ("arm64: dts: qcom: monaco-evk: Add IFP Mezzanine")Signed-off-by Alex Elder <[email protected]>
PATCH v2 5/6 arm64: dts: qcom: qcs6490-thundercomm-minipc-g1iot: clean up PCI function nodes
In reply to Alex ElderThe Thundercomm AI Mini PC G1 IoT devicetree source file defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions.
The devicetree nodes erroneously include a "pci" device_type property for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes.
In addition, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove properties as well; they can be added back once they are actually needed/used.
--- .../boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts | 8 -------- 1 file changed, 8 deletions(-)
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +0 -8
@@ -792,18 +792,10 @@ pcie@3,0 { pcie@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; pcie@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; }; };
Signature · 1 line
2.53.0
Re: [PATCH v2 5/6] arm64: dts: qcom: qcs6490-thundercomm-minipc-g1iot: clean up PCI function nodes
Quoted 14 lines · Alex Elder
The Thundercomm AI Mini PC G1 IoT devicetree source file defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions.
The devicetree nodes erroneously include a "pci"
device_typeproperty for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes.In addition, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove properties as well; they can be added back once they are actually needed/used.
Quoted 4 lines
Reviewed-by Manivannan Sadhasivam <[email protected]>Reviewed-by Konrad Dybcio <[email protected]>Fixes 1cde54c54b83b ("arm64: dts: qcom: qcs6490: Add Thundercomm AI Mini PC G1 IoT")Signed-off-by Alex Elder <[email protected]>
PATCH v2 6/6 arm64: dts: qcom: qcs8550-rb5gen2: clean up PCI function nodes
In reply to Alex ElderThe Qualcomm RB5gen2 devicetree source file defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions.
The devicetree nodes erroneously include a "pci" device_type property for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes.
In addition, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove properties as well; they can be added back once they are actually needed/used.
---
v2: - New patch updating DTS that was not present for v1
arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts | 8 -------- 1 file changed, 8 deletions(-)
arch/arm64/boot/dts/qcom/qcs8550-rb5gen2.dts +0 -8
@@ -1128,18 +1128,10 @@ pcie@3,0 { pci@0,0 { reg = <0x50000 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; pci@0,1 { reg = <0x50100 0x0 0x0 0x0 0x0>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges; }; }; };
Signature · 1 line
2.53.0
Re: [PATCH v2 6/6] arm64: dts: qcom: qcs8550-rb5gen2: clean up PCI function nodes
Quoted 9 lines · Alex Elder
The Qualcomm RB5gen2 devicetree source file defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions.
The devicetree nodes erroneously include a "pci"
device_typeproperty for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes.
Quoted 7 lines
In addition, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove properties as well; they can be added back once they are actually needed/used.
Fixes 33cae252054a6 ("arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support")Signed-off-by Alex Elder <[email protected]>
Re: [PATCH v2 6/6] arm64: dts: qcom: qcs8550-rb5gen2: clean up PCI function nodes
In reply to Alex ElderQuoted 9 lines · Alex Elder
The Qualcomm RB5gen2 devicetree source file defines a node representing a TC956x chip which contains a PCIe switch and an embedded endpoint that implements two PCIe functions.
The devicetree nodes erroneously include a "pci"
device_typeproperty for the two PCIe functions. That property should only be used for a PCI device "that implements a PCI bus". Remove this property for the two function nodes.
Quoted 7 lines
In addition, these nodes define #address-cells, #size-cells, and ranges properties, which are not normally defined for PCIe endpoints. Remove properties as well; they can be added back once they are actually needed/used.
Fixes 33cae252054a6 ("arm64: dts: qcom: qcs8550: add QCS8550 RB5Gen2 board support")Signed-off-by Alex Elder <[email protected]>
- Mani
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