iio: adc: ad4134: Enable greater sample rate data capture

---
Now
find drivers/iio/ -type f | xargs grep -i "Analog Device " finds no leftover occurrence of such typo.

Also,
grep -nrIi drivers/iio/ -e "Analog Device" | wc -l and
grep -nrIi drivers/iio/ -e "Analog Devices" | wc -l both count the same number of lines.

Quoted 5 lines · Marcelo Schmitt

---
Now
find drivers/iio/ -type f | xargs grep -i "Analog Device " finds no leftover occurrence of such typo.

Quoted 5 lines

Also,
grep -nrIi drivers/iio/ -e "Analog Device" | wc -l and
grep -nrIi drivers/iio/ -e "Analog Devices" | wc -l both count the same number of lines.

Why not git grep ...?

...

Reviewed-by Andy Shevchenko <[email protected]>

But you also want to fix possessive suffix usage

$ git grep -n 'Analog Device[^s]'

Documentation/iio/ade9000.rst:7:This driver supports Analog Device's ADE9000 and ADE9078 energy measurement Documentation/iio/adis16475.rst:7:This driver supports Analog Device's IMUs on SPI bus. Documentation/iio/adis16480.rst:7:This driver supports Analog Device's IMUs on SPI bus. Documentation/iio/adis16550.rst:7:This driver supports Analog Device's IMUs on SPI bus. Documentation/iio/adxl313.rst:7:This driver supports Analog Device's ADXL313 on SPI/I2C bus. Documentation/iio/adxl345.rst:7:This driver supports Analog Device's ADXL345/375 on SPI/I2C bus. Documentation/iio/adxl380.rst:7:This driver supports Analog Device's ADXL380/382 on SPI/I2C bus.

drivers/iio/adc/Kconfig:108:    tristate "Analog Device AD4130 ADC Driver"
drivers/iio/adc/Kconfig:124:    tristate "Analog Device AD4134 ADC Driver"
drivers/iio/adc/Kconfig:136:    tristate "Analog Device AD4170-4 ADC Driver"
drivers/iio/adc/Kconfig:167:    tristate "Analog Device AD4695 ADC Driver"
drivers/iio/adc/Kconfig:182:    tristate "Analog Device AD4851 DAS Driver"
drivers/iio/adc/Kconfig:350:    tristate "Analog Device AD7405 ADC Driver"

drivers/iio/dac/ad3552r.c:699:MODULE_DESCRIPTION("Analog Device AD3552R DAC");

Quoted 1 line · Andy Shevchenko

On Wed, Sep 02, 2026 at 02:21:34PM -0300, Marcelo Schmitt wrote:

Quoted 10 lines

Quoted 9 lines

Now
find drivers/iio/ -type f | xargs grep -i "Analog Device " finds no leftover occurrence of such typo.

Also,
grep -nrIi drivers/iio/ -e "Analog Device" | wc -l and
grep -nrIi drivers/iio/ -e "Analog Devices" | wc -l both count the same number of lines.

Quoted 2 lines

Why not git grep ...?

Could be. I'm just more used to non-git grep.

Thanks for suggestions to other patches too. Will apply them for v2.

Quoted 2 lines · Marcelo Schmitt

Quoted 1 line · Andy Shevchenko

On Wed, Sep 02, 2026 at 02:21:34PM -0300, Marcelo Schmitt wrote:

Quoted 10 lines

Quoted 10 lines

Quoted 9 lines

Now
find drivers/iio/ -type f | xargs grep -i "Analog Device " finds no leftover occurrence of such typo.

Also,
grep -nrIi drivers/iio/ -e "Analog Device" | wc -l and
grep -nrIi drivers/iio/ -e "Analog Devices" | wc -l both count the same number of lines.

Quoted 3 lines

Quoted 2 lines

Why not git grep ...?

Could be. I'm just more used to non-git grep.

The rationale here is that grep goes over filesystem (and files) while git grep goes over index which requires much less resources to waste and hence 10x faster or so). That said, I highly recommend using git grep when it's applicable.

Quoted 1 line

Thanks for suggestions to other patches too. Will apply them for v2.

You're welcome!

Add includes that were missing (according to include-what-you-use tool) to comply with include what is used principles. Namely, add bits.h for BIT and GENMASK, and time64.h for USEC_PER_SEC.

Remove time.h which is covered by time64.h and iio/types.h which is covered by iio/iio.h.

While updating the list, organize it to follow current IIO include list convention.

Protect single-sample read operations from going wrong if two or more of them run concurrently. Serialize the data read operation so to avoid single-sample read requests disrupting each other.

gpiod_set_value_cansleep(st->odr_gpio, 1);

Quoted 3 lines · Marcelo Schmitt

Protect single-sample read operations from going wrong if two or more of them run concurrently. Serialize the data read operation so to avoid single-sample read requests disrupting each other.

...

Quoted 1 line

case IIO_CHAN_INFO_RAW:

drivers/iio/adc/ad4134.c static int ad4134_read_raw(struct iio_dev *indio_dev, · line 267

Quoted 1 line

drivers/iio/adc/ad4134.c +1 -0

+		guard(mutex)(&st->lock);

Always delimit guard()() with a blank line.

Quoted 1 line

gpiod_set_value_cansleep(st->odr_gpio, 1);

...

With blank line added

Reviewed-by Andy Shevchenko <[email protected]>

AD4134 supports four types of programmable digital filters that allow users to choose between different output data rates and input bandwidths. Enable basic digital filter configuration by providing a way to select which filter type is activated for each channel.

drivers/iio/adc/ad4134.c +2 -0

+	{ }
+};

drivers/iio/adc/ad4134.c +6 -0

+	unsigned int mask, reg_val;
+	int ret;
+
+	IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
+	if (IIO_DEV_ACQUIRE_FAILED(claim))
+		return -EBUSY;

+}

Document how AD4134 chips are connected to the host SPI controller according to different wiring configurations.

Signed-off-by Marcelo Schmitt <[email protected]>

---
 .../bindings/iio/adc/adi,ad4134.yaml          | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +0 -0

index ea6d7e026419..d843c02a394a 100644
@@ -131,6 +131,28 @@ properties:
     enum: [ free-running, gated ]
     default: gated

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +13 -0

+
+      * no-cs: The datasheet calls this "minimum I/O mode". In this mode, the CS
+        line is not used (tied to GND).
+      * 4-wire: Specifies a conventional SPI wiring configuration.
+      * one-channel-chain: In this mode, the DOUT0 line of one chip is connected
+        to DOUT2 of the next chip upstream in the chain. Only the data interface
+        of the upmost device in the stream is in direct connection with the
+        digital host.
+      * two-channel-chain: In this mode, the DOUT0 and DOUT1 lines of one chip
+        are respectively connected to DOUT2 and DOUT3 of the next chip upstream
+        in the chain. Only the data interface of the upmost device in the stream
+        is in direct connection with the digital host.
+
 required:
   - compatible
   - reg

Signature · 1 line

2.53.0

Quoted 25 lines · Marcelo Schmitt

Document how AD4134 chips are connected to the host SPI controller according to different wiring configurations.

Signed-off-by Marcelo Schmitt <[email protected]>

---
 .../bindings/iio/adc/adi,ad4134.yaml          | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +9 -0

index ea6d7e026419..d843c02a394a 100644
@@ -131,6 +131,28 @@ properties:
     enum: [ free-running, gated ]
     default: gated
 
+  adi,spi-mode:
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [ no-cs, 4-wire, one-channel-chain, two-channel-chain ]
+    description: |
+      This property indicates the SPI wiring configuration.
+
+      When this property is omitted, it is assumed that the device is using
+      'no-cs' wiring. When this property is present, it indicates that the
+      device is using one of the following wiring configurations:

I'd also really appreciate a dts example for a system
with one-channel-chain or two-channel-chain looks, given the second device may require different supplies etc. I have no impression in my head of how the dt would be constructed, so I'd like to see wht you have in mind.

Quoted 4 lines

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +3 -0

+
+      * no-cs: The datasheet calls this "minimum I/O mode". In this mode, the CS
+        line is not used (tied to GND).

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml properties: · line 155

Quoted 10 lines

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +10 -0

+      * 4-wire: Specifies a conventional SPI wiring configuration.
+      * one-channel-chain: In this mode, the DOUT0 line of one chip is connected
+        to DOUT2 of the next chip upstream in the chain. Only the data interface
+        of the upmost device in the stream is in direct connection with the
+        digital host.
+      * two-channel-chain: In this mode, the DOUT0 and DOUT1 lines of one chip
+        are respectively connected to DOUT2 and DOUT3 of the next chip upstream
+        in the chain. Only the data interface of the upmost device in the stream
+        is in direct connection with the digital host.
+

Quoted 17 lines · Conor Dooley

Quoted 16 lines · Marcelo Schmitt

Document how AD4134 chips are connected to the host SPI controller according to different wiring configurations.

Signed-off-by Marcelo Schmitt <[email protected]>

---
 .../bindings/iio/adc/adi,ad4134.yaml          | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +0 -0

index ea6d7e026419..d843c02a394a 100644
@@ -131,6 +131,28 @@ properties:
     enum: [ free-running, gated ]
     default: gated
 

Quoted 10 lines

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml properties: · line 142

Quoted 9 lines

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +9 -0

+  adi,spi-mode:
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [ no-cs, 4-wire, one-channel-chain, two-channel-chain ]
+    description: |
+      This property indicates the SPI wiring configuration.
+
+      When this property is omitted, it is assumed that the device is using
+      'no-cs' wiring. When this property is present, it indicates that the
+      device is using one of the following wiring configurations:

...

Quoted 5 lines

I'd also really appreciate a dts example for a system
with one-channel-chain or two-channel-chain looks, given the second device may require different supplies etc. I have no impression in my head of how the dt would be constructed, so I'd like to see wht you have in mind.

Quoted 28 lines · Marcelo Schmitt

Quoted 26 lines · Conor Dooley

Quoted 25 lines · Marcelo Schmitt

Document how AD4134 chips are connected to the host SPI controller according to different wiring configurations.

Signed-off-by Marcelo Schmitt <[email protected]>

---
 .../bindings/iio/adc/adi,ad4134.yaml          | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +9 -0

index ea6d7e026419..d843c02a394a 100644
@@ -131,6 +131,28 @@ properties:
     enum: [ free-running, gated ]
     default: gated
 
+  adi,spi-mode:
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [ no-cs, 4-wire, one-channel-chain, two-channel-chain ]
+    description: |
+      This property indicates the SPI wiring configuration.
+
+      When this property is omitted, it is assumed that the device is using
+      'no-cs' wiring. When this property is present, it indicates that the
+      device is using one of the following wiring configurations:  

...

Quoted 6 lines

Quoted 5 lines

I'd also really appreciate a dts example for a system
with one-channel-chain or two-channel-chain looks, given the second device may require different supplies etc. I have no impression in my head of how the dt would be constructed, so I'd like to see wht you have in mind.

...

Realized what I said doesn't make much sense. The peripherals can all have the same configuration and thus share CS, SCLK, and controller SDO. The wiring would be like the following

::

  +-----------------------+                               +-----------------+
  |         AD4134        |                               | SPI Controller  |
  |                       |                               |                 |
  |                       |                               |                 |
  | SPI interface    SCLK |<--------------------+---------| SCLK            |
  | for register       CS |<--------------------|-+-------| CS              |
  | access            SDI |<--------------------|-|-+-----| SDO             |
  |                   SDO |------->|¯¯¯¯\       | | |     |                 |
  |                       |        |MUX  >------|-|-|---->| SDI0            |
  | Data interface  DOUT0 |------->|____/<------|-|-|---- | GPIO            |
  | for ADC sample  DOUT1 |---------------------|-|-|---->| SDI1            |
  | data read        DCLK |<-------------+------|-|-|-----| DCLK            |
  |                 DOUT2 |<-+           |      | | |     |                 |
  |                 DOUT3 |<-|-+         |      | | |     |                 |
  |                   ODR |<-|-|---------|--+   | | |  +->| Offload Trigger |
  +-----------------------+  | |         |  |   | | |  |  +-----------------+
                             | |         |  |   | | |  +--| PWM1            |
                             | |         |  +---| | | ----| PWM0            |
                             | |         |  |   | | |    +-----------------+
                             | |         |  |   | | |
  +-----------------------+  | |         |  |   | | |
  |         AD4134        |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  | SPI interface         |  | |         |  |   | | |
  | for register     SCLK |<-|-|---------|--|---+ | |
  | access             CS |<-|-|---------|--|---|-+ |
  |                   SDI |<-|-|---------|--|---|-|-+
  |                   SDO |  | |         |  |   | | |
  | Data interface        |  | |         |  |   | | |
  | for ADC sample  DOUT0 |--+ |         |  |   | | |
  | data read       DOUT1 |----+         |  |   | | |
  |                 DOUT2 |<-+           |  |   | | |
  |                 DOUT3 |<-|-+         |  |   | | |
  |                  DCLK |<-|-|---------+  |   | | |
  |                   ODR |<-|-|---------|--+   | | |
  +-----------------------+  | |         |  |   | | |
                             | |         |  |   | | |
                             | |         |  |   | | |
                             | |         |  |   | | |
  +-----------------------+  | |         |  |   | | |
  |         AD4134        |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  | SPI interface    SCLK |<-|-|---------|--|---+ | |
  | for register       CS |<-|-|---------|--|-----+ |
  | access            SDI |<-|-|---------|--|-------+
  |                       |  | |         |  |
  | Data interface        |  | |         |  |
  | for ADC sample  DOUT0 |--+ |         |  |
  | data read       DOUT1 |----+         |  |
  |                 DOUT2 |              |  |
  |                 DOUT3 |              |  |
  |                  DCLK |<-------------+  |
  |                   ODR |<----------------+
  +-----------------------+

So we would set them as only one daisy-chained device.

    spi {
        ...
        adc@0 {
            compatible = "adi,ad4134";
            reg = <0>;
            spi-rx-bus-width = <1>, <1>; /* 2 lanes of 1 bit each */

            <supplies, clock, and other properties ...> 

            #daisy-chained-devices = <2>;

            adi,spi-mode = "two-channel-chain";
        };
    };

Thanks,
Marcelo

Quoted 35 lines · On Fri, 4 Sep 2026 19:06:44 -0300 Marcelo Schmitt <[email protected]>…

Quoted 34 lines · Marcelo Schmitt

Quoted 26 lines · Conor Dooley

Quoted 25 lines · Marcelo Schmitt

Document how AD4134 chips are connected to the host SPI controller according to different wiring configurations.

Signed-off-by Marcelo Schmitt <[email protected]>

---
 .../bindings/iio/adc/adi,ad4134.yaml          | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +9 -0

index ea6d7e026419..d843c02a394a 100644
@@ -131,6 +131,28 @@ properties:
     enum: [ free-running, gated ]
     default: gated
 
+  adi,spi-mode:
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [ no-cs, 4-wire, one-channel-chain, two-channel-chain ]
+    description: |
+      This property indicates the SPI wiring configuration.
+
+      When this property is omitted, it is assumed that the device is using
+      'no-cs' wiring. When this property is present, it indicates that the
+      device is using one of the following wiring configurations:  

...

Quoted 5 lines

I'd also really appreciate a dts example for a system
with one-channel-chain or two-channel-chain looks, given the second device may require different supplies etc. I have no impression in my head of how the dt would be constructed, so I'd like to see wht you have in mind.

Quoted 5 lines

...

Realized what I said doesn't make much sense. The peripherals can all have the same configuration and thus share CS, SCLK, and controller SDO. The wiring would be like the following

That mux in the middle is controlled how?

I'd assume we still have separate chip selects and SDO/SDI shared. So I'd expect those to be on one SPI bus and the data to be going into separate buses (maybe all that can be hidden in the backend, not sure).

Or are you suggesting we are just letting all the chained devices see the same register writes? That might work I guess with no ability to read any register state back other than for first device.

If you want to do the
mux magic below you are going to need to treat it as an SPI mux - just with some lines shared. That means this device ends up split into multiple device (even if only one ad4134 which is messy).

So to me this has a simple SPI bus, potentially connected to multiple devices and an IIO backend that deals with DOUT0 etc and the chaining.

Jonathan

Quoted 79 lines

::

  +-----------------------+                               +-----------------+
  |         AD4134        |                               | SPI Controller  |
  |                       |                               |                 |
  |                       |                               |                 |
  | SPI interface    SCLK |<--------------------+---------| SCLK            |
  | for register       CS |<--------------------|-+-------| CS              |
  | access            SDI |<--------------------|-|-+-----| SDO             |
  |                   SDO |------->|¯¯¯¯\       | | |     |                 |
  |                       |        |MUX  >------|-|-|---->| SDI0            |
  | Data interface  DOUT0 |------->|____/<------|-|-|---- | GPIO            |
  | for ADC sample  DOUT1 |---------------------|-|-|---->| SDI1            |
  | data read        DCLK |<-------------+------|-|-|-----| DCLK            |
  |                 DOUT2 |<-+           |      | | |     |                 |
  |                 DOUT3 |<-|-+         |      | | |     |                 |
  |                   ODR |<-|-|---------|--+   | | |  +->| Offload Trigger |
  +-----------------------+  | |         |  |   | | |  |  +-----------------+
                             | |         |  |   | | |  +--| PWM1            |
                             | |         |  +---| | | ----| PWM0            |
                             | |         |  |   | | |    +-----------------+
                             | |         |  |   | | |
  +-----------------------+  | |         |  |   | | |
  |         AD4134        |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  | SPI interface         |  | |         |  |   | | |
  | for register     SCLK |<-|-|---------|--|---+ | |
  | access             CS |<-|-|---------|--|---|-+ |
  |                   SDI |<-|-|---------|--|---|-|-+
  |                   SDO |  | |         |  |   | | |
  | Data interface        |  | |         |  |   | | |
  | for ADC sample  DOUT0 |--+ |         |  |   | | |
  | data read       DOUT1 |----+         |  |   | | |
  |                 DOUT2 |<-+           |  |   | | |
  |                 DOUT3 |<-|-+         |  |   | | |
  |                  DCLK |<-|-|---------+  |   | | |
  |                   ODR |<-|-|---------|--+   | | |
  +-----------------------+  | |         |  |   | | |
                             | |         |  |   | | |
                             | |         |  |   | | |
                             | |         |  |   | | |
  +-----------------------+  | |         |  |   | | |
  |         AD4134        |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  | SPI interface    SCLK |<-|-|---------|--|---+ | |
  | for register       CS |<-|-|---------|--|-----+ |
  | access            SDI |<-|-|---------|--|-------+
  |                       |  | |         |  |
  | Data interface        |  | |         |  |
  | for ADC sample  DOUT0 |--+ |         |  |
  | data read       DOUT1 |----+         |  |
  |                 DOUT2 |              |  |
  |                 DOUT3 |              |  |
  |                  DCLK |<-------------+  |
  |                   ODR |<----------------+
  +-----------------------+

So we would set them as only one daisy-chained device.

    spi {
        ...
        adc@0 {
            compatible = "adi,ad4134";
            reg = <0>;
            spi-rx-bus-width = <1>, <1>; /* 2 lanes of 1 bit each */

            <supplies, clock, and other properties ...> 

            #daisy-chained-devices = <2>;

            adi,spi-mode = "two-channel-chain";
        };
    };

Thanks,
Marcelo

Quoted 40 lines · Jonathan Cameron

Quoted 37 lines · On Fri, 4 Sep 2026 19:06:44 -0300 Marcelo Schmitt <[email protected]>…

Quoted 34 lines · Marcelo Schmitt

Quoted 26 lines · Conor Dooley

Quoted 25 lines · Marcelo Schmitt

Document how AD4134 chips are connected to the host SPI controller according to different wiring configurations.

Signed-off-by Marcelo Schmitt <[email protected]>

---
 .../bindings/iio/adc/adi,ad4134.yaml          | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +9 -0

index ea6d7e026419..d843c02a394a 100644
@@ -131,6 +131,28 @@ properties:
     enum: [ free-running, gated ]
     default: gated
 
+  adi,spi-mode:
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [ no-cs, 4-wire, one-channel-chain, two-channel-chain ]
+    description: |
+      This property indicates the SPI wiring configuration.
+
+      When this property is omitted, it is assumed that the device is using
+      'no-cs' wiring. When this property is present, it indicates that the
+      device is using one of the following wiring configurations:    

...

Quoted 5 lines

I'd also really appreciate a dts example for a system
with one-channel-chain or two-channel-chain looks, given the second device may require different supplies etc. I have no impression in my head of how the dt would be constructed, so I'd like to see wht you have in mind.

...

Quoted 5 lines

Quoted 3 lines

Realized what I said doesn't make much sense. The peripherals can all have the same configuration and thus share CS, SCLK, and controller SDO. The wiring would be like the following

That mux in the middle is controlled how?

The mux is controlled by a GPIO. I ended up drawing the GPIO among SPI lines in the connection diagram but the mux controll signal is not part of the SPI controller.

Quoted 5 lines

I'd assume we still have separate chip selects and SDO/SDI shared. So I'd expect those to be on one SPI bus and the data to be going into separate buses (maybe all that can be hidden in the backend, not sure).

Quoted 3 lines

Or are you suggesting we are just letting all the chained devices see the same register writes? That might work I guess with no ability to read any register state back other than for first device.

Correct, that's the proposed configuration for daisy-chaining. Since all peripherals will receive the same write commands they shall all retain the same register configurations (except maybe for error indication registers). Reading from the topmost device in the chain would be enough to figure out the status of the other chained devices.

Quoted 5 lines

If you want to do the
mux magic below you are going to need to treat it as an SPI mux - just with some lines shared. That means this device ends up split into multiple device (even if only one ad4134 which is messy).

You mean spi-mux.yaml/spi-mux.c? So the goal/intent would be to have one IIO device for each peripheral in the chain? I think that would also work. Though, the only device bringing ADC sample data is the topmost one so that would be the only one buffer capable.

Quoted 4 lines

So to me this has a simple SPI bus, potentially connected to multiple devices and an IIO backend that deals with DOUT0 etc and the chaining.

Yeah, the benefit of having the mux is being able to connect both AD4134 interfaces to a single bus while being able to have ADC sample data on all SDI lines as the diagrams in patch 13.

Alternatively, we could have something like

                                                              +-------------+
  +----------------------+                                    |  DATA HOST  |
  |       AD4134         |                                    |             |
  |                      |                                    |             |
  |Data interface  DOUT0 |----------------------------------->| SDI1        |
  |for ADC data    DOUT1 |----------------------------------->| SDI2        |
  |sample read     DOUT2 |----------------------------------->| SDI3        |
  |                DOUT3 |----------------------------------->| SDI4        |
  |                DCLK  |<--------------+        +---------->| CS          |
  |                ODR   |<------------+ |        | +-------->| SCLK        |
  |                      |             | |        | | +------>| SDO         |
  |                      |             | |        | | | +---->| SDI         |
  | SPI interface   CS   |<-------+    | +--------|-|-|-|-----| DCLK        |
  | for register    SCLK |<-----+ |    |          | | | |     |             |
  | access          SDI  |<---+ | |    |          | | | |     | TRIGGER     |
  |                 SDO  |--+ | | |    |          | | | |     +-------------+
  +----------------------+  | | | |    +----------|-|-|-|---------+
                            | | | +---------------+ | | |
                            | | +-------------------+ | |
                            | +-----------------------+ |
                            +---------------------------+

The downside of the above is we would need an SPI_MULTI_LANE_MODE_STRIPE to read only from SDI1 to SDI4.

Quoted 84 lines

Jonathan

Quoted 79 lines

::

  +-----------------------+                               +-----------------+
  |         AD4134        |                               | SPI Controller  |
  |                       |                               |                 |
  |                       |                               |                 |
  | SPI interface    SCLK |<--------------------+---------| SCLK            |
  | for register       CS |<--------------------|-+-------| CS              |
  | access            SDI |<--------------------|-|-+-----| SDO             |
  |                   SDO |------->|¯¯¯¯\       | | |     |                 |
  |                       |        |MUX  >------|-|-|---->| SDI0            |
  | Data interface  DOUT0 |------->|____/<------|-|-|---- | GPIO            |
  | for ADC sample  DOUT1 |---------------------|-|-|---->| SDI1            |
  | data read        DCLK |<-------------+------|-|-|-----| DCLK            |
  |                 DOUT2 |<-+           |      | | |     |                 |
  |                 DOUT3 |<-|-+         |      | | |     |                 |
  |                   ODR |<-|-|---------|--+   | | |  +->| Offload Trigger |
  +-----------------------+  | |         |  |   | | |  |  +-----------------+
                             | |         |  |   | | |  +--| PWM1            |
                             | |         |  +---| | | ----| PWM0            |
                             | |         |  |   | | |    +-----------------+
                             | |         |  |   | | |
  +-----------------------+  | |         |  |   | | |
  |         AD4134        |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  | SPI interface         |  | |         |  |   | | |
  | for register     SCLK |<-|-|---------|--|---+ | |
  | access             CS |<-|-|---------|--|---|-+ |
  |                   SDI |<-|-|---------|--|---|-|-+
  |                   SDO |  | |         |  |   | | |
  | Data interface        |  | |         |  |   | | |
  | for ADC sample  DOUT0 |--+ |         |  |   | | |
  | data read       DOUT1 |----+         |  |   | | |
  |                 DOUT2 |<-+           |  |   | | |
  |                 DOUT3 |<-|-+         |  |   | | |
  |                  DCLK |<-|-|---------+  |   | | |
  |                   ODR |<-|-|---------|--+   | | |
  +-----------------------+  | |         |  |   | | |
                             | |         |  |   | | |
                             | |         |  |   | | |
                             | |         |  |   | | |
  +-----------------------+  | |         |  |   | | |
  |         AD4134        |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  | SPI interface    SCLK |<-|-|---------|--|---+ | |
  | for register       CS |<-|-|---------|--|-----+ |
  | access            SDI |<-|-|---------|--|-------+
  |                       |  | |         |  |
  | Data interface        |  | |         |  |
  | for ADC sample  DOUT0 |--+ |         |  |
  | data read       DOUT1 |----+         |  |
  |                 DOUT2 |              |  |
  |                 DOUT3 |              |  |
  |                  DCLK |<-------------+  |
  |                   ODR |<----------------+
  +-----------------------+

So we would set them as only one daisy-chained device.

    spi {
        ...
        adc@0 {
            compatible = "adi,ad4134";
            reg = <0>;
            spi-rx-bus-width = <1>, <1>; /* 2 lanes of 1 bit each */

            <supplies, clock, and other properties ...> 

            #daisy-chained-devices = <2>;

            adi,spi-mode = "two-channel-chain";
        };
    };

Thanks,
Marcelo

Quoted 28 lines · Marcelo Schmitt

Quoted 17 lines · Conor Dooley

Quoted 16 lines · Marcelo Schmitt

Document how AD4134 chips are connected to the host SPI controller according to different wiring configurations.

Signed-off-by Marcelo Schmitt <[email protected]>

---
 .../bindings/iio/adc/adi,ad4134.yaml          | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +0 -0

index ea6d7e026419..d843c02a394a 100644
@@ -131,6 +131,28 @@ properties:
     enum: [ free-running, gated ]
     default: gated
 

Quoted 10 lines

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml properties: · line 142

Quoted 9 lines

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +9 -0

+  adi,spi-mode:
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [ no-cs, 4-wire, one-channel-chain, two-channel-chain ]
+    description: |
+      This property indicates the SPI wiring configuration.
+
+      When this property is omitted, it is assumed that the device is using
+      'no-cs' wiring. When this property is present, it indicates that the
+      device is using one of the following wiring configurations:

Quoted 7 lines

...

Quoted 5 lines

I'd also really appreciate a dts example for a system
with one-channel-chain or two-channel-chain looks, given the second device may require different supplies etc. I have no impression in my head of how the dt would be constructed, so I'd like to see wht you have in mind.

...

Realized what I said doesn't make much sense. The peripherals can all have the same configuration and thus share CS, SCLK, and controller SDO. The wiring would be like the following

::

  +-----------------------+                               +-----------------+
  |         AD4134        |                               | SPI Controller  |
  |                       |                               |                 |
  |                       |                               |                 |
  | SPI interface    SCLK |<--------------------+---------| SCLK            |
  | for register       CS |<--------------------|-+-------| CS              |
  | access            SDI |<--------------------|-|-+-----| SDO             |
  |                   SDO |------->|¯¯¯¯\       | | |     |                 |
  |                       |        |MUX  >------|-|-|---->| SDI0            |
  | Data interface  DOUT0 |------->|____/<------|-|-|---- | GPIO            |
  | for ADC sample  DOUT1 |---------------------|-|-|---->| SDI1            |
  | data read        DCLK |<-------------+------|-|-|-----| DCLK            |
  |                 DOUT2 |<-+           |      | | |     |                 |
  |                 DOUT3 |<-|-+         |      | | |     |                 |
  |                   ODR |<-|-|---------|--+   | | |  +->| Offload Trigger |
  +-----------------------+  | |         |  |   | | |  |  +-----------------+
                             | |         |  |   | | |  +--| PWM1            |
                             | |         |  +---| | | ----| PWM0            |
                             | |         |  |   | | |    +-----------------+
                             | |         |  |   | | |
  +-----------------------+  | |         |  |   | | |
  |         AD4134        |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  | SPI interface         |  | |         |  |   | | |
  | for register     SCLK |<-|-|---------|--|---+ | |
  | access             CS |<-|-|---------|--|---|-+ |
  |                   SDI |<-|-|---------|--|---|-|-+
  |                   SDO |  | |         |  |   | | |
  | Data interface        |  | |         |  |   | | |
  | for ADC sample  DOUT0 |--+ |         |  |   | | |
  | data read       DOUT1 |----+         |  |   | | |
  |                 DOUT2 |<-+           |  |   | | |
  |                 DOUT3 |<-|-+         |  |   | | |
  |                  DCLK |<-|-|---------+  |   | | |
  |                   ODR |<-|-|---------|--+   | | |
  +-----------------------+  | |         |  |   | | |
                             | |         |  |   | | |
                             | |         |  |   | | |
                             | |         |  |   | | |
  +-----------------------+  | |         |  |   | | |
  |         AD4134        |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  | SPI interface    SCLK |<-|-|---------|--|---+ | |
  | for register       CS |<-|-|---------|--|-----+ |
  | access            SDI |<-|-|---------|--|-------+
  |                       |  | |         |  |
  | Data interface        |  | |         |  |
  | for ADC sample  DOUT0 |--+ |         |  |
  | data read       DOUT1 |----+         |  |
  |                 DOUT2 |              |  |
  |                 DOUT3 |              |  |
  |                  DCLK |<-------------+  |
  |                   ODR |<----------------+
  +-----------------------+

So we would set them as only one daisy-chained device.

    spi {
        ...
        adc@0 {
            compatible = "adi,ad4134";
            reg = <0>;
            spi-rx-bus-width = <1>, <1>; /* 2 lanes of 1 bit each */

            <supplies, clock, and other properties ...> 

            #daisy-chained-devices = <2>;

            adi,spi-mode = "two-channel-chain";

Quoted 110 lines · Marcelo Schmitt

Quoted 28 lines · Marcelo Schmitt

Quoted 17 lines · Conor Dooley

Quoted 16 lines · Marcelo Schmitt

Document how AD4134 chips are connected to the host SPI controller according to different wiring configurations.

Signed-off-by Marcelo Schmitt <[email protected]>

---
 .../bindings/iio/adc/adi,ad4134.yaml          | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +0 -0

index ea6d7e026419..d843c02a394a 100644
@@ -131,6 +131,28 @@ properties:
     enum: [ free-running, gated ]
     default: gated
 

Quoted 10 lines

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml properties: · line 142

Quoted 9 lines

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +9 -0

+  adi,spi-mode:
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [ no-cs, 4-wire, one-channel-chain, two-channel-chain ]
+    description: |
+      This property indicates the SPI wiring configuration.
+
+      When this property is omitted, it is assumed that the device is using
+      'no-cs' wiring. When this property is present, it indicates that the
+      device is using one of the following wiring configurations:

Quoted 7 lines

...

Quoted 5 lines

I'd also really appreciate a dts example for a system
with one-channel-chain or two-channel-chain looks, given the second device may require different supplies etc. I have no impression in my head of how the dt would be constructed, so I'd like to see wht you have in mind.

...

Realized what I said doesn't make much sense. The peripherals can all have the same configuration and thus share CS, SCLK, and controller SDO. The wiring would be like the following

::

  +-----------------------+                               +-----------------+
  |         AD4134        |                               | SPI Controller  |
  |                       |                               |                 |
  |                       |                               |                 |
  | SPI interface    SCLK |<--------------------+---------| SCLK            |
  | for register       CS |<--------------------|-+-------| CS              |
  | access            SDI |<--------------------|-|-+-----| SDO             |
  |                   SDO |------->|¯¯¯¯\       | | |     |                 |
  |                       |        |MUX  >------|-|-|---->| SDI0            |
  | Data interface  DOUT0 |------->|____/<------|-|-|---- | GPIO            |
  | for ADC sample  DOUT1 |---------------------|-|-|---->| SDI1            |
  | data read        DCLK |<-------------+------|-|-|-----| DCLK            |
  |                 DOUT2 |<-+           |      | | |     |                 |
  |                 DOUT3 |<-|-+         |      | | |     |                 |
  |                   ODR |<-|-|---------|--+   | | |  +->| Offload Trigger |
  +-----------------------+  | |         |  |   | | |  |  +-----------------+
                             | |         |  |   | | |  +--| PWM1            |
                             | |         |  +---| | | ----| PWM0            |
                             | |         |  |   | | |    +-----------------+
                             | |         |  |   | | |
  +-----------------------+  | |         |  |   | | |
  |         AD4134        |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  | SPI interface         |  | |         |  |   | | |
  | for register     SCLK |<-|-|---------|--|---+ | |
  | access             CS |<-|-|---------|--|---|-+ |
  |                   SDI |<-|-|---------|--|---|-|-+
  |                   SDO |  | |         |  |   | | |
  | Data interface        |  | |         |  |   | | |
  | for ADC sample  DOUT0 |--+ |         |  |   | | |
  | data read       DOUT1 |----+         |  |   | | |
  |                 DOUT2 |<-+           |  |   | | |
  |                 DOUT3 |<-|-+         |  |   | | |
  |                  DCLK |<-|-|---------+  |   | | |
  |                   ODR |<-|-|---------|--+   | | |
  +-----------------------+  | |         |  |   | | |
                             | |         |  |   | | |
                             | |         |  |   | | |
                             | |         |  |   | | |
  +-----------------------+  | |         |  |   | | |
  |         AD4134        |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  | SPI interface    SCLK |<-|-|---------|--|---+ | |
  | for register       CS |<-|-|---------|--|-----+ |
  | access            SDI |<-|-|---------|--|-------+
  |                       |  | |         |  |
  | Data interface        |  | |         |  |
  | for ADC sample  DOUT0 |--+ |         |  |
  | data read       DOUT1 |----+         |  |
  |                 DOUT2 |              |  |
  |                 DOUT3 |              |  |
  |                  DCLK |<-------------+  |
  |                   ODR |<----------------+
  +-----------------------+

So we would set them as only one daisy-chained device.

    spi {
        ...
        adc@0 {
            compatible = "adi,ad4134";
            reg = <0>;
            spi-rx-bus-width = <1>, <1>; /* 2 lanes of 1 bit each */

Quoted 3 lines

<supplies, clock, and other properties ...>

#daisy-chained-devices = <2>;

Does this property actually provide value here? I assume it does because otherwise you don't know how many devices there are.

Quoted 2 lines

            adi,spi-mode = "two-channel-chain";

How does this interact with spi-rx-bus-width? Is the value of this consistent with adi,spi-mode? IOW, for adi,spi-mode = "one.." will there only ever be Dout0 connected to the host and for adi,spi-mode = "two.." will Dout1 and Dout0 both be connected?

Hello Conor, sorry for delayed reply.

Quoted 111 lines · Conor Dooley

Quoted 110 lines · Marcelo Schmitt

Quoted 28 lines · Marcelo Schmitt

Quoted 17 lines · Conor Dooley

Quoted 16 lines · Marcelo Schmitt

Document how AD4134 chips are connected to the host SPI controller according to different wiring configurations.

Signed-off-by Marcelo Schmitt <[email protected]>

---
 .../bindings/iio/adc/adi,ad4134.yaml          | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +0 -0

index ea6d7e026419..d843c02a394a 100644
@@ -131,6 +131,28 @@ properties:
     enum: [ free-running, gated ]
     default: gated
 

Quoted 10 lines

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml properties: · line 142

Quoted 9 lines

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +9 -0

+  adi,spi-mode:
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [ no-cs, 4-wire, one-channel-chain, two-channel-chain ]
+    description: |
+      This property indicates the SPI wiring configuration.
+
+      When this property is omitted, it is assumed that the device is using
+      'no-cs' wiring. When this property is present, it indicates that the
+      device is using one of the following wiring configurations:

Quoted 7 lines

...

Quoted 5 lines

I'd also really appreciate a dts example for a system
with one-channel-chain or two-channel-chain looks, given the second device may require different supplies etc. I have no impression in my head of how the dt would be constructed, so I'd like to see wht you have in mind.

...

Realized what I said doesn't make much sense. The peripherals can all have the same configuration and thus share CS, SCLK, and controller SDO. The wiring would be like the following

::

  +-----------------------+                               +-----------------+
  |         AD4134        |                               | SPI Controller  |
  |                       |                               |                 |
  |                       |                               |                 |
  | SPI interface    SCLK |<--------------------+---------| SCLK            |
  | for register       CS |<--------------------|-+-------| CS              |
  | access            SDI |<--------------------|-|-+-----| SDO             |
  |                   SDO |------->|¯¯¯¯\       | | |     |                 |
  |                       |        |MUX  >------|-|-|---->| SDI0            |
  | Data interface  DOUT0 |------->|____/<------|-|-|---- | GPIO            |
  | for ADC sample  DOUT1 |---------------------|-|-|---->| SDI1            |
  | data read        DCLK |<-------------+------|-|-|-----| DCLK            |
  |                 DOUT2 |<-+           |      | | |     |                 |
  |                 DOUT3 |<-|-+         |      | | |     |                 |
  |                   ODR |<-|-|---------|--+   | | |  +->| Offload Trigger |
  +-----------------------+  | |         |  |   | | |  |  +-----------------+
                             | |         |  |   | | |  +--| PWM1            |
                             | |         |  +---| | | ----| PWM0            |
                             | |         |  |   | | |    +-----------------+
                             | |         |  |   | | |
  +-----------------------+  | |         |  |   | | |
  |         AD4134        |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  | SPI interface         |  | |         |  |   | | |
  | for register     SCLK |<-|-|---------|--|---+ | |
  | access             CS |<-|-|---------|--|---|-+ |
  |                   SDI |<-|-|---------|--|---|-|-+
  |                   SDO |  | |         |  |   | | |
  | Data interface        |  | |         |  |   | | |
  | for ADC sample  DOUT0 |--+ |         |  |   | | |
  | data read       DOUT1 |----+         |  |   | | |
  |                 DOUT2 |<-+           |  |   | | |
  |                 DOUT3 |<-|-+         |  |   | | |
  |                  DCLK |<-|-|---------+  |   | | |
  |                   ODR |<-|-|---------|--+   | | |
  +-----------------------+  | |         |  |   | | |
                             | |         |  |   | | |
                             | |         |  |   | | |
                             | |         |  |   | | |
  +-----------------------+  | |         |  |   | | |
  |         AD4134        |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  |                       |  | |         |  |   | | |
  | SPI interface    SCLK |<-|-|---------|--|---+ | |
  | for register       CS |<-|-|---------|--|-----+ |
  | access            SDI |<-|-|---------|--|-------+
  |                       |  | |         |  |
  | Data interface        |  | |         |  |
  | for ADC sample  DOUT0 |--+ |         |  |
  | data read       DOUT1 |----+         |  |
  |                 DOUT2 |              |  |
  |                 DOUT3 |              |  |
  |                  DCLK |<-------------+  |
  |                   ODR |<----------------+
  +-----------------------+

So we would set them as only one daisy-chained device.

    spi {
        ...
        adc@0 {
            compatible = "adi,ad4134";
            reg = <0>;
            spi-rx-bus-width = <1>, <1>; /* 2 lanes of 1 bit each */

Quoted 6 lines

Quoted 3 lines

<supplies, clock, and other properties ...>

#daisy-chained-devices = <2>;

Does this property actually provide value here? I assume it does because otherwise you don't know how many devices there are.

Yes, the number of daisy-chained-devices is needed to determine how much data to transfer on ADC sample read. We already have some documentation in Documentation/devicetree/bindings/common-properties.txt

Quoted 7 lines

Quoted 2 lines

            adi,spi-mode = "two-channel-chain";

How does this interact with spi-rx-bus-width? Is the value of this consistent with adi,spi-mode? IOW, for adi,spi-mode = "one.." will there only ever be Dout0 connected to the host and for adi,spi-mode = "two.." will Dout1 and Dout0 both be connected?

For this particular ADC design, yes.
adi,spi-mode = "one-channel-chain" always expects spi-rx-bus-width = <1> (only DOUT0) and adi,spi-mode = "two-channel-chain" always expects spi-rx-bus-width = <1>, <1> (DOUT0, DOOUT1). Though, it is possible to have spi-rx-bus-width = <1> and
spi-rx-bus-width = <1>, <1> in non-chained setups.

Will make the constraints explicit on v2.

allOf:
...
- oneOf:
- required: [adi,spi-mode, '#daisy-chained-devices'] properties:
adi,spi-mode:
const: one-channel-chain
spi-rx-bus-width:
maxItems: 1

- required: [adi,spi-mode, '#daisy-chained-devices'] properties:
adi,spi-mode:
const: two-channel-chain
spi-rx-bus-width:
minItems: 2
maxItems: 2

- properties:
'#daisy-chained-devices': false

Best regards,
Marcelo

Quoted 27 lines · Conor Dooley

Quoted 25 lines · Marcelo Schmitt

Document how AD4134 chips are connected to the host SPI controller according to different wiring configurations.

Signed-off-by Marcelo Schmitt <[email protected]>

---
 .../bindings/iio/adc/adi,ad4134.yaml          | 22 +++++++++++++++++++
 1 file changed, 22 insertions(+)

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +9 -0

index ea6d7e026419..d843c02a394a 100644
@@ -131,6 +131,28 @@ properties:
     enum: [ free-running, gated ]
     default: gated
 
+  adi,spi-mode:
+    $ref: /schemas/types.yaml#/definitions/string
+    enum: [ no-cs, 4-wire, one-channel-chain, two-channel-chain ]
+    description: |
+      This property indicates the SPI wiring configuration.
+
+      When this property is omitted, it is assumed that the device is using
+      'no-cs' wiring. When this property is present, it indicates that the
+      device is using one of the following wiring configurations:  

...

Quoted 5 lines

I'd also really appreciate a dts example for a system
with one-channel-chain or two-channel-chain looks, given the second device may require different supplies etc. I have no impression in my head of how the dt would be constructed, so I'd like to see wht you have in mind.

I've added the daisy-chain modes for completeness. It has the same semantics of ad7944 (daisy-)chain, despite the wiring being different. It looks like the supplies for the chained devices are simply assumed to be there (unless I'm missing something?).

Though, now that I'm checking how to configure AD4134
for daisy-chain, I'm not sure how we could set them in dt. For 3 devices, we would have

    spi {
        ...
        adc@0 {
            compatible = "adi,ad4134";
            reg = <0>;
            spi-rx-bus-width = <1>, <1>; /* 2 lanes of 1 bit each */

            <supplies, clock, and other properties ...> 

            #daisy-chained-devices = <2>;

            adi,spi-mode = "4-wire";
        };
    };

But, the peripheral needs a register write to set the DOUT lines to 2-line daisy-chain and it doesn't seem to have register access propagation. So, we would need

    spi {
        ...
        adc@0 {
            compatible = "adi,ad4134";
            spi-rx-bus-width = <1>, <1>; /* 2 lanes of 1 bit each */

            <supplies, clock, and other properties ...> 

            #daisy-chained-devices = <2>;

            adi,spi-mode = "4-wire";
        };
        adc@1 {
            compatible = "adi,ad4134";
            <supplies, clock, and other properties ...> 

            adi,spi-mode = "4-wire";
        };
        adc@2 {
            compatible = "adi,ad4134";
            <supplies, clock, and other properties ...> 

            adi,spi-mode = "4-wire";
        };
    };

with adc@1 and adc@2 only set for register access. Even if not a dt-doc issue, that might (probably) lead to interface issues. The top of the daisy-chain may want to read from the other ADCs, but those could also be requested by IIO sysfs operations.

Quoted 15 lines

Quoted 5 lines

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +3 -0

+
+      * no-cs: The datasheet calls this "minimum I/O mode". In this mode, the CS
+        line is not used (tied to GND).

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml properties: · line 155

Quoted 10 lines

Documentation/devicetree/bindings/iio/adc/adi,ad4134.yaml +10 -0

+      * 4-wire: Specifies a conventional SPI wiring configuration.
+      * one-channel-chain: In this mode, the DOUT0 line of one chip is connected
+        to DOUT2 of the next chip upstream in the chain. Only the data interface
+        of the upmost device in the stream is in direct connection with the
+        digital host.
+      * two-channel-chain: In this mode, the DOUT0 and DOUT1 lines of one chip
+        are respectively connected to DOUT2 and DOUT3 of the next chip upstream
+        in the chain. Only the data interface of the upmost device in the stream
+        is in direct connection with the digital host.
+  

With best regards,
Marcelo

AD4134 devices can be wired in a few different ways. So far, only minimum I/O mode was supported. While minimum I/O mode allows interfacing with AD4134 with a reduced number of wires, that wiring configuration is not optimal for high-throughput data acquisition.

Extend AD4134 support to enable interfacing in SPI 4-wire configuration.

struct ad4134_state {

drivers/iio/adc/ad4134.c +6 -0

 	struct gpio_desc *odr_gpio;
 	int refin_mv;
 	bool crc_en;
+	enum ad4134_spi_mode spi_mode;
+	struct mux_state *mux_st[2];
 	/*
 	 * Synchronize access to members the of driver state, and ensure
 	 * atomicity of consecutive register access operations.
 	 */
 	struct mutex lock;
+	/*
+	 * Ensure atomicity of access mode switch operations.
+	 */
+	struct mutex access_mode_lock;
 
 };

(quoted diff) +2 -0

+	return 0;
+}

drivers/iio/adc/ad4134.c +32 -0

+	guard(mutex)(&st->access_mode_lock);
+	ret = mux_state_deselect(st->mux_st[AD4134_SDO_INPUT]);
+	if (ret)
+		dev_err(&st->spi->dev, "error on SDO deselect: %d\n", ret);
+
+	ret = mux_state_try_select(st->mux_st[AD4134_DOUT0_INPUT]);
+	if (ret) {
+		dev_err(&st->spi->dev, "error on DOUT0 select: %d\n", ret);
+		return mux_state_select(st->mux_st[AD4134_SDO_INPUT]);
+	}
+
+	/*
+	 * Data output on the DOUT lines is sampled on the falling edge
+	 * (SPI mode 1).
+	 */
+	st->spi->mode = SPI_MODE_1;
+	ret = spi_setup(st->spi);
+	if (ret) {
+		dev_err(&st->spi->dev, "failed to setup SPI mode 1: %d\n", ret);
+		ret2 = mux_state_deselect(st->mux_st[AD4134_DOUT0_INPUT]);
+		if (ret2)
+			dev_err(&st->spi->dev, "error on DOUT0 deselect: %d\n", ret2);
+
+		ret2 = mux_state_select(st->mux_st[AD4134_SDO_INPUT]);
+		if (ret2)
+			dev_err(&st->spi->dev, "error on SDO select: %d\n", ret2);
+
+		return ret;
+	}
+
+	return 0;
+}

static int ad4134_reg_read(void *context, unsigned int reg, unsigned int *val) {

drivers/iio/adc/ad4134.c +5 -2

 	struct ad4134_state *st = context;
+	int ret, ret2;
 
-	if (reg >= AD4134_CH_VREG(0))
-		return ad4134_data_read(st, reg, val);
+	if (reg >= AD4134_CH_VREG(0)) {
+		if (st->spi_mode == AD4134_SPI_MODE_4_WIRE) {
+			ret = ad4134_set_sample_access(st);
+			if (ret)

(quoted diff) +2 -0

+		return ret;
+	}

drivers/iio/adc/ad4134.c +5 -1

+		st->spi_mode = AD4134_SPI_MODE_NO_CS;
+	else if (ret < 0)
 		return dev_err_probe(dev, ret,
-				     "failed to setup minimum I/O mode\n");
+				     "getting adi,spi-mode property failed\n");
+	else
+		st->spi_mode = ret;

Make use of SPI transfer offloading to speed up data capture, enabling data acquisition at faster sample rates (up to 1.496 MSPS).

drivers/iio/adc/ad4134.c +21 -0

+	} while (count-- && odr_wf.duty_length_ns < odr_high_time_ns);
+
+	/* Check the minimum ODR high time is met */
+	if (odr_wf.duty_length_ns < odr_high_time_ns)
+		return -EDOM;
+
+	if (odr_wf.period_length_ns < 2 * odr_high_time_ns)
+		return -EDOM;
+
+	/*
+	 * Configure SPI offload PWM trigger.
+	 * For gated DCLK, the minimum required time between ODR rising edge
+	 * and DCLK rising edge is the sum of ODR high time and ODR falling
+	 * edge to DCLK rising edge time. Delay the offload trigger for at least
+	 * that amount of time so the ADC sample data will be available when the
+	 * SPI transfer begin.
+	 *
+	 * Use the same period as ODR PWM to avoid timing issues.
+	 * Convert back from period to frequency for the SPI offload API.
+	 */
+	offload_period_ns = odr_wf.period_length_ns;

drivers/iio/adc/ad4134.c +22 -0

+	} while (count-- && config.periodic.offset_ns < odr_high_time_ns +
+							AD4134_DCLK_RISING_OFFSET_NS);
+
+	/* Check the minimum ODR to DCLK delay is met */
+	if (config.periodic.offset_ns < odr_high_time_ns + AD4134_DCLK_RISING_OFFSET_NS)
+		return -EDOM;
+
+	/* Check the PWM periods remain the same */
+	offload_period_ns = DIV_ROUND_UP_ULL(HZ_PER_GHZ, config.periodic.frequency_hz);
+	if (odr_wf.period_length_ns != offload_period_ns)
+		return -EDOM;
+
+	ret = pwm_set_waveform_might_sleep(st->odr_pwm, &odr_wf, false);
+	if (ret)
+		return ret;
+
+	st->offload_trigger_config = config;
+	st->odr_wf = odr_wf;
+	st->odr_hz = DIV_ROUND_UP_ULL(NSEC_PER_SEC, odr_wf.period_length_ns);
+
+	return 0;
+}

drivers/iio/adc/ad4134.c +29 -0

+	if (st->spi_mode == AD4134_SPI_MODE_4_WIRE) {
+		ret = ad4134_set_sample_access(st);
+		if (ret)
+			return ret;
+	}
+
+	ad4134_prepare_offload_msg(indio_dev);
+	st->msg.offload = st->offload;
+	ret = spi_optimize_message(st->spi, &st->msg);
+	if (ret)
+		goto out_set_register_input;
+
+	ret = spi_offload_trigger_enable(st->offload, st->offload_trigger,
+					 &st->offload_trigger_config);
+	if (ret)
+		goto out_unoptimize;
+
+	return 0;
+
+out_unoptimize:
+	spi_unoptimize_message(&st->msg);
+
+out_set_register_input:
+	ret2 = ad4134_set_register_access(st);
+	if (ret2)
+		dev_err(&st->spi->dev, "reg input select error: %d\n", ret2);
+
+	return ret;
+}

drivers/iio/adc/ad4134.c +2 -0

+	0
+};