FAILED: patch "[PATCH] cxl/ras: Fix cxl_rch_get_aer_severity() wrong severity" failed to apply to 6.12-stable tree
Subsystems (2)
[email protected]
maintainerThe patch below does not apply to the 6.12-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-6.12.y
git checkout FETCH_HEAD
git cherry-pick -x 9d399526128bae184b153deab42b49f5f3eea2ed
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2026090317-roundish-company-df16@gregkh' --subject-prefix 'PATCH 6.12.y' 'HEAD^..'
Possible dependencies:
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 9d399526128bae184b153deab42b49f5f3eea2ed Mon Sep 17 00:00:00 2001
From: Terry Bowman <[email protected]>
Date: Mon, 3 Aug 2026 17:17:58 -0500
Subject: [PATCH] cxl/ras: Fix cxl_rch_get_aer_severity() wrong severity
register
cxl_rch_get_aer_severity() classifies RCH Downstream Port uncorrectable errors as fatal or non-fatal by ANDing uncorrectable status with PCI_ERR_ROOT_FATAL_RCV. This is wrong because PCI_ERR_ROOT_FATAL_RCV is a Root Error Status register bit (bit 6), not a severity bit. ANDing it against uncorrectable status tests a reserved bit and produces incorrect severity classification.
Fix by ANDing the unmasked uncor_status against uncor_severity. Per PCIe Base Spec r6.0 Section 7.8.4.4, each bit in the Uncorrectable Error Severity register indicates whether the corresponding error is fatal (1) or non-fatal (0).
drivers/cxl/core/ras_rch.c +5 -5
@@ -94,11 +94,11 @@ static bool cxl_rch_get_aer_info(void __iomem *aer_base,static bool cxl_rch_get_aer_severity (struct aer_capability_regs *aer_regs,int *severity) { -if (aer_regs->uncor_status & ~aer_regs->uncor_mask) { -if (aer_regs->uncor_status &PCI_ERR_ROOT_FATAL_RCV ) - *severity =AER_FATAL ; -else - *severity =AER_NONFATAL ; +u32 uncor_status = aer_regs->uncor_status & ~aer_regs->uncor_mask; + +if (uncor_status) { + *severity = (uncor_status & aer_regs->uncor_severity) ? +AER_FATAL :AER_NONFATAL ;return true; }
Sasha Levin
maintainerPATCH 1/4 cxl/pci: Remove unnecessary CXL Endpoint handling helper functions
From: Terry Bowman <[email protected]>
[ Upstream commit ca3d1a53e62093d17436abd447463da9c0f4e56b ]
The CXL driver's cxl_handle_endpoint_cor_ras()/cxl_handle_endpoint_ras() are unnecessary helper functions used only for Endpoints. Remove these functions as they are not common for all CXL devices and do not provide value for EP handling.
Rename __cxl_handle_ras to cxl_handle_ras() and __cxl_handle_cor_ras() to cxl_handle_cor_ras().
Stable-dep-of: 9d399526128b ("cxl/ras: Fix cxl_rch_get_aer_severity() wrong severity register")
--- drivers/cxl/core/pci.c | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-)
drivers/cxl/core/pci.c +8 -18
@@ -650,8 +650,8 @@ void read_cdat_data(struct cxl_port *port) }EXPORT_SYMBOL_NS_GPL (read_cdat_data,CXL ); -static void __cxl_handle_cor_ras (struct cxl_dev_state *cxlds, -void __iomem *ras_base) +static void cxl_handle_cor_ras (struct cxl_dev_state *cxlds, +void __iomem *ras_base) {void __iomem *addr;u32 status;
@@ -667,11 +667,6 @@ static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, } } -static void cxl_handle_endpoint_cor_ras (struct cxl_dev_state *cxlds) -{ -return __cxl_handle_cor_ras (cxlds, cxlds->regs.ras); -} -/* CXL spec rev3.0 8.2.4.16.1 */ static void header_log_copy (void __iomem *ras_base,u32 *log) {
@@ -693,8 +688,8 @@ static void header_log_copy(void __iomem *ras_base, u32 *log)* Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool __cxl_handle_ras (struct cxl_dev_state *cxlds, -void __iomem *ras_base) +static bool cxl_handle_ras (struct cxl_dev_state *cxlds, +void __iomem *ras_base) {u32 hl[CXL_HEADERLOG_SIZE_U32 ];void __iomem *addr;
@@ -727,11 +722,6 @@ static bool __cxl_handle_ras(struct cxl_dev_state *cxlds,return true; } -static bool cxl_handle_endpoint_ras (struct cxl_dev_state *cxlds) -{ -return __cxl_handle_ras (cxlds, cxlds->regs.ras); -} -#ifdef CONFIG_PCIEAER_CXL static void cxl_dport_map_rch_aer (struct cxl_dport *dport)
@@ -810,13 +800,13 @@ EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, CXL);static void cxl_handle_rdport_cor_ras (struct cxl_dev_state *cxlds,struct cxl_dport *dport) { -return __cxl_handle_cor_ras (cxlds, dport->regs.ras); +return cxl_handle_cor_ras (cxlds, dport->regs.ras); }static bool cxl_handle_rdport_ras (struct cxl_dev_state *cxlds,struct cxl_dport *dport) { -return __cxl_handle_ras (cxlds, dport->regs.ras); +return cxl_handle_ras (cxlds, dport->regs.ras); }/*
@@ -913,7 +903,7 @@ void cxl_cor_error_detected(struct pci_dev *pdev)if (cxlds->rcd)cxl_handle_rdport_errors (cxlds); -cxl_handle_endpoint_cor_ras (cxlds); +cxl_handle_cor_ras (cxlds, cxlds->regs.ras); } }EXPORT_SYMBOL_NS_GPL (cxl_cor_error_detected,CXL );
@@ -942,7 +932,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,* chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue =cxl_handle_endpoint_ras (cxlds); + ue =cxl_handle_ras (cxlds, cxlds->regs.ras); }
Signature · 1 line
2.53.0
Sasha Levin
maintainerPATCH 2/4 cxl/pci: Remove unnecessary CXL RCH handling helper functions
From: Terry Bowman <[email protected]>
[ Upstream commit eb78ef4d6f0e51243c1ee117f801dbc503e886ab ]
cxl_handle_rdport_cor_ras() and cxl_handle_rdport_ras() are specific to Restricted CXL Host (RCH) handling. Improve readability and maintainability by replacing these and instead using the common cxl_handle_cor_ras() and cxl_handle_ras() functions.
Stable-dep-of: 9d399526128b ("cxl/ras: Fix cxl_rch_get_aer_severity() wrong severity register")
--- drivers/cxl/core/pci.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-)
drivers/cxl/core/pci.c +2 -14
@@ -797,18 +797,6 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dport, struct device *host) }EXPORT_SYMBOL_NS_GPL (cxl_dport_init_ras_reporting,CXL ); -static void cxl_handle_rdport_cor_ras (struct cxl_dev_state *cxlds, -struct cxl_dport *dport) -{ -return cxl_handle_cor_ras (cxlds, dport->regs.ras); -} - -static bool cxl_handle_rdport_ras (struct cxl_dev_state *cxlds, -struct cxl_dport *dport) -{ -return cxl_handle_ras (cxlds, dport->regs.ras); -} -/* * Copy the AER capability registers using 32 bit read accesses. * This is necessary because RCRB AER capability is MMIO mapped. Clear the
@@ -878,9 +866,9 @@ static void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds)pci_print_aer (pdev, severity, &aer_regs);if (severity ==AER_CORRECTABLE ) -cxl_handle_rdport_cor_ras (cxlds, dport); +cxl_handle_cor_ras (cxlds, dport->regs.ras);else - cxl_handle_rdport_ras(cxlds, dport); + cxl_handle_ras(cxlds, dport->regs.ras); }#else
Signature · 1 line
2.53.0
Sasha Levin
maintainerPATCH 3/4 cxl/pci: Remove CXL VH handling in CONFIG_PCIEAER_CXL conditional blocks from core/pci.c
In reply to Sasha LevinFrom: Dave Jiang <[email protected]>
[ Upstream commit 7ff8b1d60881c5f97b5ae426e14d2822917d3b69 ]
Create new config CONFIG_CXL_RAS and put all CXL RAS items behind the config. The config will depend on CPER and PCIE AER to build. Move the related VH RAS code from core/pci.c to core/ras.c.
Restricted CXL host (RCH) RAS functions will be moved in a future patch.
[ Stable backport note: The 6.12 tree does not have the upstream CPER/GHES
ras.c base. Move only the existing VH handlers into ras.c and fold the later RCH split into ras_rch.c so the target fix applies there. ]
Stable-dep-of: 9d399526128b ("cxl/ras: Fix cxl_rch_get_aer_severity() wrong severity register")
--- drivers/cxl/Kconfig | 4 + drivers/cxl/core/Makefile | 2 + drivers/cxl/core/core.h | 23 +++ drivers/cxl/core/pci.c | 296 ------------------------------------- drivers/cxl/core/ras.c | 184 +++++++++++++++++++++++ drivers/cxl/core/ras_rch.c | 121 +++++++++++++++ drivers/cxl/cxl.h | 8 - drivers/cxl/cxlpci.h | 16 ++ tools/testing/cxl/Kbuild | 2 + 9 files changed, 352 insertions(+), 304 deletions(-) create mode 100644 drivers/cxl/core/ras.c create mode 100644 drivers/cxl/core/ras_rch.c
drivers/cxl/Kconfig +4 -0
@@ -146,4 +146,8 @@ config CXL_REGION_INVALIDATION_TEST If unsure, or if this kernel is meant for production environments, say N. +config CXL_RAS + def_bool y + depends on ACPI_APEI_GHES && PCIEAER && CXL_PCI + endif
drivers/cxl/core/Makefile +2 -0
@@ -16,3 +16,5 @@ cxl_core-y += pmu.o cxl_core-y += cdat.o cxl_core-$(CONFIG_TRACING) += trace.o cxl_core-$(CONFIG_CXL_REGION) += region.o +cxl_core-$(CONFIG_CXL_RAS) += ras.o +cxl_core-$(CONFIG_CXL_RAS) += ras_rch.o
drivers/cxl/core/core.h +23 -0
@@ -8,6 +8,8 @@ extern const struct device_type cxl_nvdimm_bridge_type;extern const struct device_type cxl_nvdimm_type;extern const struct device_type cxl_pmu_type; +struct cxl_dev_state ; +extern struct attribute_group cxl_base_attribute_group;#ifdef CONFIG_CXL_REGION
@@ -110,4 +112,25 @@ bool cxl_need_node_perf_attrs_update(int nid);int cxl_port_get_switch_dport_bandwidth (struct cxl_port *port,struct access_coordinate *c); +#ifdef CONFIG_CXL_RAS +bool cxl_handle_ras (struct cxl_dev_state *cxlds,void __iomem *ras_base); +void cxl_handle_cor_ras (struct cxl_dev_state *cxlds,void __iomem *ras_base); + +/* Restricted CXL Host specific RAS functions */ +void cxl_dport_map_rch_aer (struct cxl_dport *dport); +void cxl_disable_rch_root_ints (struct cxl_dport *dport); +void cxl_handle_rdport_errors (struct cxl_dev_state *cxlds); +#else +static inline bool cxl_handle_ras (struct cxl_dev_state *cxlds, +void __iomem *ras_base) +{ +return false; +} +static inline void cxl_handle_cor_ras (struct cxl_dev_state *cxlds, +void __iomem *ras_base) { } +static inline void cxl_dport_map_rch_aer (struct cxl_dport *dport) { } +static inline void cxl_disable_rch_root_ints (struct cxl_dport *dport) { } +static inline void cxl_handle_rdport_errors (struct cxl_dev_state *cxlds) { } +#endif /* CONFIG_CXL_RAS */ +#endif /* __CXL_CORE_H__ */
drivers/cxl/core/pci.c +0 -296
302 lines not on this page · raw message
drivers/cxl/core/ras.c new file +184 -0
184 lines not on this page · raw message
drivers/cxl/core/ras_rch.c new file +121 -0
121 lines not on this page · raw message
drivers/cxl/cxl.h +0 -8
@@ -763,14 +763,6 @@ struct cxl_dport *devm_cxl_add_rch_dport(struct cxl_port *port, struct device *dport_dev, int port_id, resource_size_t rcrb); -#ifdef CONFIG_PCIEAER_CXL -void cxl_setup_parent_dport (struct device *host,struct cxl_dport *dport); -void cxl_dport_init_ras_reporting (struct cxl_dport *dport,struct device *host); -#else -static inline void cxl_dport_init_ras_reporting (struct cxl_dport *dport, -struct device *host) { } -#endif -struct cxl_decoder *to_cxl_decoder (struct device *dev);struct cxl_root_decoder *to_cxl_root_decoder (struct device *dev);struct cxl_switch_decoder *to_cxl_switch_decoder (struct device *dev);
drivers/cxl/cxlpci.h +16 -0
@@ -126,7 +126,23 @@ struct cxl_dev_state;int cxl_hdm_decode_init (struct cxl_dev_state *cxlds,struct cxl_hdm *cxlhdm,struct cxl_endpoint_dvsec_info *info);void read_cdat_data (struct cxl_port *port); + +#ifdef CONFIG_CXL_RAS void cxl_cor_error_detected (struct pci_dev *pdev);pci_ers_result_t cxl_error_detected (struct pci_dev *pdev,pci_channel_state_t state); +void cxl_dport_init_ras_reporting (struct cxl_dport *dport,struct device *host); +#else +static inline void cxl_cor_error_detected (struct pci_dev *pdev) { } + +static inline pci_ers_result_t cxl_error_detected (struct pci_dev *pdev, +pci_channel_state_t state) +{ +return PCI_ERS_RESULT_NONE ; +} + +static inline void cxl_dport_init_ras_reporting (struct cxl_dport *dport, +struct device *host) { } +#endif +#endif /* __CXL_PCI_H__ */
tools/testing/cxl/Kbuild +2 -0
@@ -63,6 +63,8 @@ cxl_core-y += $(CXL_CORE_SRC)/pmu.o cxl_core-y += $(CXL_CORE_SRC)/cdat.o cxl_core-$(CONFIG_TRACING) += $(CXL_CORE_SRC)/trace.o cxl_core-$(CONFIG_CXL_REGION) += $(CXL_CORE_SRC)/region.o +cxl_core-$(CONFIG_CXL_RAS) += $(CXL_CORE_SRC)/ras.o +cxl_core-$(CONFIG_CXL_RAS) += $(CXL_CORE_SRC)/ras_rch.o cxl_core-y += config_check.o cxl_core-y += cxl_core_test.o cxl_core-y += cxl_core_exports.o
Signature · 1 line
2.53.0
Sasha Levin
maintainerPATCH 4/4 cxl/ras: Fix cxl_rch_get_aer_severity() wrong severity register
In reply to Sasha LevinFrom: Terry Bowman <[email protected]>
[ Upstream commit 9d399526128bae184b153deab42b49f5f3eea2ed ]
cxl_rch_get_aer_severity() classifies RCH Downstream Port uncorrectable errors as fatal or non-fatal by ANDing uncorrectable status with PCI_ERR_ROOT_FATAL_RCV. This is wrong because PCI_ERR_ROOT_FATAL_RCV is a Root Error Status register bit (bit 6), not a severity bit. ANDing it against uncorrectable status tests a reserved bit and produces incorrect severity classification.
Fix by ANDing the unmasked uncor_status against uncor_severity. Per PCIe Base Spec r6.0 Section 7.8.4.4, each bit in the Uncorrectable Error Severity register indicates whether the corresponding error is fatal (1) or non-fatal (0).
--- drivers/cxl/core/ras_rch.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
drivers/cxl/core/ras_rch.c +5 -5
@@ -79,11 +79,11 @@ static bool cxl_rch_get_aer_info(void __iomem *aer_base,static bool cxl_rch_get_aer_severity (struct aer_capability_regs *aer_regs,int *severity) { -if (aer_regs->uncor_status & ~aer_regs->uncor_mask) { -if (aer_regs->uncor_status &PCI_ERR_ROOT_FATAL_RCV ) - *severity =AER_FATAL ; -else - *severity =AER_NONFATAL ; +u32 uncor_status = aer_regs->uncor_status & ~aer_regs->uncor_mask; + +if (uncor_status) { + *severity = (uncor_status & aer_regs->uncor_severity) ? +AER_FATAL :AER_NONFATAL ;return true; }
Signature · 1 line
2.53.0