ARM: errata: document Cortex-A9 r4 as affected by erratum 754322
PATCH 1/1 ARM: errata: document Cortex-A9 r4 as affected by erratum 754322
The Cortex-A9 r4 Software Developers Errata Notice (ARM UAN 0009D), section 2.3.3, lists erratum 754322 as affecting all r2, r3 and r4 revisions. The Kconfig help text currently mentions only r2 and r3.
Add r4p* to the affected revisions so that users configuring Cortex-A9 r4 systems know that the workaround also applies to them.
--- arch/arm/Kconfig | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
arch/arm/Kconfig +6 -5
@@ -708,11 +708,12 @@ config ARM_ERRATA_754322 depends on CPU_V7 help This option enables the workaround for the 754322 Cortex-A9 (r2p*, - r3p*) erratum. A speculative memory access may cause a page table walk - which starts prior to an ASID switch but completes afterwards. This - can populate the micro-TLB with a stale entry which may be hit with - the new ASID. This workaround places two dsb instructions in the mm - switching code so that no page table walks can cross the ASID switch. + r3p*,r4p*) erratum. A speculative memory access may cause a page table + walk which starts prior to an ASID switch but completes afterwards. + This can populate the micro-TLB with a stale entry which may be hit + with the new ASID. This workaround places two dsb instructions in the + mm switching code so that no page table walks can cross the ASID + switch. config ARM_ERRATA_754327 bool "ARM errata: no automatic Store Buffer drain"
Signature · 1 line
2.43.0
Quoted 8 lines · Qingfang Deng
The Cortex-A9 r4 Software Developers Errata Notice (ARM UAN 0009D), section 2.3.3, lists erratum 754322 as affecting all r2, r3 and r4 revisions. The
Kconfighelp text currently mentions only r2 and r3.Add r4p* to the affected revisions so that users configuring Cortex-A9 r4 systems know that the workaround also applies to them.
The document you link to says:
Fault Status: Present in: All r2, r3 and r4 revisions. Open
The "Open" part means this isn't fixed, and so we have no idea whether this could afect a hypothetical r5, etc. Listing all the affected versions is a bad idea as it wil just lead to needless churn...
Quoted 1 line
Fixes fcbdc5fe6ebe ("ARM: 6772/1: errata: possible fault MMU translations following an ASID switch")
I don't beleive a fixes tag is necessary. The code works regardless of what the documentation says.
Quoted 14 lines
Signed-off-by Qingfang Deng <[email protected]>--- arch/arm/Kconfig | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)arch/arm/Kconfig +0
-1@@ -708,11 +708,12 @@ config ARM_ERRATA_754322 depends on CPU_V7 help This option enables the workaround for the 754322 Cortex-A9 (r2p*, - r3p*) erratum. A speculative memory access may cause a page table walk
arch/arm/Kconfig config ARM_ERRATA_754322 · line 716
Quoted 10 lines
arch/arm/Kconfig +6
-4- which starts prior to an ASID switch but completes afterwards. This - can populate the micro-TLB with a stale entry which may be hit with - the new ASID. This workaround places two dsb instructions in the mm - switching code so that no page table walks can cross the ASID switch. + r3p*,r4p*) erratum. A speculative memory access may cause a page table + walk which starts prior to an ASID switch but completes afterwards. + This can populate the micro-TLB with a stale entry which may be hit + with the new ASID. This workaround places two dsb instructions in the + mm switching code so that no page table walks can cross the ASID + switch.
If you want to change this, you could say "r2p* and later", but TBH I think we can just leave this as-is.
Mark.
Quoted 7 lines
arch/arm/Kconfig +0
-0config ARM_ERRATA_754327 bool "ARM errata: no automatic Store Buffer drain"Signature · 1 line
2.43.0