arm64: dts: socfpga: enable SD UHS and eMMC DDR modes on Agilex5/Agilex3 SoCDK
cover arm64: dts: socfpga: enable SD UHS and eMMC DDR modes on Agilex5/Agilex3 SoCDK
From: Tze Yee Ng <[email protected]>
This series enables higher-speed SD/MMC modes on the Agilex5 and Agilex3 SoC development kits.
Patch 1 adds the shared DDR50 read-path tuning defaults to the Agilex5 sdmmc node (also inherited by Agilex3). Patches 2-3 enable SD DDR50 and 1.8V eMMC DDR on the Agilex5 SoCDK. Patches 4-6 bring up the micro-SD slot (regulators + SDR104/DDR50) on the Agilex5 SoCDK modular, Agilex5 SoCDK 013B and Agilex3 SoCDK.
Depends on the SD6HC DDR read-path tuning series [1], which adds the sdhci-cadence driver and the dt-bindings for the cdns,ddr50-* properties used here; please apply it first.
[1] https://lore.kernel.org/all/[email protected]/
Tze Yee Ng (6):
arm64: dts: socfpga: agilex5: add DDR50 read-path tuning to sdmmc
arm64: dts: socfpga: agilex5: enable SD UHS DDR50 on SoCDK
arm64: dts: socfpga: agilex5: enable eMMC 1.8V DDR on SoCDK eMMC
arm64: dts: socfpga: agilex5: enable SD card on SoCDK modular
arm64: dts: socfpga: agilex5: enable SD card on SoCDK 013B
arm64: dts: socfpga: agilex3: enable SD card on SoCDK
.../boot/dts/intel/socfpga_agilex3_socdk.dts | 33 ++++++++++++++ .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 + .../boot/dts/intel/socfpga_agilex5_socdk.dts | 1 + .../dts/intel/socfpga_agilex5_socdk_013b.dts | 33 ++++++++++++++ .../dts/intel/socfpga_agilex5_socdk_emmc.dts | 1 + .../intel/socfpga_agilex5_socdk_modular.dts | 44 +++++++++++++++++++ 6 files changed, 114 insertions(+)
Signature · 1 line
2.43.7
PATCH 1/6 arm64: dts: socfpga: agilex5: add DDR50 read-path tuning to sdmmc
From: Tze Yee Ng <[email protected]>
Add the Cadence SD6HC DDR50 read-path tuning properties to the shared Agilex5 sdmmc node so that boards enabling SD UHS DDR50 pick up sane defaults for the loopback DQS selection and the read DQS delay:
- cdns,ddr50-use-lpbk-dqs = <0>
- cdns,ddr50-read-dqs-delay = <96>
--- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 ++ 1 file changed, 2 insertions(+)
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +2 -0
@@ -322,6 +322,8 @@ sdmmc: mmc@10808000 { resets = <&rst SDMMC_RESET>, <&rst COMBOPHY_RESET>, <&rst SDMMC_OCP_RESET>; reset-names = "sdhc-reset", "combophy", "sdmmc-ocp"; + cdns,ddr50-use-lpbk-dqs = <0>; + cdns,ddr50-read-dqs-delay = <96>; status = "disabled"; };
Signature · 1 line
2.43.7
[email protected]
AI reviewRe: [PATCH 1/6] arm64: dts: socfpga: agilex5: add DDR50 read-path tuning to sdmmc
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Medium] dt: mmc: cdns,ddr50-* properties undocumented and unused --
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] dt: mmc: cdns,ddr50-* properties undocumented and unused
--
commit 980c0e02eef0135ea601c44b02d3683b9aeff804
Author: Tze Yee Ng <[email protected]>
arm64: dts: socfpga: agilex5: add DDR50 read-path tuning to sdmmc
Add the Cadence SD6HC DDR50 read-path tuning properties to the shared Agilex5 sdmmc node.
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi sdmmc: mmc@10808000 { · line 326
Quoted 10 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +2
-0@@ -322,6 +322,8 @@ sdmmc: mmc@10808000 { resets = <&rst SDMMC_RESET>, <&rst COMBOPHY_RESET>, <&rst SDMMC_OCP_RESET>; reset-names = "sdhc-reset", "combophy", "sdmmc-ocp"; + cdns,ddr50-use-lpbk-dqs = <0>; + cdns,ddr50-read-dqs-delay = <96>;
[Severity: Medium]
Are these cdns,ddr50-* properties documented in the device tree bindings or supported by the driver?
Adding undocumented properties to the device tree without accompanying binding documentation and driver support creates dead code and causes dtbs_check schema validation errors, since the corresponding binding (cdns,sd6hc.yaml) enforces
unevaluatedProperties: false.
Quoted 3 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +0
-0status = "disabled"; };
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1
Re: [PATCH 1/6] arm64: dts: socfpga: agilex5: add DDR50 read-path tuning to sdmmc
In reply to [email protected]Quoted 19 lines · On 9/23/26 03:22, [email protected] wrote:
From: Tze Yee Ng <[email protected]>
Add the Cadence SD6HC DDR50 read-path tuning properties to the shared Agilex5 sdmmc node so that boards enabling SD UHS DDR50 pick up sane defaults for the loopback DQS selection and the read DQS delay:
- cdns,ddr50-use-lpbk-dqs = <0>
- cdns,ddr50-read-dqs-delay = <96>Signed-off-by Tze Yee Ng <[email protected]>--- arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 ++ 1 file changed, 2 insertions(+)arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +0
-0
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi sdmmc: mmc@10808000 { · line 327
Quoted 6 lines
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +2
-0@@ -322,6 +322,8 @@ sdmmc: mmc@10808000 { resets = <&rst SDMMC_RESET>, <&rst COMBOPHY_RESET>, <&rst SDMMC_OCP_RESET>; reset-names = "sdhc-reset", "combophy", "sdmmc-ocp"; + cdns,ddr50-use-lpbk-dqs = <0>; + cdns,ddr50-read-dqs-delay = <96>;
These bindings haven't been accepted yet right?
Dinh
PATCH 2/6 arm64: dts: socfpga: agilex5: enable SD UHS DDR50 on SoCDK
In reply to [email protected]From: Tze Yee Ng <[email protected]>
The SoCDK SD interface already advertises SDR104. Add sd-uhs-ddr50 so the DDR50 UHS-I mode is available as well, using the DDR50 read-path tuning defaults from the SoC dtsi.
--- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 1 + 1 file changed, 1 insertion(+)
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts +1 -0
@@ -63,6 +63,7 @@ &sdmmc { disable-wp; max-frequency = <200000000>; no-mmc; + sd-uhs-ddr50; sd-uhs-sdr104; vmmc-supply = <&vmmc_reg>; vqmmc-supply = <&vqmmc_io_reg>;
Signature · 1 line
2.43.7
PATCH 3/6 arm64: dts: socfpga: agilex5: enable eMMC 1.8V DDR on SoCDK eMMC
In reply to [email protected]From: Tze Yee Ng <[email protected]>
Add mmc-ddr-1_8v to the eMMC variant so the controller can use the high-speed DDR (52 MHz) 1.8V eMMC mode in addition to the existing HS200/HS400 modes.
--- arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts | 1 + 1 file changed, 1 insertion(+)
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_emmc.dts +1 -0
@@ -63,6 +63,7 @@ &sdmmc { max-frequency = <200000000>; mmc-hs200-1_8v; mmc-hs400-1_8v; + mmc-ddr-1_8v; no-sd; no-sdio; non-removable;
Signature · 1 line
2.43.7
PATCH 4/6 arm64: dts: socfpga: agilex5: enable SD card on SoCDK modular
In reply to [email protected]From: Tze Yee Ng <[email protected]>
Enable the micro-SD slot on the Agilex5 SoCDK modular board:
- Add the fixed 3.3V card supply and the GPIO-controlled 1.8V/3.3V VQMMC I/O regulator driven by the on-SoM PCA9535 expander.
- Enable the I2C3 bus and describe the PCA9535 expander that gates the SD I/O voltage switch.
- Enable the sdmmc node in 4-bit mode with SDR104 and DDR50 UHS-I support, wire up the vmmc/vqmmc supplies, and set the board's DDR50 phony DQS timing.
--- .../intel/socfpga_agilex5_socdk_modular.dts | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+)
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts +44 -0
@@ -34,6 +34,24 @@ memory@80000000 { /* We expect the bootloader to fill in the reg */ reg = <0x0 0x80000000 0x0 0x0>; }; + + vqmmc_io_reg: regulator-1p8v { + compatible = "regulator-gpio"; + regulator-name = "sd-bus-io-power"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios = <&expander1 1 GPIO_ACTIVE_HIGH>; + states = <1800000 0x1>, + <3300000 0x0>; + }; + + vmmc_reg: regulator-fixed-3p3v { + compatible = "regulator-fixed"; + regulator-name = "card-power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; &gpio0 {
@@ -61,6 +79,32 @@ emac2_phy0: ethernet-phy@0 { }; }; +&i2c3 { + status = "okay"; + + expander1: gpio@27 { + compatible = "nxp,pca9535"; + reg = <0x27>; /* SoM expander address */ + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-mmc; + sd-uhs-ddr50; + sd-uhs-sdr104; + vmmc-supply = <&vmmc_reg>; + vqmmc-supply = <&vqmmc_io_reg>; + cdns,ddr50-phony-dqs-timing = <0>; + + status = "okay"; +}; + &osc1 { clock-frequency = <25000000>; };
Signature · 1 line
2.43.7
[email protected]
AI reviewRe: [PATCH 4/6] arm64: dts: socfpga: agilex5: enable SD card on SoCDK modular
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [Low] dtbs_check failure: unparsed cdns,ddr50-phony-dqs-timing property --
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dtbs_check failure: unparsed cdns,ddr50-phony-dqs-timing property --
commit 856f28d1f721f596d93f5b3cac3f410afa5e6dc8
Author: Tze Yee Ng <[email protected]>
arm64: dts: socfpga: agilex5: enable SD card on SoCDK modular
This commit enables the micro-SD slot on the Agilex5 SoCDK modular board by adding regulators, the PCA9535 expander, and configuring the sdmmc node.
Quoted 3 lines
- Enable the sdmmc node in 4-bit mode with SDR104 and DDR50 UHS-I support, wire up the vmmc/vqmmc supplies, and set the board's DDR50 phony DQS timing.
Is the claim about setting the DDR50 phony DQS timing accurate?
The added devicetree property doesn't appear to be parsed by the host driver, meaning this might not actually set the board's timing as intended.
Quoted 4 lines
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts +0
-0
[ ... ]
Quoted 1 line
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts +0
-0@@ -61,6 +79,32 @@ emac2_phy0: ethernet-phy@0 {
[ ... ]
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts emac2_phy0: ethernet-phy@0 { · line 103
Quoted 11 lines
+&sdmmc {
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts +10
-0+ bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-mmc; + sd-uhs-ddr50; + sd-uhs-sdr104; + vmmc-supply = <&vmmc_reg>; + vqmmc-supply = <&vqmmc_io_reg>; + cdns,ddr50-phony-dqs-timing = <0>;
[Severity: Low]
Does this property actually configure the hardware?
It appears cdns,ddr50-phony-dqs-timing does not exist in any Cadence SDHCI bindings and is completely unparsed by the driver in drivers/mmc/host/sdhci-cadence-phy-v6.c.
Since Cadence devicetree schemas strictly prohibit unevaluated properties, will this trigger dtbs_check validation errors when building the devicetree? It looks like the driver manages phony DQS logic internally, making this property dead code with no functional runtime impact.
Quoted 3 lines
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts +3
-0+ + status = "okay"; +};
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=4
PATCH 5/6 arm64: dts: socfpga: agilex5: enable SD card on SoCDK 013B
In reply to [email protected]From: Tze Yee Ng <[email protected]>
Enable the micro-SD slot on the Agilex5 SoCDK 013B board:
- Add the fixed 3.3V card supply and the GPIO-controlled 1.8V/3.3V VQMMC I/O regulator.
- Enable the sdmmc node in 4-bit mode with SDR104 and DDR50 UHS-I support and wire up the vmmc/vqmmc supplies.
--- .../dts/intel/socfpga_agilex5_socdk_013b.dts | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+)
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts +33 -0
@@ -39,6 +39,25 @@ memory@80000000 { /* We expect the bootloader to fill in the reg */ reg = <0x0 0x80000000 0x0 0x0>; }; + + vqmmc_io_reg: regulator-1p8v { + compatible = "regulator-gpio"; + gpios = <&portb 3 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vqmmc-io"; + states = <1800000 0x1>, + <3300000 0x0>; + }; + + vmmc_reg: regulator-fixed-3p3v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc-sd"; + }; }; &gmac2 {
@@ -115,6 +134,20 @@ root: partition@c00000 { }; }; +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-mmc; + sd-uhs-ddr50; + sd-uhs-sdr104; + vmmc-supply = <&vmmc_reg>; + vqmmc-supply = <&vqmmc_io_reg>; + + status = "okay"; +}; + &smmu { status = "okay"; };
Signature · 1 line
2.43.7
PATCH 6/6 arm64: dts: socfpga: agilex3: enable SD card on SoCDK
In reply to [email protected]From: Tze Yee Ng <[email protected]>
Enable the micro-SD slot on the Agilex3 SoCDK board:
- Add the fixed 3.3V card supply and the GPIO-controlled 1.8V/3.3V VQMMC I/O regulator.
- Enable the sdmmc node in 4-bit mode with SDR104 and DDR50 UHS-I support and wire up the vmmc/vqmmc supplies.
The board includes socfpga_agilex5.dtsi, so the DDR50 read-path tuning defaults added there apply here as well.
--- .../boot/dts/intel/socfpga_agilex3_socdk.dts | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+)
arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts +33 -0
@@ -45,6 +45,25 @@ memory@80000000 { /* We expect the bootloader to fill in the reg */ reg = <0x0 0x80000000 0x0 0x0>; }; + + vqmmc_io_reg: regulator-1p8v { + compatible = "regulator-gpio"; + gpios = <&portb 3 GPIO_ACTIVE_HIGH>; + gpios-states = <0>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vqmmc-io"; + states = <1800000 0x1>, + <3300000 0x0>; + }; + + vmmc_reg: regulator-fixed-3p3v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc-sd"; + }; }; &gmac2 {
@@ -121,6 +140,20 @@ root: partition@c00000 { }; }; +&sdmmc { + bus-width = <4>; + cap-sd-highspeed; + disable-wp; + max-frequency = <200000000>; + no-mmc; + sd-uhs-ddr50; + sd-uhs-sdr104; + vmmc-supply = <&vmmc_reg>; + vqmmc-supply = <&vqmmc_io_reg>; + + status = "okay"; +}; + &smmu { status = "okay"; };
Signature · 1 line
2.43.7
Quoted 17 lines · On 9/23/26 03:22, [email protected] wrote:
From: Tze Yee Ng <[email protected]>
This series enables higher-speed SD/MMC modes on the Agilex5 and Agilex3 SoC development kits.
Patch 1 adds the shared DDR50 read-path tuning defaults to the Agilex5 sdmmc node (also inherited by Agilex3). Patches 2-3 enable SD DDR50 and 1.8V eMMC DDR on the Agilex5 SoCDK. Patches 4-6 bring up the micro-SD slot (regulators + SDR104/DDR50) on the Agilex5 SoCDK modular, Agilex5 SoCDK 013B and Agilex3 SoCDK.
Depends on the SD6HC DDR read-path tuning series [1], which adds the sdhci-cadence driver and the dt-bindings for the cdns,ddr50-* properties used here; please apply it first.
Quoted 8 lines
Tze Yee Ng (6):
arm64: dts: socfpga: agilex5: add DDR50 read-path tuning to sdmmc
arm64: dts: socfpga: agilex5: enable SD UHS DDR50 on SoCDK
arm64: dts: socfpga: agilex5: enable eMMC 1.8V DDR on SoCDK eMMC
arm64: dts: socfpga: agilex5: enable SD card on SoCDK modular
arm64: dts: socfpga: agilex5: enable SD card on SoCDK 013B
arm64: dts: socfpga: agilex3: enable SD card on SoCDK
I can't take any of these until the SDMMC bindings are accepted.
Dinh