arm64: dts: allwinner: h616: orangepi-zero2w: add 24-pin expansion overlay
Subsystems (2)
PATCH v2 1/2 arm64: dts: allwinner: h616: orangepi-zero2w: add 24-pin expansion overlay
The optional 24-pin expansion board carries two buttons on LRADC channel 0 and an IR receiver. Keep them out of the base board .dts: with the board detached the LRADC input and the IR receiver pin are not driven and float, which can produce phantom key presses and interrupt storms.
Provide them as a devicetree overlay instead, following the existing sun8i-orangepi-zero-interface-board.dtso approach.
Tested on: OrangePi Zero 2W (Allwinner H618) with the 24-pin expansion board.
--- arch/arm64/boot/dts/allwinner/Makefile | 2 + .../sun50i-h618-orangepi-zero2w-24pin.dtso | 42 +++++++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w-24pin.dtso
arch/arm64/boot/dts/allwinner/Makefile +2 -0
@@ -57,6 +57,8 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-longanpi-3h.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w-24pin.dtb +sun50i-h618-orangepi-zero2w-24pin-dtbs := sun50i-h618-orangepi-zero2w.dtb sun50i-h618-orangepi-zero2w-24pin.dtbo dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-transpeed-8k618-t.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-yuzukihd-chameleon.dtb
arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w-24pin.dtso new file +42 -0
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Signature · 1 line
2.55.0.windows.3
PATCH v2 2/2 arm64: dts: allwinner: h616: orangepi-zero2w: add SDIO WiFi/BT (AW859A)
Enable the SDIO bus (mmc1) and power the on-board AW859A (UWE5622) WiFi/BT combo through an mmc-pwrseq-simple that resets WL_REG_ON (PG18), with the 3.3 V and 1.8 V supplies and the RTC 32 kHz clock.
Tested on: OrangePi Zero 2W (Allwinner H618) with the out-of-tree uwe5622 driver.
--- .../allwinner/sun50i-h618-orangepi-zero2w.dts | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+)
arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts +40 -0
@@ -189,3 +189,43 @@ &usbphy { usb1_vbus-supply = <®_vcc5v>; status = "okay"; }; + +/ { + reg_vcc33_wifi: vcc33-wifi { + /* Always-on 3.3V regulator for WiFi and BT */ + compatible = "regulator-fixed"; + regulator-name = "vcc33-wifi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <®_vcc5v>; + }; + + reg_vcc_wifi_io: vcc-wifi-io { + /* Always-on 1.8V regulator for WiFi and BT IO */ + compatible = "regulator-fixed"; + regulator-name = "vcc-wifi-io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <®_vcc33_wifi>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + clocks = <&rtc 1>; + clock-names = "osc32k-out"; + reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ + post-power-on-delay-ms = <200>; + }; +}; + +&mmc1 { + vmmc-supply = <®_vcc33_wifi>; + vqmmc-supply = <®_vcc_wifi_io>; + mmc-pwrseq = <&wifi_pwrseq>; + bus-width = <4>; + non-removable; + mmc-ddr-1_8v; + status = "okay"; +};
Signature · 1 line
2.55.0.windows.3
[email protected]
AI reviewRe: [PATCH v2 2/2] arm64: dts: allwinner: h616: orangepi-zero2w: add SDIO WiFi/BT (AW859A)
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider: - [High] dt: mmc-pwrseq-simple silent clock failure due to incorrect clock-names - [High] dt: missing…
Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] dt: mmc-pwrseq-simple silent clock failure due to incorrect clock-names
- [High] dt: missing pinctrl for RTC 32kHz clock output
- [Low] dt: use of magic number for RTC clock index
--
commit 97053bae21777f073acfc22535e6c83308625172
Author: Vladimir <[email protected]>
arm64: dts: allwinner: h616: orangepi-zero2w: add SDIO WiFi/BT (AW859A)
Enable the SDIO bus (mmc1) and power the on-board AW859A (UWE5622) WiFi/BT combo through an mmc-pwrseq-simple that resets WL_REG_ON (PG18), with the 3.3 V and 1.8 V supplies and the RTC 32 kHz clock.
Quoted 5 lines
arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts +0
-0@@ -189,3 +189,43 @@ &usbphy {
[ ... ]
arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts &usbphy { · line 215
Quoted 2 lines
arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts +2
-0+ wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple";
[Severity: High]
Does this node need pinctrl properties to physically route the 32kHz RTC fanout clock to its output pin (PG10)?
During the probing of the wifi_pwrseq node at boot, without specifying pinctrl-0 = <&x32clk_fanout_pin>; and pinctrl-names = "default";, the pin remains in its default state. This physically disconnects the clock signal from the external WiFi/BT chip.
arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts &usbphy { · line 216
Quoted 1 line
arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts +1
-0+ clocks = <&rtc 1>;
[Severity: Low]
Is it possible to use the CLK_OSC32K_FANOUT macro defined in include/dt-bindings/clock/sun6i-rtc.h here instead of the magic number 1?
This would improve readability and consistency with other Allwinner device trees.
arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts &usbphy { · line 217
Quoted 1 line
arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts +1
-0+ clock-names = "osc32k-out";
[Severity: High]
Does the mmc-pwrseq-simple driver expect the clock name to be exactly "ext_clock"?
When probing the wifi_pwrseq node, because this patch uses "osc32k-out", devm_clk_get(dev, "ext_clock") returns -ENOENT. The driver treats -ENOENT as an optional clock being absent and silently continues without enabling the 32kHz clock. This causes the WiFi/BT module to fail to initialize or operate reliably.
Quoted 4 lines
arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts +4
-0+ reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */ + post-power-on-delay-ms = <200>; + }; +};
Signature · 1 line
Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=2