arm64: dts: qcom: hamoa: add operating points for pcie4/5/6a
PATCH 1/1 arm64: dts: qcom: hamoa: add operating points for pcie4/5/6a
Similarly to pcie3, add operating-points-v2 tables for the controllers used for Wi-Fi cards, cellular modems and SSDs on X1E laptops.
Signed-off-by Val Packett <[email protected]>
---
I've had this in my tree for a few months, now that PCIe BW scaling work is picking up[1] this seems more relevant than ever..
Hopefully I've trimmed down the table correctly for each controller :) Tested with NVMe scaling patches[2] flipping the link between 2.5 and 16 GT/s quite frequently.
[1]: https://lore.kernel.org/all/[email protected]/
[2]: https://lore.kernel.org/all/[email protected]/
Thanks,
~val
--- arch/arm64/boot/dts/qcom/hamoa.dtsi | 213 +++++++++++++++++++++++++++- 1 file changed, 210 insertions(+), 3 deletions(-)
arch/arm64/boot/dts/qcom/hamoa.dtsi +210 -3
@@ -3516,13 +3516,114 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, "link_down"; power-domains = <&gcc GCC_PCIE_6A_GDSC>; - required-opps = <&rpmhpd_opp_nom>; eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>; + operating-points-v2 = <&pcie6a_opp_table>; + status = "disabled"; + pcie6a_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* 2.5GT/s x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* 2.5 GT/s x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* 2.5 GT/s x4 */ + opp-10000000-1 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <1>; + }; + + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x4 */ + opp-20000000-2 { + opp-hz = /bits/ 64 <20000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <2000000 1>; + opp-level = <2>; + }; + + /* 8 GT/s x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* 8 GT/s x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + + /* 8 GT/s x4 */ + opp-32000000-3 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <3>; + }; + + /* 16 GT/s x1 */ + opp-16000000-4 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <4>; + }; + + /* 16 GT/s x2 */ + opp-32000000-4 { + opp-hz = /bits/ 64 <32000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <3938000 1>; + opp-level = <4>; + }; + + /* 16 GT/s x4 */ + opp-64000000-4 { + opp-hz = /bits/ 64 <64000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <7876000 1>; + opp-level = <4>; + }; + }; + pcie6a_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>;
@@ -3657,12 +3758,65 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, "link_down"; power-domains = <&gcc GCC_PCIE_5_GDSC>; - required-opps = <&rpmhpd_opp_nom>; eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + operating-points-v2 = <&pcie5_opp_table>; + status = "disabled"; + pcie5_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* 2.5GT/s x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* 2.5 GT/s x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* 8 GT/s x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* 8 GT/s x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + }; + pcie5_port0: pcie@0 { device_type = "pci"; reg = <0x0 0x0 0x0 0x0 0x0>;
@@ -3796,12 +3950,65 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, "link_down"; power-domains = <&gcc GCC_PCIE_4_GDSC>; - required-opps = <&rpmhpd_opp_nom>; eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; + operating-points-v2 = <&pcie4_opp_table>; + status = "disabled"; + pcie4_opp_table: opp-table { + compatible = "operating-points-v2"; + + /* 2.5GT/s x1 */ + opp-2500000-1 { + opp-hz = /bits/ 64 <2500000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <250000 1>; + opp-level = <1>; + }; + + /* 2.5 GT/s x2 */ + opp-5000000-1 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <1>; + }; + + /* 5 GT/s x1 */ + opp-5000000-2 { + opp-hz = /bits/ 64 <5000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <500000 1>; + opp-level = <2>; + }; + + /* 5 GT/s x2 */ + opp-10000000-2 { + opp-hz = /bits/ 64 <10000000>; + required-opps = <&rpmhpd_opp_low_svs>; + opp-peak-kBps = <1000000 1>; + opp-level = <2>; + }; + + /* 8 GT/s x1 */ + opp-8000000-3 { + opp-hz = /bits/ 64 <8000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <984500 1>; + opp-level = <3>; + }; + + /* 8 GT/s x2 */ + opp-16000000-3 { + opp-hz = /bits/ 64 <16000000>; + required-opps = <&rpmhpd_opp_svs>; + opp-peak-kBps = <1969000 1>; + opp-level = <3>; + }; + }; + pcie4_port0: pcie@0 { compatible = "pciclass,0604"; device_type = "pci";
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2.55.0