iio: adc: Add TI ADS126X ADC family support

927 lines not on this page · raw message

index a54f78e88012..7a6fa009ddad 100644
@@ -24,6 +24,7 @@
 #include <linux/regulator/consumer.h>
 #include <linux/spi/spi.h>
 #include <linux/types.h>
+#include <linux/units.h>
 
 #include <asm/byteorder.h>
 

@@ -98,6 +99,7 @@
 #define     ADS1262_DR_14400_SPS		  13
 #define     ADS1262_DR_19200_SPS		  14
 #define     ADS1262_DR_38400_SPS		  15
+#define     ADS1262_DR_COUNT			  (ADS1262_DR_38400_SPS + 1)
 
 #define ADS1262_INPMUX_REG			0x06
 #define   ADS1262_INPMUX_MUXP_MASK		GENMASK(7, 4)

@@ -165,6 +167,7 @@
 #define ADS1262_POWER_TRANS_US			65536
 
 #define ADS1262_NOMINAL_CLK_RATE_HZ		7372800
+#define ADS1262_MODULATOR_DIV			8
 
 #define ADS1262_FW_CHANNEL_COUNT		16
 #define ADS1262_MON_CHANNEL_COUNT		4

@@ -176,16 +179,25 @@ struct ads1262_chip_info {
 	const char *name;
 };
 
+struct ads1262_channel {
+	u8 data_rate;
+	u8 filter;
+};
+
 struct ads1262 {
 	struct spi_device *spi;
 	struct regmap *regmap;
 	struct gpio_desc *start_gpiod;
+	size_t num_channels;
+	struct ads1262_channel *channels __counted_by_ptr(num_channels);
 	/* protects concurrent SPI transfers */
 	struct mutex xfer_lock;
 	/* protects channel state */
 	struct mutex chan_lock;
 	struct completion drdy;
 	unsigned long clk_rate_hz;
+	int sampling_freq_table[ADS1262_DR_COUNT][2];
+	int sampling_freq_fir[ADS1262_DR_16_6_SPS + 1][2];
 };
 
 static const struct iio_chan_spec ads1262_monitor_chan_specs[] = {

@@ -199,7 +211,9 @@ static const struct iio_chan_spec ads1262_monitor_chan_specs[] = {
 			.storagebits = 32,
 			.endianness = IIO_BE,
 		},
-		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+				      BIT(IIO_CHAN_INFO_SAMP_FREQ),
+		.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 	},
 	{
 		.type = IIO_VOLTAGE,

@@ -212,7 +226,9 @@ static const struct iio_chan_spec ads1262_monitor_chan_specs[] = {
 			.storagebits = 32,
 			.endianness = IIO_BE,
 		},
-		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+				      BIT(IIO_CHAN_INFO_SAMP_FREQ),
+		.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 	},
 	{
 		.type = IIO_VOLTAGE,

@@ -225,7 +241,9 @@ static const struct iio_chan_spec ads1262_monitor_chan_specs[] = {
 			.storagebits = 32,
 			.endianness = IIO_BE,
 		},
-		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+				      BIT(IIO_CHAN_INFO_SAMP_FREQ),
+		.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 	},
 	{
 		.type = IIO_VOLTAGE,

@@ -239,10 +257,66 @@ static const struct iio_chan_spec ads1262_monitor_chan_specs[] = {
 			.storagebits = 32,
 			.endianness = IIO_BE,
 		},
-		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
+		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+				      BIT(IIO_CHAN_INFO_SAMP_FREQ),
+		.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
 	},
 };
 
+#define ads1262_default_channel ((struct ads1262_channel) {	\
+	.data_rate = ADS1262_DR_20_SPS,				\
+	.filter = ADS1262_FILTER_FIR,				\
+})
+
+static const u32 ads1262_mod_decimator_a[] = {
+	[ADS1262_DR_2_5_SPS]	= 64,
+	[ADS1262_DR_5_SPS]	= 64,
+	[ADS1262_DR_10_SPS]	= 64,
+	[ADS1262_DR_16_6_SPS]	= 64,
+	[ADS1262_DR_20_SPS]	= 64,
+	[ADS1262_DR_50_SPS]	= 64,
+	[ADS1262_DR_60_SPS]	= 64,
+	[ADS1262_DR_100_SPS]	= 64,
+	[ADS1262_DR_400_SPS]	= 64,
+	[ADS1262_DR_1200_SPS]	= 64,
+	[ADS1262_DR_2400_SPS]	= 64,
+	[ADS1262_DR_4800_SPS]	= 64,
+	[ADS1262_DR_7200_SPS]	= 64,
+	[ADS1262_DR_14400_SPS]	= 64,
+	[ADS1262_DR_19200_SPS]	= 48,
+	[ADS1262_DR_38400_SPS]	= 24,
+};
+
+static const u32 ads1262_mod_decimator_b[] = {
+	[ADS1262_DR_2_5_SPS]	= 5760,
+	[ADS1262_DR_5_SPS]	= 2880,
+	[ADS1262_DR_10_SPS]	= 1440,
+	[ADS1262_DR_16_6_SPS]	= 864,
+	[ADS1262_DR_20_SPS]	= 720,
+	[ADS1262_DR_50_SPS]	= 288,
+	[ADS1262_DR_60_SPS]	= 240,
+	[ADS1262_DR_100_SPS]	= 144,
+	[ADS1262_DR_400_SPS]	= 36,
+	[ADS1262_DR_1200_SPS]	= 12,
+	[ADS1262_DR_2400_SPS]	= 6,
+	[ADS1262_DR_4800_SPS]	= 3,
+	[ADS1262_DR_7200_SPS]	= 2,
+	[ADS1262_DR_14400_SPS]	= 1,
+	[ADS1262_DR_19200_SPS]	= 1,
+	[ADS1262_DR_38400_SPS]	= 1,
+};
+
+static int ads1262_find_two(const int (*array)[2], size_t num_elements, int val,
+			    int val2)
+{
+	for (unsigned int i = 0; i < num_elements; i++) {
+		if (val == array[i][0] && val2 == array[i][1])
+			return i;
+	}
+
+	return -EINVAL;
+}
+
 static int ads1262_dev_send_cmd(struct ads1262 *st, u8 opcode)
 {
 	guard(mutex)(&st->xfer_lock);

@@ -367,9 +441,18 @@ static int ads1262_wait_for_conversion(struct ads1262 *st)
 static int ads1262_channel_enable(struct ads1262 *st,
 				  const struct iio_chan_spec *spec)
 {
+	struct ads1262_channel *chan = &st->channels[spec->scan_index];
+	int ret;
+
 	guard(mutex)(&st->xfer_lock);
 	guard(mutex)(&st->chan_lock);
 
+	ret = regmap_update_bits(st->regmap, ADS1262_MODE2_REG,
+				 ADS1262_MODE2_DR_MASK,
+				 FIELD_PREP(ADS1262_MODE2_DR_MASK, chan->data_rate));
+	if (ret)
+		return ret;
+
 	return regmap_update_bits(st->regmap, ADS1262_INPMUX_REG,
 				  ADS1262_INPMUX_MUXN_MASK |
 				  ADS1262_INPMUX_MUXP_MASK,

@@ -421,6 +504,8 @@ static int ads1262_read_raw(struct iio_dev *indio_dev,
 			    struct iio_chan_spec const *chan, int *val,
 			    int *val2, long mask)
 {
+	struct ads1262 *st = iio_priv(indio_dev);
+	struct ads1262_channel *chan_data = &st->channels[chan->scan_index];
 	__be32 raw;
 	int ret;
 

@@ -433,6 +518,83 @@ static int ads1262_read_raw(struct iio_dev *indio_dev,
 
 		return IIO_VAL_INT;
 
+	case IIO_CHAN_INFO_SAMP_FREQ: {
+		guard(mutex)(&st->chan_lock);
+
+		*val = st->sampling_freq_table[chan_data->data_rate][0];
+		*val2 = st->sampling_freq_table[chan_data->data_rate][1];
+
+		return IIO_VAL_INT_PLUS_MICRO;
+	}
+
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int ads1262_read_avail(struct iio_dev *indio_dev,
+			      struct iio_chan_spec const *chan, const int **vals,
+			      int *type, int *length, long mask)
+{
+	struct ads1262 *st = iio_priv(indio_dev);
+	struct ads1262_channel *chan_data = &st->channels[chan->scan_index];
+
+	switch (mask) {
+	case IIO_CHAN_INFO_SAMP_FREQ:
+		*type = IIO_VAL_INT_PLUS_MICRO;
+
+		switch (chan_data->filter) {
+		case ADS1262_FILTER_FIR:
+			*vals = (const int *)st->sampling_freq_fir;
+			*length = ARRAY_SIZE(st->sampling_freq_fir) * 2;
+			return IIO_AVAIL_LIST;
+		default:
+			return -EOPNOTSUPP;
+		}
+
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static int ads1262_write_raw(struct iio_dev *indio_dev,
+			     struct iio_chan_spec const *chan, int val,
+			     int val2, long mask)
+{
+	struct ads1262 *st = iio_priv(indio_dev);
+	struct ads1262_channel *chan_data = &st->channels[chan->scan_index];
+	int ret;
+
+	IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
+	if (IIO_DEV_ACQUIRE_FAILED(claim))
+		return -EBUSY;
+
+	guard(mutex)(&st->chan_lock);
+
+	switch (mask) {
+	case IIO_CHAN_INFO_SAMP_FREQ:
+		switch (chan_data->filter) {
+		case ADS1262_FILTER_FIR:
+			ret = ads1262_find_two(st->sampling_freq_fir,
+					       ARRAY_SIZE(st->sampling_freq_fir),
+					       val, val2);
+			if (ret < 0)
+				return ret;
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		ret = ads1262_find_two(st->sampling_freq_table,
+				       ARRAY_SIZE(st->sampling_freq_table),
+				       val, val2);
+		if (ret < 0)
+			return ret;
+
+		chan_data->data_rate = ret;
+
+		return 0;
+
 	default:
 		return -EOPNOTSUPP;
 	}

@@ -472,6 +634,8 @@ static int ads1262_fwnode_xlate(struct iio_dev *indio_dev,
 
 static const struct iio_info ads1262_iio_info = {
 	.read_raw = ads1262_read_raw,
+	.read_avail = ads1262_read_avail,
+	.write_raw = ads1262_write_raw,
 	.debugfs_reg_access = ads1262_debugfs_reg_access,
 	.fwnode_xlate = ads1262_fwnode_xlate,
 };

@@ -678,6 +842,49 @@ static const struct regmap_bus ads1262_regmap_bus = {
 	.max_raw_write = ADS1262_REGMAP_WRITE_SZ,
 };
 
+static void ads1262_populate_samp_freqs(struct ads1262 *st)
+{
+	u64 freq_Hz, freq_uHz;
+	u32 freq_rem;
+
+	for (unsigned int i = 0; i < ARRAY_SIZE(st->sampling_freq_table); i++) {
+		freq_uHz = div_u64(mul_u32_u32(st->clk_rate_hz, MICRO),
+				   ADS1262_MODULATOR_DIV *
+				   ads1262_mod_decimator_a[i] *
+				   ads1262_mod_decimator_b[i]);
+		freq_Hz = div_u64_rem(freq_uHz, MICRO, &freq_rem);
+
+		st->sampling_freq_table[i][0] = (int)freq_Hz;
+		st->sampling_freq_table[i][1] = (int)freq_rem;
+	}
+
+	for (unsigned int i = 0; i < ARRAY_SIZE(st->sampling_freq_fir); i++) {
+		/*
+		 * The FIR filter does not support the 16.6 SPS data rate so it
+		 * gets mapped to 20 SPS instead.
+		 */
+		switch (i) {
+		case ADS1262_DR_2_5_SPS ... ADS1262_DR_10_SPS:
+			st->sampling_freq_fir[i][0] = st->sampling_freq_table[i][0];
+			st->sampling_freq_fir[i][1] = st->sampling_freq_table[i][1];
+			break;
+		case ADS1262_DR_16_6_SPS:
+			st->sampling_freq_fir[i][0] = st->sampling_freq_table[ADS1262_DR_20_SPS][0];
+			st->sampling_freq_fir[i][1] = st->sampling_freq_table[ADS1262_DR_20_SPS][1];
+			break;
+		}
+	}
+}
+
+static int ads1262_populate_tables(struct iio_dev *indio_dev)
+{
+	struct ads1262 *st = iio_priv(indio_dev);
+
+	ads1262_populate_samp_freqs(st);
+
+	return 0;
+}
+
 static int ads1262_parse_channel_node(struct ads1262 *st,
 				      struct iio_chan_spec *spec,
 				      struct fwnode_handle *node)

@@ -744,9 +951,18 @@ static int ads1262_parse_channels(struct iio_dev *indio_dev)
 	if (!chan_specs)
 		return -ENOMEM;
 
+	st->num_channels = num_fw_channels + ADS1262_MON_CHANNEL_COUNT;
+	st->channels = devm_kcalloc(dev, st->num_channels, sizeof(*st->channels),
+				    GFP_KERNEL);
+	if (!st->channels)
+		return -ENOMEM;
+
 	i = 0;
 	device_for_each_named_child_node_scoped(dev, node, "channel") {
 		struct iio_chan_spec *spec = &chan_specs[i];
+		struct ads1262_channel *chan = &st->channels[i];
+
+		*chan = ads1262_default_channel;
 
 		ret = ads1262_parse_channel_node(st, spec, node);
 		if (ret)

@@ -767,7 +983,9 @@ static int ads1262_parse_channels(struct iio_dev *indio_dev)
 			.storagebits = 32,
 			.endianness = IIO_BE,
 		};
-		spec->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
+		spec->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
+					   BIT(IIO_CHAN_INFO_SAMP_FREQ);
+		spec->info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ);
 
 		i++;
 	}

@@ -776,6 +994,7 @@ static int ads1262_parse_channels(struct iio_dev *indio_dev)
 	       sizeof(ads1262_monitor_chan_specs));
 
 	for (unsigned int mon = 0; mon < ADS1262_MON_CHANNEL_COUNT; mon++) {
+		st->channels[i] = ads1262_default_channel;
 		chan_specs[i].scan_index = i;
 		i++;
 	}

@@ -875,6 +1094,10 @@ static int ads1262_spi_probe(struct spi_device *spi)
 	if (ret)
 		return dev_err_probe(dev, ret, "failed to configure device\n");
 
+	ret = ads1262_populate_tables(indio_dev);
+	if (ret)
+		return ret;
+
 	/*
 	 * REVISIT: This chip has software polling capabilities, which could be
 	 * used to stop depending on the DRDY signal.

index 7a6fa009ddad..98d147f120c4 100644
@@ -8,6 +8,7 @@
 #include <linux/array_size.h>
 #include <linux/bitfield.h>
 #include <linux/bitops.h>
+#include <linux/bitmap.h>
 #include <linux/cleanup.h>
 #include <linux/clk.h>
 #include <linux/completion.h>

@@ -17,12 +18,14 @@
 #include <linux/interrupt.h>
 #include <linux/lockdep.h>
 #include <linux/math64.h>
+#include <linux/minmax.h>
 #include <linux/module.h>
 #include <linux/mutex.h>
 #include <linux/property.h>
 #include <linux/regmap.h>
 #include <linux/regulator/consumer.h>
 #include <linux/spi/spi.h>
+#include <linux/string.h>
 #include <linux/types.h>
 #include <linux/units.h>
 

@@ -82,6 +85,7 @@
 #define ADS1262_MODE2_REG			0x05
 #define   ADS1262_MODE2_BYPASS_MASK		BIT(7)
 #define   ADS1262_MODE2_GAIN_MASK		GENMASK(6, 4)
+#define     ADS1262_GAIN_COUNT			6
 #define   ADS1262_MODE2_DR_MASK			GENMASK(3, 0)
 #define     ADS1262_DR_2_5_SPS			  0
 #define     ADS1262_DR_5_SPS			  1

@@ -122,7 +126,7 @@
 #define ADS1262_IDACMUX_REG			0x0D
 #define   ADS1262_IDACMUX_MUX2_MASK		GENMASK(7, 4)
 #define   ADS1262_IDACMUX_MUX1_MASK		GENMASK(3, 0)
-#define     ADS1262_IDACMUX_NO_CONN		0b1011
+#define     ADS1262_IDACMUX_NO_CONN		  11
 
 #define ADS1262_IDACMAG_REG			0x0E
 #define   ADS1262_IDACMAG_MAG2_MASK		GENMASK(7, 4)

@@ -130,7 +134,17 @@
 
 #define ADS1262_REFMUX_REG			0x0F
 #define   ADS1262_REFMUX_RMUXP_MASK		GENMASK(5, 3)
+#define     ADS1262_RMUXP_INTERNAL		  0
+#define     ADS1262_RMUXP_REFP1			  1
+#define     ADS1262_RMUXP_REFP2			  2
+#define     ADS1262_RMUXP_REFP3			  3
+#define     ADS1262_RMUXP_AVDD			  4
 #define   ADS1262_REFMUX_RMUXN_MASK		GENMASK(2, 0)
+#define     ADS1262_RMUXN_INTERNAL		  0
+#define     ADS1262_RMUXN_REFN1			  1
+#define     ADS1262_RMUXN_REFN2			  2
+#define     ADS1262_RMUXN_REFN3			  3
+#define     ADS1262_RMUXN_AVSS			  4
 
 #define ADS1262_TDACP_REG			0x10
 #define   ADS1262_TDACP_OUTP_MASK		BIT(7)

@@ -168,9 +182,13 @@
 
 #define ADS1262_NOMINAL_CLK_RATE_HZ		7372800
 #define ADS1262_MODULATOR_DIV			8
+#define ADS1262_INTERNAL_REFERENCE_uV		2500000
+#define ADS1262_TEMP_SLOPE_uV_C			420ULL
+#define ADS1262_TEMP_ZERO_C			111900ULL
 
 #define ADS1262_FW_CHANNEL_COUNT		16
 #define ADS1262_MON_CHANNEL_COUNT		4
+#define ADS1262_EXT_REF_COUNT			3
 #define ADS1262_REGMAP_WRITE_SZ			8
 
 #define ADS1262_ADC1_RESOLUTION			32

@@ -182,6 +200,13 @@ struct ads1262_chip_info {
 struct ads1262_channel {
 	u8 data_rate;
 	u8 filter;
+	u8 gain;
+	u8 ref_p;
+	u8 ref_n;
+	bool ref_reversal;
+	bool is_resistance;
+	size_t num_scales;
+	int scales[ADS1262_GAIN_COUNT][2];
 };
 
 struct ads1262 {

@@ -196,8 +221,14 @@ struct ads1262 {
 	struct mutex chan_lock;
 	struct completion drdy;
 	unsigned long clk_rate_hz;
+	bool bipolar_supply;
+	int avdd_uV;
+	int avss_uV;
 	int sampling_freq_table[ADS1262_DR_COUNT][2];
 	int sampling_freq_fir[ADS1262_DR_16_6_SPS + 1][2];
+	u32 rref_ohms[ADS1262_EXT_REF_COUNT][ADS1262_EXT_REF_COUNT];
+	int refp_uV[ADS1262_EXT_REF_COUNT];
+	int refn_uV[ADS1262_EXT_REF_COUNT];
 };
 
 static const struct iio_chan_spec ads1262_monitor_chan_specs[] = {

@@ -212,8 +243,11 @@ static const struct iio_chan_spec ads1262_monitor_chan_specs[] = {
 			.endianness = IIO_BE,
 		},
 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
-				      BIT(IIO_CHAN_INFO_SAMP_FREQ),
-		.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
+				      BIT(IIO_CHAN_INFO_OFFSET) |
+				      BIT(IIO_CHAN_INFO_SAMP_FREQ) |
+				      BIT(IIO_CHAN_INFO_SCALE),
+		.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) |
+						BIT(IIO_CHAN_INFO_SCALE),
 	},
 	{
 		.type = IIO_VOLTAGE,

@@ -227,8 +261,10 @@ static const struct iio_chan_spec ads1262_monitor_chan_specs[] = {
 			.endianness = IIO_BE,
 		},
 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
-				      BIT(IIO_CHAN_INFO_SAMP_FREQ),
-		.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
+				      BIT(IIO_CHAN_INFO_SAMP_FREQ) |
+				      BIT(IIO_CHAN_INFO_SCALE),
+		.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) |
+						BIT(IIO_CHAN_INFO_SCALE),
 	},
 	{
 		.type = IIO_VOLTAGE,

@@ -242,8 +278,10 @@ static const struct iio_chan_spec ads1262_monitor_chan_specs[] = {
 			.endianness = IIO_BE,
 		},
 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
-				      BIT(IIO_CHAN_INFO_SAMP_FREQ),
-		.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
+				      BIT(IIO_CHAN_INFO_SAMP_FREQ) |
+				      BIT(IIO_CHAN_INFO_SCALE),
+		.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) |
+						BIT(IIO_CHAN_INFO_SCALE),
 	},
 	{
 		.type = IIO_VOLTAGE,

@@ -258,8 +296,10 @@ static const struct iio_chan_spec ads1262_monitor_chan_specs[] = {
 			.endianness = IIO_BE,
 		},
 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
-				      BIT(IIO_CHAN_INFO_SAMP_FREQ),
-		.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ),
+				      BIT(IIO_CHAN_INFO_SAMP_FREQ) |
+				      BIT(IIO_CHAN_INFO_SCALE),
+		.info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) |
+						BIT(IIO_CHAN_INFO_SCALE),
 	},
 };
 

@@ -306,6 +346,24 @@ static const u32 ads1262_mod_decimator_b[] = {
 	[ADS1262_DR_38400_SPS]	= 1,
 };
 
+static const char * const ads1262_ref_sources_pos[] = {
+	[ADS1262_RMUXP_INTERNAL] = "internal-p",
+	[ADS1262_RMUXP_REFP1] = "refp1",
+	[ADS1262_RMUXP_REFP2] = "refp2",
+	[ADS1262_RMUXP_REFP3] = "refp3",
+	[ADS1262_RMUXP_AVDD] = "avdd",
+	NULL
+};
+
+static const char * const ads1262_ref_sources_neg[] = {
+	[ADS1262_RMUXN_INTERNAL] = "internal-n",
+	[ADS1262_RMUXN_REFN1] = "refn1",
+	[ADS1262_RMUXN_REFN2] = "refn2",
+	[ADS1262_RMUXN_REFN3] = "refn3",
+	[ADS1262_RMUXN_AVSS] = "avss",
+	NULL
+};
+
 static int ads1262_find_two(const int (*array)[2], size_t num_elements, int val,
 			    int val2)
 {

@@ -317,6 +375,12 @@ static int ads1262_find_two(const int (*array)[2], size_t num_elements, int val,
 	return -EINVAL;
 }
 
+static bool ads1262_reference_is_external(int ref_p, int ref_n)
+{
+	return in_range(ref_p, ADS1262_RMUXP_REFP1, ADS1262_EXT_REF_COUNT) &&
+	       in_range(ref_n, ADS1262_RMUXN_REFN1, ADS1262_EXT_REF_COUNT);
+}
+
 static int ads1262_dev_send_cmd(struct ads1262 *st, u8 opcode)
 {
 	guard(mutex)(&st->xfer_lock);

@@ -447,17 +511,33 @@ static int ads1262_channel_enable(struct ads1262 *st,
 	guard(mutex)(&st->xfer_lock);
 	guard(mutex)(&st->chan_lock);
 
-	ret = regmap_update_bits(st->regmap, ADS1262_MODE2_REG,
-				 ADS1262_MODE2_DR_MASK,
-				 FIELD_PREP(ADS1262_MODE2_DR_MASK, chan->data_rate));
+	ret = regmap_update_bits(st->regmap, ADS1262_MODE0_REG,
+				 ADS1262_MODE0_REFREV_MASK,
+				 FIELD_PREP(ADS1262_MODE0_REFREV_MASK, chan->ref_reversal));
 	if (ret)
 		return ret;
 
-	return regmap_update_bits(st->regmap, ADS1262_INPMUX_REG,
-				  ADS1262_INPMUX_MUXN_MASK |
-				  ADS1262_INPMUX_MUXP_MASK,
-				  FIELD_PREP(ADS1262_INPMUX_MUXN_MASK, spec->channel2) |
-				  FIELD_PREP(ADS1262_INPMUX_MUXP_MASK, spec->channel));
+	ret = regmap_update_bits(st->regmap, ADS1262_MODE2_REG,
+				 ADS1262_MODE2_DR_MASK |
+				 ADS1262_MODE2_GAIN_MASK,
+				 FIELD_PREP(ADS1262_MODE2_DR_MASK, chan->data_rate) |
+				 FIELD_PREP(ADS1262_MODE2_GAIN_MASK, chan->gain));
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(st->regmap, ADS1262_INPMUX_REG,
+				 ADS1262_INPMUX_MUXN_MASK |
+				 ADS1262_INPMUX_MUXP_MASK,
+				 FIELD_PREP(ADS1262_INPMUX_MUXN_MASK, spec->channel2) |
+				 FIELD_PREP(ADS1262_INPMUX_MUXP_MASK, spec->channel));
+	if (ret)
+		return ret;
+
+	return regmap_update_bits(st->regmap, ADS1262_REFMUX_REG,
+				  ADS1262_REFMUX_RMUXN_MASK |
+				  ADS1262_REFMUX_RMUXP_MASK,
+				  FIELD_PREP(ADS1262_REFMUX_RMUXN_MASK, chan->ref_n) |
+				  FIELD_PREP(ADS1262_REFMUX_RMUXP_MASK, chan->ref_p));
 }
 
 static int ads1262_set_runmode(struct ads1262 *st, u8 runmode)

@@ -506,6 +586,7 @@ static int ads1262_read_raw(struct iio_dev *indio_dev,
 {
 	struct ads1262 *st = iio_priv(indio_dev);
 	struct ads1262_channel *chan_data = &st->channels[chan->scan_index];
+	u64 scale, offset;
 	__be32 raw;
 	int ret;
 

@@ -518,6 +599,34 @@ static int ads1262_read_raw(struct iio_dev *indio_dev,
 
 		return IIO_VAL_INT;
 
+	case IIO_CHAN_INFO_SCALE: {
+		guard(mutex)(&st->chan_lock);
+
+		*val = chan_data->scales[chan_data->gain][0];
+		*val2 = chan_data->scales[chan_data->gain][1];
+
+		return IIO_VAL_DECIMAL64_PICO;
+	}
+
+	case IIO_CHAN_INFO_OFFSET: {
+		guard(mutex)(&st->chan_lock);
+
+		scale = iio_val_s64_compose(chan_data->scales[chan_data->gain][0],
+					    chan_data->scales[chan_data->gain][1]);
+
+		switch (chan->type) {
+		case IIO_TEMP:
+			offset = -mul_u64_u64_div_u64(ADS1262_TEMP_ZERO_C,
+						      PICO * MILLIDEGREE_PER_DEGREE,
+						      scale * ADS1262_TEMP_SLOPE_uV_C);
+			iio_val_s64_decompose(offset, val, val2);
+
+			return IIO_VAL_INT_64;
+		default:
+			return -EOPNOTSUPP;
+		}
+	}
+
 	case IIO_CHAN_INFO_SAMP_FREQ: {
 		guard(mutex)(&st->chan_lock);
 

@@ -540,6 +649,12 @@ static int ads1262_read_avail(struct iio_dev *indio_dev,
 	struct ads1262_channel *chan_data = &st->channels[chan->scan_index];
 
 	switch (mask) {
+	case IIO_CHAN_INFO_SCALE:
+		*type = IIO_VAL_DECIMAL64_PICO;
+		*vals = (const int *)chan_data->scales;
+		*length = chan_data->num_scales * 2;
+		return IIO_AVAIL_LIST;
+
 	case IIO_CHAN_INFO_SAMP_FREQ:
 		*type = IIO_VAL_INT_PLUS_MICRO;
 

@@ -572,6 +687,16 @@ static int ads1262_write_raw(struct iio_dev *indio_dev,
 	guard(mutex)(&st->chan_lock);
 
 	switch (mask) {
+	case IIO_CHAN_INFO_SCALE:
+		ret = ads1262_find_two(chan_data->scales, chan_data->num_scales,
+				       val, val2);
+		if (ret < 0)
+			return ret;
+
+		chan_data->gain = ret;
+
+		return 0;
+
 	case IIO_CHAN_INFO_SAMP_FREQ:
 		switch (chan_data->filter) {
 		case ADS1262_FILTER_FIR:

@@ -613,6 +738,17 @@ static int ads1262_debugfs_reg_access(struct iio_dev *indio_dev, unsigned int re
 	return regmap_write(st->regmap, reg, writeval);
 }
 
+static int ads1262_write_raw_get_fmt(struct iio_dev *indio_dev,
+				     struct iio_chan_spec const *chan, long mask)
+{
+	switch (mask) {
+	case IIO_CHAN_INFO_SCALE:
+		return IIO_VAL_DECIMAL64_PICO;
+	default:
+		return IIO_VAL_INT_PLUS_MICRO;
+	}
+}
+
 static int ads1262_fwnode_xlate(struct iio_dev *indio_dev,
 				const struct fwnode_reference_args *iiospec)
 {

@@ -636,6 +772,7 @@ static const struct iio_info ads1262_iio_info = {
 	.read_raw = ads1262_read_raw,
 	.read_avail = ads1262_read_avail,
 	.write_raw = ads1262_write_raw,
+	.write_raw_get_fmt = ads1262_write_raw_get_fmt,
 	.debugfs_reg_access = ads1262_debugfs_reg_access,
 	.fwnode_xlate = ads1262_fwnode_xlate,
 };

@@ -876,20 +1013,241 @@ static void ads1262_populate_samp_freqs(struct ads1262 *st)
 	}
 }
 
+static void ads1262_calculate_scales(int (*scales)[2], size_t num_scales,
+				     u32 full_scale, u64 mult,
+				     u32 resolution)
+{
+	unsigned int i;
+	s64 val;
+
+	/*
+	 * Each scale in the table corresponds to a PGA gain configuration,
+	 * which are given in powers of 2.
+	 */
+	for (i = 0; i < num_scales; i++) {
+		val = mul_u64_u64_shr(full_scale, mult, resolution - 1 + i);
+		iio_val_s64_decompose(val, &scales[i][0], &scales[i][1]);
+	}
+}
+
+static int ads1262_populate_scales_resistance(struct ads1262 *st,
+					      const struct iio_chan_spec *spec)
+{
+	struct ads1262_channel *chan = &st->channels[spec->scan_index];
+	u32 full_scale;
+
+	if (!ads1262_reference_is_external(chan->ref_p, chan->ref_n))
+		return -EINVAL;
+
+	full_scale = st->rref_ohms[chan->ref_p - 1][chan->ref_n - 1];
+
+	chan->num_scales = ARRAY_SIZE(chan->scales);
+
+	ads1262_calculate_scales(chan->scales, chan->num_scales, full_scale,
+				 PICO, ADS1262_ADC1_RESOLUTION);
+
+	return 0;
+}
+
+static int ads1262_populate_scales_temp(struct ads1262 *st,
+					const struct iio_chan_spec *spec)
+{
+	struct ads1262_channel *chan = &st->channels[spec->scan_index];
+	u32 full_scale;
+	u64 mult;
+
+	full_scale = ADS1262_INTERNAL_REFERENCE_uV;
+	mult = PICO * MILLIDEGREE_PER_DEGREE / ADS1262_TEMP_SLOPE_uV_C;
+
+	chan->num_scales = 1;
+
+	ads1262_calculate_scales(chan->scales, chan->num_scales, full_scale,
+				 mult, ADS1262_ADC1_RESOLUTION);
+
+	return 0;
+}
+
+static int ads1262_populate_scales_voltage(struct ads1262 *st,
+					   const struct iio_chan_spec *spec)
+{
+	struct device *dev = &st->spi->dev;
+	struct ads1262_channel *chan = &st->channels[spec->scan_index];
+	int refp_uV, refn_uV;
+	u32 full_scale_uV;
+	u64 mult;
+
+	switch (chan->ref_p) {
+	case ADS1262_RMUXP_INTERNAL:
+		if (chan->ref_n == ADS1262_RMUXN_INTERNAL) {
+			refp_uV = ADS1262_INTERNAL_REFERENCE_uV;
+			break;
+		}
+
+		/* The negative internal reference is AVSS */
+		refp_uV = st->avss_uV + ADS1262_INTERNAL_REFERENCE_uV;
+		break;
+	case ADS1262_RMUXP_REFP1 ... ADS1262_RMUXP_REFP3:
+		refp_uV = st->refp_uV[chan->ref_p - 1];
+		break;
+	case ADS1262_RMUXP_AVDD:
+		if (!st->avdd_uV)
+			return dev_err_probe(dev, -EINVAL,
+					     "channel@%lu: avdd voltage unknown\n",
+					     spec->address);
+		refp_uV = st->avdd_uV;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	switch (chan->ref_n) {
+	case ADS1262_RMUXN_INTERNAL:
+		if (chan->ref_p == ADS1262_RMUXP_INTERNAL) {
+			refn_uV = 0;
+			break;
+		}
+		fallthrough;
+	case ADS1262_RMUXN_AVSS:
+		refn_uV = st->avss_uV;
+		break;
+	case ADS1262_RMUXN_REFN1 ... ADS1262_RMUXN_REFN3:
+		refn_uV = st->refn_uV[chan->ref_n - 1];
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	full_scale_uV = abs(refp_uV - refn_uV);
+	if (full_scale_uV < 900000)
+		return dev_err_probe(dev, -EINVAL, "channel@%lu: reference voltage below 0.9V\n",
+				     spec->address);
+
+	if (spec->channel >= ADS1262_INPMUX_AVDD &&
+	    spec->channel <= ADS1262_INPMUX_DVDD) {
+		/* The power supply monitors are scaled down by a factor of 4 */
+		mult = 4;
+		chan->num_scales = 1;
+	} else {
+		mult = 1;
+		chan->num_scales = ARRAY_SIZE(chan->scales);
+	}
+
+	ads1262_calculate_scales(chan->scales, chan->num_scales, full_scale_uV,
+				 NANO * mult, ADS1262_ADC1_RESOLUTION);
+
+	return 0;
+}
+
+static int ads1262_parse_references(struct ads1262 *st)
+{
+	struct device *dev = &st->spi->dev;
+	unsigned int i, j;
+	char name[sizeof("ti,refpN-refnM-resistor-ohms")];
+	u32 ohms;
+	int ret;
+
+	for (i = ADS1262_RMUXP_REFP1; i <= ADS1262_RMUXP_REFP3; i++) {
+		scnprintf(name, sizeof(name), "refp%u", i);
+		ret = devm_regulator_get_enable_read_voltage(dev, name);
+		if (ret < 0 && ret != -ENODEV)
+			return dev_err_probe(dev, ret, "failed to read reference voltage: %s\n",
+					     name);
+
+		st->refp_uV[i - 1] = ret == -ENODEV ? 0 : ret;
+	}
+
+	for (i = ADS1262_RMUXN_REFN1; i <= ADS1262_RMUXN_REFN3; i++) {
+		scnprintf(name, sizeof(name), "refn%u", i);
+		ret = devm_regulator_get_enable_read_voltage(dev, name);
+		if (ret < 0 && ret != -ENODEV)
+			return dev_err_probe(dev, ret, "failed to read reference voltage: %s\n",
+					     name);
+
+		/*
+		 * REVISIT: Currently the regulator subsystem doesn't support
+		 * reading negative voltages. If we have a bipolar supply
+		 * configuration (AVSS < 0), then we are forced to assume that
+		 * negative references are either 0V (no regulator) or below
+		 * ground magnitudes.
+		 */
+		if (st->bipolar_supply)
+			st->refn_uV[i - 1] = ret == -ENODEV ? 0 : -ret;
+		else
+			st->refn_uV[i - 1] = ret == -ENODEV ? 0 : ret;
+	}
+
+	for (i = ADS1262_RMUXP_REFP1; i <= ADS1262_RMUXP_REFP3; i++) {
+		for (j = ADS1262_RMUXN_REFN1; j <= ADS1262_RMUXN_REFN3; j++) {
+			scnprintf(name, sizeof(name),
+				  "ti,refp%u-refn%u-resistor-ohms", i, j);
+
+			if (!device_property_present(dev, name))
+				continue;
+
+			ret = device_property_read_u32(dev, name, &ohms);
+			if (ret)
+				return dev_err_probe(dev, ret,
+						     "failed to read reference resistor: %s\n",
+						     name);
+			if (!ohms)
+				return dev_err_probe(dev, -EINVAL,
+						     "reference resistor can't be 0 ohms: %s\n",
+						     name);
+
+			st->rref_ohms[i - 1][j - 1] = ohms;
+		}
+	}
+
+	return 0;
+}
+
 static int ads1262_populate_tables(struct iio_dev *indio_dev)
 {
 	struct ads1262 *st = iio_priv(indio_dev);
+	const struct iio_chan_spec *spec;
+	int ret;
 
 	ads1262_populate_samp_freqs(st);
 
+	ret = ads1262_parse_references(st);
+	if (ret)
+		return ret;
+
+	for (unsigned int i = 0; i < st->num_channels; i++) {
+		spec = &indio_dev->channels[i];
+
+		switch (spec->type) {
+		case IIO_VOLTAGE:
+			ret = ads1262_populate_scales_voltage(st, spec);
+			if (ret)
+				return ret;
+			break;
+		case IIO_TEMP:
+			ret = ads1262_populate_scales_temp(st, spec);
+			if (ret)
+				return ret;
+			break;
+		case IIO_RESISTANCE:
+			ret = ads1262_populate_scales_resistance(st, spec);
+			if (ret)
+				return ret;
+			break;
+		default:
+			return -EOPNOTSUPP;
+		}
+	}
+
 	return 0;
 }
 
 static int ads1262_parse_channel_node(struct ads1262 *st,
 				      struct iio_chan_spec *spec,
+				      struct ads1262_channel *chan,
 				      struct fwnode_handle *node)
 {
 	struct device *dev = &st->spi->dev;
+	const char *sources[2];
+	char name[sizeof("ti,refpN-refnM-resistor-ohms")];
 	u32 pins[2];
 	int ret;
 

@@ -928,6 +1286,38 @@ static int ads1262_parse_channel_node(struct ads1262 *st,
 	spec->channel = pins[0];
 	spec->channel2 = pins[1];
 
+	if (fwnode_property_present(node, "reference-sources")) {
+		ret = fwnode_property_read_string_array(node, "reference-sources",
+							sources, ARRAY_SIZE(sources));
+		if (ret < 0)
+			return dev_err_probe(dev, ret, "%pfwP: failed to read reference-sources\n",
+					     node);
+		if (ret < 2)
+			return dev_err_probe(dev, -EINVAL, "%pfwP: missing reference-sources\n",
+					     node);
+
+		ret = match_string(ads1262_ref_sources_pos, -1, sources[0]);
+		if (ret < 0)
+			return dev_err_probe(dev, ret, "%pfwP: invalid positive reference source\n",
+					     node);
+		chan->ref_p = ret;
+
+		ret = match_string(ads1262_ref_sources_neg, -1, sources[1]);
+		if (ret < 0)
+			return dev_err_probe(dev, ret, "%pfwP: invalid negative reference source\n",
+					     node);
+		chan->ref_n = ret;
+
+		if (ads1262_reference_is_external(chan->ref_p, chan->ref_n)) {
+			scnprintf(name, sizeof(name), "ti,refp%u-refn%u-resistor-ohms",
+				  chan->ref_p, chan->ref_n);
+			if (device_property_present(dev, name))
+				chan->is_resistance = true;
+		}
+	}
+
+	chan->ref_reversal = fwnode_property_read_bool(node, "ti,reference-reversal");
+
 	return 0;
 }
 

@@ -964,7 +1354,7 @@ static int ads1262_parse_channels(struct iio_dev *indio_dev)
 
 		*chan = ads1262_default_channel;
 
-		ret = ads1262_parse_channel_node(st, spec, node);
+		ret = ads1262_parse_channel_node(st, spec, chan, node);
 		if (ret)
 			return ret;
 

@@ -973,7 +1363,7 @@ static int ads1262_parse_channels(struct iio_dev *indio_dev)
 			return dev_err_probe(dev, ret, "%pfwP: failed to read reg\n",
 					     node);
 
-		spec->type = IIO_VOLTAGE;
+		spec->type = chan->is_resistance ? IIO_RESISTANCE : IIO_VOLTAGE;
 		spec->indexed = true;
 		spec->scan_index = i;
 		spec->address = reg;

@@ -984,8 +1374,10 @@ static int ads1262_parse_channels(struct iio_dev *indio_dev)
 			.endianness = IIO_BE,
 		};
 		spec->info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
-					   BIT(IIO_CHAN_INFO_SAMP_FREQ);
-		spec->info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ);
+					   BIT(IIO_CHAN_INFO_SAMP_FREQ) |
+					   BIT(IIO_CHAN_INFO_SCALE);
+		spec->info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) |
+						     BIT(IIO_CHAN_INFO_SCALE);
 
 		i++;
 	}

@@ -1008,22 +1400,59 @@ static int ads1262_parse_channels(struct iio_dev *indio_dev)
 	return 0;
 }
 
+static void ads1262_regulator_disable(void *data)
+{
+	struct regulator *supply = data;
+
+	regulator_disable(supply);
+}
+
 static int ads1262_supplies_setup(struct ads1262 *st)
 {
 	struct device *dev = &st->spi->dev;
+	struct regulator *avdd;
 	int ret;
 
 	ret = devm_regulator_get_enable(dev, "dvdd");
 	if (ret)
 		return dev_err_probe(dev, ret, "failed to get dvdd regulator\n");
 
-	ret = devm_regulator_get_enable(dev, "avdd");
-	if (ret < 0)
+	avdd = devm_regulator_get(dev, "avdd");
+	ret = PTR_ERR_OR_ZERO(avdd);
+	if (ret)
 		return dev_err_probe(dev, ret, "failed to get avdd regulator\n");
 
-	ret = devm_regulator_get_enable_optional(dev, "avss");
+	ret = regulator_enable(avdd);
+	if (ret)
+		return ret;
+
+	ret = devm_add_action_or_reset(dev, ads1262_regulator_disable, avdd);
+	if (ret)
+		return ret;
+
+	ret = regulator_get_voltage(avdd);
+	if (ret > 0)
+		st->avdd_uV = ret;
+
+	/*
+	 * REVISIT: The AVSS supply has a minimum of -2.5V and maximum of 0V.
+	 * Currently the regulator subsystem doesn't support negative voltages,
+	 * so we assume the value returned here is actually the magnitude
+	 * (absolute value).
+	 *
+	 * This limitation forces us to assume that, if we have a bipolar supply
+	 * (AVSS < 0V), all negative references are below ground (REFN <= 0V)
+	 * and positive references are above ground (REFP >= 0V), as this is the
+	 * most common configuration.
+	 */
+	ret = devm_regulator_get_enable_read_voltage(dev, "avss");
 	if (ret < 0 && ret != -ENODEV)
-		return dev_err_probe(dev, ret, "failed to get avss regulator\n");
+		return dev_err_probe(dev, ret, "failed to read AVSS voltage\n");
+
+	if (ret > 0) {
+		st->avss_uV = -ret;
+		st->bipolar_supply = true;
+	}
 
 	fsleep(ADS1262_POWER_TRANS_US);
 

index 98d147f120c4..938e26075302 100644
@@ -205,6 +205,7 @@ struct ads1262_channel {
 	u8 ref_n;
 	bool ref_reversal;
 	bool is_resistance;
+	bool input_chop;
 	size_t num_scales;
 	int scales[ADS1262_GAIN_COUNT][2];
 };

@@ -456,7 +457,7 @@ static int ads1262_dev_stop(struct ads1262 *st)
 	return ret;
 }
 
-static int ads1262_dev_start_one(struct ads1262 *st)
+static int ads1262_dev_start_one(struct ads1262 *st, u8 runmode)
 {
 	int ret;
 

@@ -464,7 +465,7 @@ static int ads1262_dev_start_one(struct ads1262 *st)
 	if (ret)
 		return ret;
 
-	if (st->start_gpiod) {
+	if (runmode == ADS1262_RUNMODE_CONTINUOUS || st->start_gpiod) {
 		/*
 		 * The START pulse timing requirement is 4 clock cycles, at the
 		 * minimum clock rate this is 4 microseconds.

@@ -512,7 +513,9 @@ static int ads1262_channel_enable(struct ads1262 *st,
 	guard(mutex)(&st->chan_lock);
 
 	ret = regmap_update_bits(st->regmap, ADS1262_MODE0_REG,
+				 ADS1262_MODE0_INPUT_CHOP_MASK |
 				 ADS1262_MODE0_REFREV_MASK,
+				 FIELD_PREP(ADS1262_MODE0_INPUT_CHOP_MASK, chan->input_chop) |
 				 FIELD_PREP(ADS1262_MODE0_REFREV_MASK, chan->ref_reversal));
 	if (ret)
 		return ret;

@@ -553,13 +556,26 @@ static int ads1262_channel_read(struct iio_dev *indio_dev,
 				const struct iio_chan_spec *spec, __be32 *val)
 {
 	struct ads1262 *st = iio_priv(indio_dev);
+	struct ads1262_channel *chan = &st->channels[spec->scan_index];
+	u8 runmode;
 	int ret;
 
 	IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
 	if (IIO_DEV_ACQUIRE_FAILED(claim))
 		return -EBUSY;
 
-	ret = ads1262_set_runmode(st, ADS1262_RUNMODE_PULSE);
+	/*
+	 * When a channel has chop mode or IDAC rotation mode, the first
+	 * conversion is always withheld so the datasheet suggests using the
+	 * CONTINUOUS mode and briefly starting and stopping conversions to
+	 * achieve the same effect (Section 9.4.1.2).
+	 */
+	if (chan->input_chop)
+		runmode = ADS1262_RUNMODE_CONTINUOUS;
+	else
+		runmode = ADS1262_RUNMODE_PULSE;
+
+	ret = ads1262_set_runmode(st, runmode);
 	if (ret)
 		return ret;
 

@@ -569,7 +585,7 @@ static int ads1262_channel_read(struct iio_dev *indio_dev,
 
 	reinit_completion(&st->drdy);
 
-	ret = ads1262_dev_start_one(st);
+	ret = ads1262_dev_start_one(st, runmode);
 	if (ret)
 		return ret;
 

@@ -1316,6 +1332,7 @@ static int ads1262_parse_channel_node(struct ads1262 *st,
 		}
 	}
 
+	chan->input_chop = fwnode_property_read_bool(node, "input-chopping");
 	chan->ref_reversal = fwnode_property_read_bool(node, "ti,reference-reversal");
 
 	return 0;

index 938e26075302..49d4bf206be0 100644
@@ -200,12 +200,15 @@ struct ads1262_chip_info {
 struct ads1262_channel {
 	u8 data_rate;
 	u8 filter;
+	u8 idac_mux[2];
+	u8 idac_mag[2];
 	u8 gain;
 	u8 ref_p;
 	u8 ref_n;
 	bool ref_reversal;
 	bool is_resistance;
 	bool input_chop;
+	bool idac_chop;
 	size_t num_scales;
 	int scales[ADS1262_GAIN_COUNT][2];
 };

@@ -307,6 +310,10 @@ static const struct iio_chan_spec ads1262_monitor_chan_specs[] = {
 #define ads1262_default_channel ((struct ads1262_channel) {	\
 	.data_rate = ADS1262_DR_20_SPS,				\
 	.filter = ADS1262_FILTER_FIR,				\
+	.idac_mux = {						\
+		ADS1262_IDACMUX_NO_CONN,			\
+		ADS1262_IDACMUX_NO_CONN				\
+	},							\
 })
 
 static const u32 ads1262_mod_decimator_a[] = {

@@ -365,6 +372,21 @@ static const char * const ads1262_ref_sources_neg[] = {
 	NULL
 };
 
+static const u32 ads1262_idac_mags_nA[] = {
+	0, 50000, 100000, 250000, 500000, 750000, 1000000, 1500000,	/* 0..7 */
+	2000000, 2500000, 3000000					/* 8..10 */
+};
+
+static int ads1262_find_one(const u32 *array, size_t num_elements, u32 val)
+{
+	for (unsigned int i = 0; i < num_elements; i++) {
+		if (val == array[i])
+			return i;
+	}
+
+	return -EINVAL;
+}
+
 static int ads1262_find_two(const int (*array)[2], size_t num_elements, int val,
 			    int val2)
 {

@@ -514,8 +536,10 @@ static int ads1262_channel_enable(struct ads1262 *st,
 
 	ret = regmap_update_bits(st->regmap, ADS1262_MODE0_REG,
 				 ADS1262_MODE0_INPUT_CHOP_MASK |
+				 ADS1262_MODE0_IDAC_CHOP_MASK |
 				 ADS1262_MODE0_REFREV_MASK,
 				 FIELD_PREP(ADS1262_MODE0_INPUT_CHOP_MASK, chan->input_chop) |
+				 FIELD_PREP(ADS1262_MODE0_IDAC_CHOP_MASK, chan->idac_chop) |
 				 FIELD_PREP(ADS1262_MODE0_REFREV_MASK, chan->ref_reversal));
 	if (ret)
 		return ret;

@@ -536,6 +560,22 @@ static int ads1262_channel_enable(struct ads1262 *st,
 	if (ret)
 		return ret;
 
+	ret = regmap_update_bits(st->regmap, ADS1262_IDACMUX_REG,
+				 ADS1262_IDACMUX_MUX1_MASK |
+				 ADS1262_IDACMUX_MUX2_MASK,
+				 FIELD_PREP(ADS1262_IDACMUX_MUX1_MASK, chan->idac_mux[0]) |
+				 FIELD_PREP(ADS1262_IDACMUX_MUX2_MASK, chan->idac_mux[1]));
+	if (ret)
+		return ret;
+
+	ret = regmap_update_bits(st->regmap, ADS1262_IDACMAG_REG,
+				 ADS1262_IDACMAG_MAG1_MASK |
+				 ADS1262_IDACMAG_MAG2_MASK,
+				 FIELD_PREP(ADS1262_IDACMAG_MAG1_MASK, chan->idac_mag[0]) |
+				 FIELD_PREP(ADS1262_IDACMAG_MAG2_MASK, chan->idac_mag[1]));
+	if (ret)
+		return ret;
+
 	return regmap_update_bits(st->regmap, ADS1262_REFMUX_REG,
 				  ADS1262_REFMUX_RMUXN_MASK |
 				  ADS1262_REFMUX_RMUXP_MASK,

@@ -570,7 +610,7 @@ static int ads1262_channel_read(struct iio_dev *indio_dev,
 	 * CONTINUOUS mode and briefly starting and stopping conversions to
 	 * achieve the same effect (Section 9.4.1.2).
 	 */
-	if (chan->input_chop)
+	if (chan->input_chop || chan->idac_chop)
 		runmode = ADS1262_RUNMODE_CONTINUOUS;
 	else
 		runmode = ADS1262_RUNMODE_PULSE;

@@ -1264,8 +1304,8 @@ static int ads1262_parse_channel_node(struct ads1262 *st,
 	struct device *dev = &st->spi->dev;
 	const char *sources[2];
 	char name[sizeof("ti,refpN-refnM-resistor-ohms")];
-	u32 pins[2];
-	int ret;
+	u32 pins[2], mags[2];
+	int count, ret;
 
 	if (fwnode_property_present(node, "single-channel")) {
 		ret = fwnode_property_read_u32(node, "single-channel", &pins[0]);

@@ -1332,7 +1372,51 @@ static int ads1262_parse_channel_node(struct ads1262 *st,
 		}
 	}
 
+	if (fwnode_property_present(node, "excitation-channels")) {
+		count = fwnode_property_count_u32(node, "excitation-channels");
+		if (count < 0)
+			return dev_err_probe(dev, count,
+					     "%pfwP: failed to count excitation-channels\n", node);
+
+		pins[0] = ADS1262_IDACMUX_NO_CONN;
+		pins[1] = ADS1262_IDACMUX_NO_CONN;
+		ret = fwnode_property_read_u32_array(node, "excitation-channels",
+						     pins, min(count, ARRAY_SIZE(pins)));
+		if (ret)
+			return dev_err_probe(dev, ret,
+					     "%pfwP: failed to read excitation-channels\n", node);
+		if (pins[0] > ADS1262_IDACMUX_NO_CONN || pins[1] > ADS1262_IDACMUX_NO_CONN)
+			return dev_err_probe(dev, -EINVAL,
+					     "%pfwP: excitation-channels not in range\n", node);
+		chan->idac_mux[0] = pins[0];
+		chan->idac_mux[1] = pins[1];
+
+		mags[0] = 0;
+		mags[1] = 0;
+		ret = fwnode_property_read_u32_array(node, "excitation-current-nanoamp",
+						     mags, min(count, ARRAY_SIZE(mags)));
+		if (ret)
+			return dev_err_probe(dev, ret,
+					     "%pfwP: failed to read excitation-current-nanoamp\n",
+					     node);
+
+		ret = ads1262_find_one(ads1262_idac_mags_nA,
+				       ARRAY_SIZE(ads1262_idac_mags_nA), mags[0]);
+		if (ret < 0)
+			return dev_err_probe(dev, ret,
+					     "%pfwP: invalid excitation-current-nanoamp\n", node);
+		chan->idac_mag[0] = ret;
+
+		ret = ads1262_find_one(ads1262_idac_mags_nA,
+				       ARRAY_SIZE(ads1262_idac_mags_nA), mags[1]);
+		if (ret < 0)
+			return dev_err_probe(dev, ret,
+					     "%pfwP: invalid excitation-current-nanoamp\n", node);
+		chan->idac_mag[1] = ret;
+	}
+
 	chan->input_chop = fwnode_property_read_bool(node, "input-chopping");
+	chan->idac_chop = fwnode_property_read_bool(node, "excitation-current-chopping");
 	chan->ref_reversal = fwnode_property_read_bool(node, "ti,reference-reversal");
 
 	return 0;

351 lines not on this page · raw message

138 lines not on this page · raw message

index 5bb41b70353f..66a7fedfefde 100644
@@ -241,6 +241,7 @@ struct ads1262 {
 	u32 rref_ohms[ADS1262_EXT_REF_COUNT][ADS1262_EXT_REF_COUNT];
 	int refp_uV[ADS1262_EXT_REF_COUNT];
 	int refn_uV[ADS1262_EXT_REF_COUNT];
+	int common_mode_uV[ADS1262_INPMUX_AINCOM + 1];
 	IIO_DECLARE_BUFFER_WITH_TS(__be32, scan_buffer,
 				   ADS1262_FW_CHANNEL_COUNT +
 				   ADS1262_MON_CHANNEL_COUNT);

@@ -690,6 +691,13 @@ static int ads1262_read_raw(struct iio_dev *indio_dev,
 						      scale * ADS1262_TEMP_SLOPE_uV_C);
 			iio_val_s64_decompose(offset, val, val2);
 
+			return IIO_VAL_INT_64;
+
+		case IIO_VOLTAGE:
+			offset = mul_u64_u64_div_u64(st->common_mode_uV[chan->channel2],
+						     NANO, scale);
+			iio_val_s64_decompose(offset, val, val2);
+
 			return IIO_VAL_INT_64;
 		default:
 			return -EOPNOTSUPP;

@@ -1123,6 +1131,28 @@ static irqreturn_t ads1262_irq_handler(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
+static int ads1262_parse_common_mode_supplies(struct ads1262 *st)
+{
+	struct device *dev = &st->spi->dev;
+	char name[sizeof("aincom")];
+	int ret;
+
+	for (unsigned int i = 0; i <= ADS1262_INPMUX_AINCOM; i++) {
+		if (i < ADS1262_INPMUX_AINCOM)
+			scnprintf(name, sizeof(name), "ain%u", i);
+		else
+			scnprintf(name, sizeof(name), "aincom");
+
+		ret = devm_regulator_get_enable_read_voltage(dev, name);
+		if (ret < 0 && ret != -ENODEV)
+			return dev_err_probe(dev, ret,
+					     "failed to get common mode supply: %s\n", name);
+		st->common_mode_uV[i] = ret != -ENODEV ? ret : 0;
+	}
+
+	return 0;
+}
+
 static int ads1262_vbias_enable(struct regulator_dev *rdev)
 {
 	struct ads1262 *st = rdev_get_drvdata(rdev);

@@ -1876,6 +1906,9 @@ static int ads1262_parse_channels(struct iio_dev *indio_dev)
 		spec->info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) |
 						     BIT(IIO_CHAN_INFO_SCALE);
 
+		if (!chan->is_resistance && !spec->differential)
+			spec->info_mask_separate |= BIT(IIO_CHAN_INFO_OFFSET);
+
 		i++;
 	}
 

@@ -2027,6 +2060,10 @@ static int ads1262_spi_probe(struct spi_device *spi)
 	if (ret)
 		return ret;
 
+	ret = ads1262_parse_common_mode_supplies(st);
+	if (ret)
+		return ret;
+
 	ret = ads1262_populate_tables(indio_dev);
 	if (ret)
 		return ret;