FAILED: patch "[PATCH] drm/i915/dmc: Add sanity check for DMC load address" failed to apply to 5.15-stable tree
[email protected]
maintainerThe patch below does not apply to the 5.15-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.
To reproduce the conflict and resubmit, you may use the following commands:
git fetch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/ linux-5.15.y
git checkout FETCH_HEAD
git cherry-pick -x 7dedc5bb11f95e96fe80757c924d8d9aa7327759
# <resolve conflicts, build, test, etc.>
git commit -s
git send-email --to '<[email protected]>' --in-reply-to '2026102102-cosponsor-entrench-2d30@gregkh' --subject-prefix 'PATCH 5.15.y' 'HEAD^..'
Possible dependencies:
thanks,
greg k-h
------------------ original commit in Linus's tree ------------------
From 7dedc5bb11f95e96fe80757c924d8d9aa7327759 Mon Sep 17 00:00:00 2001
From: Dibin Moolakadan Subrahmanian <[email protected]>
Date: Tue, 22 Sep 2026 19:05:38 +0530
Subject: [PATCH] drm/i915/dmc: Add sanity check for DMC load address
For DMC firmware header version 3, the firmware load address is stored in dmc_info->start_mmioaddr and later used by dmc_load_program().
Unlike the MMIO address table, the firmware load address is not validated. Add a sanity check to ensure it is within the valid range.
BSpec: 69671, 68378
drivers/gpu/drm/i915/display/intel_dmc.c +55 -0
@@ -1023,6 +1023,55 @@ static void dmc_set_fw_offset(struct intel_dmc *dmc, } } +/* +* Check if the load address is within the valid range for the given DMC ID. +*/ +static bool dmc_load_addr_sanity_check (struct intel_dmc *dmc, +u32 start_addr,u32 payload_size, +int header_ver,enum intel_dmc_id dmc_id) +{ +u32 start_range, end_range, end_addr; + +if (header_ver !=3 ) +return true; + +switch (dmc_id) { +case DMC_FW_MAIN : + start_range =DMC_MAIN_PROGRAM_BASE_START ; + end_range =DMC_MAIN_PROGRAM_BASE_END ; +break ; +case DMC_FW_PIPEA : + start_range =DMC_PIPEA_PROGRAM_BASE_START ; + end_range =DMC_PIPEA_PROGRAM_BASE_END ; +break ; +case DMC_FW_PIPEB : + start_range =DMC_PIPEB_PROGRAM_BASE_START ; + end_range =DMC_PIPEB_PROGRAM_BASE_END ; +break ; +case DMC_FW_PIPEC : + start_range =DMC_PIPEC_PROGRAM_BASE_START ; + end_range =DMC_PIPEC_PROGRAM_BASE_END ; +break ; +case DMC_FW_PIPED : + start_range =DMC_PIPED_PROGRAM_BASE_START ; + end_range =DMC_PIPED_PROGRAM_BASE_END ; +break ; +default : +MISSING_CASE (dmc_id); +return false; + } + +if (payload_size ==0 ) + end_addr = start_addr; +else if (check_add_overflow (start_addr, payload_size -1 , &end_addr)) +return false; + +if (start_addr < start_range || end_addr > end_range) +return false; + +return true; +} +static bool dmc_mmio_addr_sanity_check (struct intel_dmc *dmc,const u32 *mmioaddr,u32 mmio_count,int header_ver,enum intel_dmc_id dmc_id)
@@ -1189,6 +1238,12 @@ static u32 parse_dmc_fw_header(struct intel_dmc *dmc,return 0 ; } +if (!dmc_load_addr_sanity_check (dmc, start_mmioaddr, payload_size, + dmc_header->header_ver, dmc_id)) { +drm_err (display->drm,"DMC %d: firmware has wrong load address\n" , dmc_id); +return 0 ; + } + dmc_info->payload =kmalloc (payload_size,GFP_KERNEL );if (!dmc_info->payload)return 0 ;
drivers/gpu/drm/i915/display/intel_dmc_regs.h +12 -0
@@ -521,6 +521,18 @@ enum pipedmc_event_id {#define TGL_PIPE_MMIO_END (dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_END,\ _TGL_PIPEB_MMIO_END) +/* For DMC header version v3*/ +#define DMC_MAIN_PROGRAM_BASE_START 0x80000 +#define DMC_MAIN_PROGRAM_BASE_END 0x86fff +#define DMC_PIPEA_PROGRAM_BASE_START 0x90000 +#define DMC_PIPEA_PROGRAM_BASE_END 0x96fff +#define DMC_PIPEB_PROGRAM_BASE_START 0x98000 +#define DMC_PIPEB_PROGRAM_BASE_END 0x9efff +#define DMC_PIPEC_PROGRAM_BASE_START 0x52000 +#define DMC_PIPEC_PROGRAM_BASE_END 0x53fff +#define DMC_PIPED_PROGRAM_BASE_START 0x59000 +#define DMC_PIPED_PROGRAM_BASE_END 0x5afff +#define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030)#define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C)#define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038)