common/mlx5: fix mkey ordering enum
PATCH 1/1 common/mlx5: fix mkey ordering enum
The updated device specification defines relaxed ordering as 0x1 and reserves 0x2. Update the mkey read-after-write ordering values accordingly.
--- drivers/common/mlx5/mlx5_prm.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
drivers/common/mlx5/mlx5_prm.h +1 -2
@@ -1483,8 +1483,7 @@ enum {/* MKC read_after_write_ordering field (2-bit, dword 0x38 bits 9:8). */ enum mlx5_mkc_raw_ordering {MLX5_MKC_RAW_ORDERING_SO =0x0 , -MLX5_MKC_RAW_ORDERING_SAO =0x1 , -MLX5_MKC_RAW_ORDERING_RO =0x2 , +MLX5_MKC_RAW_ORDERING_RO =0x1 , };struct mlx5_ifc_create_mkey_out_bits {
Signature · 1 line
2.21.0
PATCH v2 1/1 common/mlx5: fix mkey ordering enum
The updated device specification defines relaxed ordering as 0x1 and reserves 0x2. Update the mkey read-after-write ordering values accordingly.
--- drivers/common/mlx5/mlx5_prm.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
drivers/common/mlx5/mlx5_prm.h +1 -2
@@ -1483,8 +1483,7 @@ enum {/* MKC read_after_write_ordering field (2-bit, dword 0x38 bits 9:8). */ enum mlx5_mkc_raw_ordering {MLX5_MKC_RAW_ORDERING_SO =0x0 , -MLX5_MKC_RAW_ORDERING_SAO =0x1 , -MLX5_MKC_RAW_ORDERING_RO =0x2 , +MLX5_MKC_RAW_ORDERING_RO =0x1 , };struct mlx5_ifc_create_mkey_out_bits {
Signature · 1 line
2.21.0
PATCH v3 1/1 common/mlx5: fix mkey ordering enum
In reply to Maayan KashaniThe updated device specification defines relaxed ordering as 0x1 and reserves 0x2. Update the mkey read-after-write ordering values accordingly.
Windows MR registration applies full MKC ordering, including read-after-write, on every non-Haswell CPU. Other mlx5 drivers apply that ordering only when firmware reports relaxed-order-only mode. Keep relaxed-ordering read and write enabled from HCA capabilities, and apply read-after-write ordering only when mkc_order_write_after_write_ro_only is set.
---
v3:
- On Windows, set relaxed-ordering read and write from HCA capabilities and apply read-after-write ordering only when firmware requires relaxed-order-only mode.
drivers/common/mlx5/mlx5_prm.h | 3 +-- drivers/common/mlx5/windows/mlx5_common_os.c | 9 +++++++-- 2 files changed, 8 insertions(+), 4 deletions(-)
drivers/common/mlx5/mlx5_prm.h +1 -2
@@ -1483,8 +1483,7 @@ enum {/* MKC read_after_write_ordering field (2-bit, dword 0x38 bits 9:8). */ enum mlx5_mkc_raw_ordering {MLX5_MKC_RAW_ORDERING_SO =0x0 , -MLX5_MKC_RAW_ORDERING_SAO =0x1 , -MLX5_MKC_RAW_ORDERING_RO =0x2 , +MLX5_MKC_RAW_ORDERING_RO =0x1 , };struct mlx5_ifc_create_mkey_out_bits {
drivers/common/mlx5/windows/mlx5_common_os.c +7 -2
@@ -403,8 +403,13 @@ mlx5_os_reg_mr(void *pd, mkey_attr.size = length; mkey_attr.umem_id = ((struct mlx5_devx_umem *)(obj))->umem_id; mkey_attr.pd = mlx5_pd->pdn; -if (!mlx5_haswell_broadwell_cpu) -mlx5_devx_mkey_attr_set_ordering (&mkey_attr, &attr); +if (!mlx5_haswell_broadwell_cpu) { + mkey_attr.relaxed_ordering_write = attr.relaxed_ordering_write; + mkey_attr.relaxed_ordering_read = + attr.relaxed_ordering_read || attr.pci_relaxed_ordered_read; +if (attr.mkc_order_write_after_write_ro_only) +mlx5_devx_mkey_attr_set_ordering (&mkey_attr, &attr); + } mkey =mlx5_devx_cmd_mkey_create (mlx5_pd->devx_ctx, &mkey_attr);if (!mkey) {claim_zero (mlx5_os_umem_dereg (obj));
Signature · 1 line
2.25.1
Patch applied to next-net-mlx.
Thanks,
Raslan Darawsheh