MIPS: mm: Add an R10000 family cache error handler
PATCH 1/1 MIPS: mm: Add an R10000 family cache error handler
cache_parity_error() does not decode the R10000 family's CacheErr layout, and panics with ERL set on every error.
Recover I-cache errors by rewriting both ways of the set, as invalidating leaves the bad word in the data array, and panic on others with ERL clear. The handler is built with CONFIG_CPU_R10000.
Signed-off-by Imre Kaloz <[email protected]>
--- arch/mips/include/asm/traps.h | 2 + arch/mips/mm/Makefile | 1 + arch/mips/mm/c-r4k.c | 9 +++ arch/mips/mm/cerr-r10k.c | 141 ++++++++++++++++++++++++++++++++++ arch/mips/mm/cex-r10k.S | 125 ++++++++++++++++++++++++++++++ 5 files changed, 278 insertions(+) create mode 100644 arch/mips/mm/cerr-r10k.c create mode 100644 arch/mips/mm/cex-r10k.S
arch/mips/include/asm/traps.h +2 -0
@@ -62,6 +62,8 @@ asmlinkage void do_page_fault(struct pt_regs *regs, unsigned long write, unsigned long address); asmlinkage void cache_parity_error(void); +asmlinkage void do_cache_error_r10k(struct pt_regs *regs, int resumable); +extern char except_vec2_r10k[]; asmlinkage void ejtag_exception_handler(struct pt_regs *regs); asmlinkage void __noreturn nmi_exception_handler(struct pt_regs *regs);
arch/mips/mm/Makefile +1 -0
@@ -36,6 +36,7 @@ obj-$(CONFIG_CPU_R3K_TLB) += tlb-r3k.o obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o obj-$(CONFIG_CPU_R3000) += c-r3k.o obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o +obj-$(CONFIG_CPU_R10000) += cerr-r10k.o cex-r10k.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
arch/mips/mm/c-r4k.c +9 -0
@@ -1690,6 +1690,15 @@ static void r4k_cache_error_setup(void)set_uncached_handler (0x100 , &except_vec2_sb1,0x80 );break ; +#ifdef CONFIG_CPU_R10000 +case CPU_R10000 : +case CPU_R12000 : +case CPU_R14000 : +case CPU_R16000 : +set_uncached_handler (0x100 , except_vec2_r10k,0x80 ); +break ; +#endif +default :set_uncached_handler (0x100 , &except_vec2_generic,0x80 );break ;
arch/mips/mm/cerr-r10k.c new file +141 -0
141 lines not on this page · raw message
arch/mips/mm/cex-r10k.S new file +125 -0
125 lines not on this page · raw message
base-commit: b2f6eb84b8bfd213c3df69f9ced41a501ac4de9b
Signature · 1 line
2.47.3