Skip to contentSkip to conversation

pinctrl: sunxi: use automatic voltage detection on A733

PATCH In review Enzo Adriano 2 participants 2 messages Nov 10 – Nov 11

Subsystems (3)
GPIO Arm/Allwinner sunXi SoC support Pin control
lore
Share & tools
lore

Enzo Adriano

author
#0 lore raw

PATCH v3 1/1 pinctrl: sunxi: use automatic voltage detection on A733

A733 uses two-bit voltage-mode fields, but the handlers selected when v7.4-rc1 added A733 support program them as one-bit fields. The R-PIO handler also writes an A523 control register absent on A733.

Add BIAS_VOLTAGE_PIO_POW_AUTO to select auto (01) in every field of POW_MOD_SEL at controller init and skip per-pin voltage setup. Use it for both A733 controllers: the A733 User Manual v1.00 documents 01 as auto in sections 18.14.6.1 and 18.14.7.20. Give A733-R a separate descriptor so A523-R keeps its existing voltage handling.

Fixes 0535bfbfa97b ("pinctrl: sunxi: add support for the Allwinner A733")
Fixes 31d68e10381c ("pinctrl: sunxi: a523-r: add a733-r compatible string")
Link https://lore.kernel.org/r/[email protected] open here
Suggested-by Andre Przywara <[email protected]>
Suggested-by Vinicius Pedrosa <[email protected]>
Signed-off-by Enzo Adriano <[email protected]>

---
Changes in v3:
- Set every two-bit field to AUTO at init on both A733 controllers.
- Shorten the description; retain A523-R's existing handling.
- Drop Vinicius' Tested-by because the voltage-mode programming changed. Keep his Suggested-by for the separate A733-R descriptor.

v2: https://lore.kernel.org/r/[email protected]
Replaces Andre's RFT: https://lore.kernel.org/r/[email protected]

Tests: arm64 defconfig sunxi W=1, boot-stack Image W=1 and DTB W=2 built. Not tested: board boot, 1.8 V switching, A523.

 drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c | 19 +++++++++++++++----
 drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c   |  2 +-
 drivers/pinctrl/sunxi/pinctrl-sunxi.c         |  7 ++++++-
 drivers/pinctrl/sunxi/pinctrl-sunxi.h         |  2 ++
 4 files changed, 24 insertions(+), 6 deletions(-)
drivers/pinctrl/sunxi/pinctrl-sun55i-a523-r.c +15 -4
index cffc1e53eef1..006754c0645f 100644
@@ -30,17 +30,28 @@ static struct sunxi_pinctrl_desc a523_r_pinctrl_data = {
 	.pin_base = PL_BASE,
 };
 
+static struct sunxi_pinctrl_desc a733_r_pinctrl_data = {
+	.irq_banks = ARRAY_SIZE(a523_r_irq_bank_map),
+	.irq_bank_map = a523_r_irq_bank_map,
+	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_AUTO,
+	.pin_base = PL_BASE,
+};
+
 static int a523_r_pinctrl_probe(struct platform_device *pdev)
 {
+	struct sunxi_pinctrl_desc *desc;
+
+	desc = (struct sunxi_pinctrl_desc *)of_device_get_match_data(&pdev->dev);
 	return sunxi_pinctrl_dt_table_init(pdev, a523_r_nr_bank_pins,
-					   a523_r_irq_bank_muxes,
-					   &a523_r_pinctrl_data,
+					   a523_r_irq_bank_muxes, desc,
 					   SUNXI_PINCTRL_NCAT2_REG_LAYOUT);
 }
 
 static const struct of_device_id a523_r_pinctrl_match[] = {
-	{ .compatible = "allwinner,sun55i-a523-r-pinctrl", },
-	{ .compatible = "allwinner,sun60i-a733-r-pinctrl", },
+	{ .compatible = "allwinner,sun55i-a523-r-pinctrl",
+	  .data = &a523_r_pinctrl_data },
+	{ .compatible = "allwinner,sun60i-a733-r-pinctrl",
+	  .data = &a733_r_pinctrl_data },
 	{}
 };
drivers/pinctrl/sunxi/pinctrl-sun60i-a733.c +1 -1
index ca82f08a3a65..e095abbb7232 100644
@@ -24,7 +24,7 @@ static const u8 a733_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
 static struct sunxi_pinctrl_desc a733_pinctrl_data = {
 	.irq_banks = 10,
 	.irq_read_needs_mux = true,
-	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
+	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_AUTO,
 };
 
 static int a733_pinctrl_probe(struct platform_device *pdev)
drivers/pinctrl/sunxi/pinctrl-sunxi.c +6 -1
index 3ee5012463da..444930d3c389 100644
@@ -732,7 +732,8 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl,
 	u32 val, reg;
 	int uV;
 
-	if (!pctl->desc->io_bias_cfg_variant)
+	if (pctl->desc->io_bias_cfg_variant == BIAS_VOLTAGE_NONE ||
+	    pctl->desc->io_bias_cfg_variant == BIAS_VOLTAGE_PIO_POW_AUTO)
 		return 0;
 
 	uV = regulator_get_voltage(supply);

@@ -1659,6 +1660,10 @@ int sunxi_pinctrl_init_with_flags(struct platform_device *pdev,
 	if (IS_ERR(clk))
 		return PTR_ERR(clk);
 
+	/* Select auto (01) for every bank, including shared VCC-IO. */
+	if (desc->io_bias_cfg_variant == BIAS_VOLTAGE_PIO_POW_AUTO)
+		writel(0x55555555, pctl->membase + pctl->pow_mod_sel_offset);
+
 	/*
 	 * Seed the output latch shadow from the hardware so pins the
 	 * bootloader left in output mode keep their state; see
drivers/pinctrl/sunxi/pinctrl-sunxi.h +2 -0
index 7c2f29e75519..7b36c5c2263e 100644
@@ -130,6 +130,8 @@ enum sunxi_desc_bias_voltage {
 	 */
 	BIAS_VOLTAGE_PIO_POW_MODE_CTL,
 	BIAS_VOLTAGE_PIO_POW_MODE_CTL_INV,
+	/* Two-bit PIO_POW_MOD_SEL fields set to automatic voltage detection. */
+	BIAS_VOLTAGE_PIO_POW_AUTO,
 };
 
 struct sunxi_desc_function {

base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4

Signature · 1 line
2.53.0
Tested-by on v3 1/1
#1 lore raw
Quoted 2 lines · Enzo Adriano

Add BIAS_VOLTAGE_PIO_POW_AUTO to select auto (01) in every field of POW_MOD_SEL at controller init and skip per-pin voltage setup.

Tested-by Vinicius Pedrosa <[email protected]> # Radxa Cubie A7Z

Tested with the posted prerequisites and my local board DT. POW_MOD_SEL reads back 0x05555555 on the main PIO and 0x00055555 on R-PIO, and UART0, MMC0 at 3.3 V, R-I2C0/PMIC and GPIO interrupts on eight main PIO banks worked.