mx5: cosmetic: Clean up lowlevel_init

PATCH Superseded Benoît Thébaudeau 3 participants 22 messages Aug 14, 2012 – Nov 19, 2012

Subsystems (3)

Arm (32-bit) Arm i.MX and Layerscape Arm/actions semi architecture

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Benoît Thébaudeau

author

2012-08-14 14:43 UTC #0 lore raw

PATCH 1/4 mx5: cosmetic: Clean up lowlevel_init

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S         |   46 ++++++++++----------
 1 file changed, 23 insertions(+), 23 deletions(-)

arch/arm/cpu/armv7/mx5/lowlevel_init.S +23 ~~-23~~

index 683a7b5..a40b84f 100644
@@ -36,9 +36,9 @@
 	/* reconfigure L2 cache aux control reg */
 	mov r0, #0xC0			/* tag RAM */
 	add r0, r0, #0x4		/* data RAM */
-	orr r0, r0, #(1 << 24)		/* disable write allocate delay */
-	orr r0, r0, #(1 << 23)		/* disable write allocate combine */
-	orr r0, r0, #(1 << 22)		/* disable write allocate */
+	orr r0, r0, #1 << 24		/* disable write allocate delay */
+	orr r0, r0, #1 << 23		/* disable write allocate combine */
+	orr r0, r0, #1 << 22		/* disable write allocate */
 
 #if defined(CONFIG_MX51)
 	ldr r1, =0x0

@@ -46,7 +46,7 @@
 	cmp r3, #0x10
 
 	/* disable write combine for TO 2 and lower revs */
-	orrls r0, r0, #(1 << 25)
+	orrls r0, r0, #1 << 25
 #endif
 
 	mcr 15, 1, r0, c9, c0, 2

@@ -247,9 +247,9 @@
 	movhi r1, #0
 #else
 	mov r1, #0
-
 #endif
 	str r1, [r0, #CLKCTL_CACRR]
+
 	/* Switch ARM back to PLL 1 */
 	mov r1, #0
 	str r1, [r0, #CLKCTL_CCSR]

@@ -288,9 +288,9 @@
 	/* Switch peripheral to PLL2 */
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x00808145
-	orr r1, r1, #(2 << 10)
-	orr r1, r1, #(0 << 16)
-	orr r1, r1, #(1 << 19)
+	orr r1, r1, #2 << 10
+	orr r1, r1, #0 << 16
+	orr r1, r1, #1 << 19
 	str r1, [r0, #CLKCTL_CBCDR]
 
 	ldr r1, =0x00016154

@@ -331,10 +331,10 @@ ENTRY(lowlevel_init)
 #if defined(CONFIG_MX51)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]
-	orr r1, r1, #(1 << 23)
+	orr r1, r1, #1 << 23
 	str r1, [r0, #0x0]
 	ldr r1, [r0, #0x4]
-	orr r1, r1, #(1 << 23)
+	orr r1, r1, #1 << 23
 	str r1, [r0, #0x4]
 #endif

@@ -351,16 +351,16 @@ ENTRY(lowlevel_init)
 ENDPROC(lowlevel_init)
 
 /* Board level setting value */
-W_DP_OP_864:              .word DP_OP_864
-W_DP_MFD_864:             .word DP_MFD_864
-W_DP_MFN_864:             .word DP_MFN_864
-W_DP_MFN_800_DIT:         .word DP_MFN_800_DIT
-W_DP_OP_800:              .word DP_OP_800
-W_DP_MFD_800:             .word DP_MFD_800
-W_DP_MFN_800:             .word DP_MFN_800
-W_DP_OP_665:              .word DP_OP_665
-W_DP_MFD_665:             .word DP_MFD_665
-W_DP_MFN_665:             .word DP_MFN_665
-W_DP_OP_216:              .word DP_OP_216
-W_DP_MFD_216:             .word DP_MFD_216
-W_DP_MFN_216:             .word DP_MFN_216
+W_DP_OP_864:		.word DP_OP_864
+W_DP_MFD_864:		.word DP_MFD_864
+W_DP_MFN_864:		.word DP_MFN_864
+W_DP_MFN_800_DIT:	.word DP_MFN_800_DIT
+W_DP_OP_800:		.word DP_OP_800
+W_DP_MFD_800:		.word DP_MFD_800
+W_DP_MFN_800:		.word DP_MFN_800
+W_DP_OP_665:		.word DP_OP_665
+W_DP_MFD_665:		.word DP_MFD_665
+W_DP_MFN_665:		.word DP_MFN_665
+W_DP_OP_216:		.word DP_OP_216
+W_DP_MFD_216:		.word DP_MFD_216
+W_DP_MFN_216:		.word DP_MFN_216

Benoît Thébaudeau

author

2012-08-14 14:44 UTC #1 lore raw

PATCH 2/4 mx5: Optimize lowlevel_init code size

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S         |  112 +++++++++++---------
 1 file changed, 59 insertions(+), 53 deletions(-)

arch/arm/cpu/armv7/mx5/lowlevel_init.S +59 ~~-53~~

index a40b84f..529e35b 100644
@@ -24,6 +24,8 @@
 #include <generated/asm-offsets.h>
 #include <linux/linkage.h>
 
+.section ".text.init", "x"
+
 /*
  * L2CC Cache setup/invalidation/disable
  */

@@ -34,15 +36,14 @@
 	mcr 15, 0, r0, c1, c0, 1
 
 	/* reconfigure L2 cache aux control reg */
-	mov r0, #0xC0			/* tag RAM */
-	add r0, r0, #0x4		/* data RAM */
-	orr r0, r0, #1 << 24		/* disable write allocate delay */
-	orr r0, r0, #1 << 23		/* disable write allocate combine */
-	orr r0, r0, #1 << 22		/* disable write allocate */
+	ldr r0, =0xC0 |			/* tag RAM */ \
+	         0x4 |			/* data RAM */ \
+	         1 << 24 |		/* disable write allocate delay */ \
+	         1 << 23 |		/* disable write allocate combine */ \
+	         1 << 22		/* disable write allocate */
 
 #if defined(CONFIG_MX51)
-	ldr r1, =0x0
-	ldr r3, [r1, #ROM_SI_REV]
+	ldr r3, [r4, #ROM_SI_REV]
 	cmp r3, #0x10
 
 	/* disable write combine for TO 2 and lower revs */

@@ -84,8 +85,7 @@
 	ldr r1, =0x00000203
 	str r1, [r0, #0x40]
 
-	ldr r1, =0x0
-	str r1, [r0, #0x44]
+	str r4, [r0, #0x44]
 
 	ldr r1, =0x00120125
 	str r1, [r0, #0x9C]

@@ -98,20 +98,29 @@
 
 .macro setup_pll pll, freq
 	ldr r0, =\pll
+	adr r2, W_DP_\freq
+	bl setup_pll_func
+.endm
+
+#define W_DP_OP		0
+#define W_DP_MFD	4
+#define W_DP_MFN	8
+
+setup_pll_func:
 	ldr r1, =0x00001232
 	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
 	mov r1, #0x2
 	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
 
-	ldr r1, W_DP_OP_\freq
+	ldr r1, [r2, #W_DP_OP]
 	str r1, [r0, #PLL_DP_OP]
 	str r1, [r0, #PLL_DP_HFS_OP]
 
-	ldr r1,	W_DP_MFD_\freq
+	ldr r1, [r2, #W_DP_MFD]
 	str r1, [r0, #PLL_DP_MFD]
 	str r1, [r0, #PLL_DP_HFS_MFD]
 
-	ldr r1,  W_DP_MFN_\freq
+	ldr r1, [r2, #W_DP_MFN]
 	str r1, [r0, #PLL_DP_MFN]
 	str r1, [r0, #PLL_DP_HFS_MFN]

@@ -120,12 +129,13 @@
 1:	ldr r1, [r0, #PLL_DP_CTL]
 	ands r1, r1, #0x1
 	beq 1b
-.endm
+
+	/* r10 saved upper lr */
+	mov pc, lr
 
 .macro setup_pll_errata pll, freq
 	ldr r2, =\pll
-	mov r1, #0x0
-	str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
+	str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
 	ldr r1, =0x00001236
 	str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
 1:	ldr r1, [r2, #PLL_DP_CTL]    /* Wait for lock */

@@ -158,10 +168,9 @@
 	/* Gate of clocks to the peripherals first */
 	ldr r1, =0x3FFFFFFF
 	str r1, [r0, #CLKCTL_CCGR0]
-	ldr r1, =0x0
-	str r1, [r0, #CLKCTL_CCGR1]
-	str r1, [r0, #CLKCTL_CCGR2]
-	str r1, [r0, #CLKCTL_CCGR3]
+	str r4, [r0, #CLKCTL_CCGR1]
+	str r4, [r0, #CLKCTL_CCGR2]
+	str r4, [r0, #CLKCTL_CCGR3]
 
 	ldr r1, =0x00030000
 	str r1, [r0, #CLKCTL_CCGR4]

@@ -184,11 +193,10 @@
 #else
 	ldr r1, =0x3FFFFFFF
 	str r1, [r0, #CLKCTL_CCGR0]
-	ldr r1, =0x0
-	str r1, [r0, #CLKCTL_CCGR1]
-	str r1, [r0, #CLKCTL_CCGR2]
-	str r1, [r0, #CLKCTL_CCGR3]
-	str r1, [r0, #CLKCTL_CCGR7]
+	str r4, [r0, #CLKCTL_CCGR1]
+	str r4, [r0, #CLKCTL_CCGR2]
+	str r4, [r0, #CLKCTL_CCGR3]
+	str r4, [r0, #CLKCTL_CCGR7]
 
 	ldr r1, =0x00030000
 	str r1, [r0, #CLKCTL_CCGR4]

@@ -214,8 +222,7 @@
 
 	/* Switch peripheral to PLL 3 */
 	ldr r0, =CCM_BASE_ADDR
-	ldr r1, =0x000010C0
-	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+	ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	ldr r1, =0x13239145
 	str r1, [r0, #CLKCTL_CBCDR]

@@ -225,8 +232,7 @@
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x19239145
 	str r1, [r0, #CLKCTL_CBCDR]
-	ldr r1, =0x000020C0
-	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+	ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 #endif
 	setup_pll PLL3_BASE_ADDR, 216

@@ -240,8 +246,7 @@
 
 #if defined(CONFIG_MX51)
 	/* Run 3.0@Full speed, for other TO's wait till we increase VDDGP */
-	ldr r1, =0x0
-	ldr r3, [r1, #ROM_SI_REV]
+	ldr r3, [r4, #ROM_SI_REV]
 	cmp r3, #0x10
 	movls r1, #0x1
 	movhi r1, #0

@@ -251,14 +256,12 @@
 	str r1, [r0, #CLKCTL_CACRR]
 
 	/* Switch ARM back to PLL 1 */
-	mov r1, #0
-	str r1, [r0, #CLKCTL_CCSR]
+	str r4, [r0, #CLKCTL_CCSR]
 
 #if defined(CONFIG_MX51)
 	/* setup the rest */
 	/* Use lp_apm (24MHz) source for perclk */
-	ldr r1, =0x000020C2
-	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+	ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
 	ldr r1, =CONFIG_SYS_CLKTL_CBCDR

@@ -289,7 +292,6 @@
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x00808145
 	orr r1, r1, #2 << 10
-	orr r1, r1, #0 << 16
 	orr r1, r1, #1 << 19
 	str r1, [r0, #CLKCTL_CBCDR]

@@ -310,8 +312,7 @@
 	cmp r1, #0x0
 	bne 1b
 
-	mov r1, #0x0
-	str r1, [r0, #CLKCTL_CCDR]
+	str r4, [r0, #CLKCTL_CCDR]
 
 	/* for cko - for ARM div by 8 */
 	mov r1, #0x000A0000

@@ -325,9 +326,10 @@
 	strh r1, [r0]
 .endm
 
-.section ".text.init", "x"
-
 ENTRY(lowlevel_init)
+	mov r10, lr
+	mov r4, #0	/* Fix R4 to 0 */
+
 #if defined(CONFIG_MX51)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]

@@ -346,21 +348,25 @@ ENTRY(lowlevel_init)
 
 	init_clock
 
-	/* r12 saved upper lr*/
-	mov pc,lr
+	mov pc, r10
 ENDPROC(lowlevel_init)
 
 /* Board level setting value */
-W_DP_OP_864:		.word DP_OP_864
-W_DP_MFD_864:		.word DP_MFD_864
-W_DP_MFN_864:		.word DP_MFN_864
+#if defined(CONFIG_MX51_PLL_ERRATA)
+W_DP_864:		.word DP_OP_864
+			.word DP_MFD_864
+			.word DP_MFN_864
 W_DP_MFN_800_DIT:	.word DP_MFN_800_DIT
-W_DP_OP_800:		.word DP_OP_800
-W_DP_MFD_800:		.word DP_MFD_800
-W_DP_MFN_800:		.word DP_MFN_800
-W_DP_OP_665:		.word DP_OP_665
-W_DP_MFD_665:		.word DP_MFD_665
-W_DP_MFN_665:		.word DP_MFN_665
-W_DP_OP_216:		.word DP_OP_216
-W_DP_MFD_216:		.word DP_MFD_216
-W_DP_MFN_216:		.word DP_MFN_216
+#else
+W_DP_800:		.word DP_OP_800
+			.word DP_MFD_800
+			.word DP_MFN_800
+#endif
+#if defined(CONFIG_MX51)
+W_DP_665:		.word DP_OP_665
+			.word DP_MFD_665
+			.word DP_MFN_665
+#endif
+W_DP_216:		.word DP_OP_216
+			.word DP_MFD_216
+			.word DP_MFN_216

Otavio Salvador

2012-08-14 14:52 UTC #2 lore raw

PATCH 2/4 mx5: Optimize lowlevel_init code size

Quoted 2 lines · Beno?t Th?baudeau

Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Stefano Babic <[email protected]>

What the patch does? Please use long description for it.

Signature · 3 lines

Otavio Salvador                             O.S. Systems
E-mail: otavio at ossystems.com.br  http://www.ossystems.com.br
Mobile: +55 53 9981-7854              http://projetos.ossystems.com.br

Benoît Thébaudeau

author

2012-08-14 15:19 UTC #3 lore raw

PATCH v2 2/4 mx5: Optimize lowlevel_init code size

Optimize mx5 lowlevel_init.S code size:
- Compute values at compile time rather than at runtime where possible.
- Assign r4 to hold the zero value rather than setting registers to 0 again and again.
- Associate a function to setup_pll rather than expanding its large macro code multiple times.
- Allocate constant values in section only if used.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2:
- Make patch description more detailed.

 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S         |  112 +++++++++++---------
 1 file changed, 59 insertions(+), 53 deletions(-)

arch/arm/cpu/armv7/mx5/lowlevel_init.S +59 ~~-53~~

index a40b84f..529e35b 100644
@@ -24,6 +24,8 @@
 #include <generated/asm-offsets.h>
 #include <linux/linkage.h>
 
+.section ".text.init", "x"
+
 /*
  * L2CC Cache setup/invalidation/disable
  */

@@ -34,15 +36,14 @@
 	mcr 15, 0, r0, c1, c0, 1
 
 	/* reconfigure L2 cache aux control reg */
-	mov r0, #0xC0			/* tag RAM */
-	add r0, r0, #0x4		/* data RAM */
-	orr r0, r0, #1 << 24		/* disable write allocate delay */
-	orr r0, r0, #1 << 23		/* disable write allocate combine */
-	orr r0, r0, #1 << 22		/* disable write allocate */
+	ldr r0, =0xC0 |			/* tag RAM */ \
+	         0x4 |			/* data RAM */ \
+	         1 << 24 |		/* disable write allocate delay */ \
+	         1 << 23 |		/* disable write allocate combine */ \
+	         1 << 22		/* disable write allocate */
 
 #if defined(CONFIG_MX51)
-	ldr r1, =0x0
-	ldr r3, [r1, #ROM_SI_REV]
+	ldr r3, [r4, #ROM_SI_REV]
 	cmp r3, #0x10
 
 	/* disable write combine for TO 2 and lower revs */

@@ -84,8 +85,7 @@
 	ldr r1, =0x00000203
 	str r1, [r0, #0x40]
 
-	ldr r1, =0x0
-	str r1, [r0, #0x44]
+	str r4, [r0, #0x44]
 
 	ldr r1, =0x00120125
 	str r1, [r0, #0x9C]

@@ -98,20 +98,29 @@
 
 .macro setup_pll pll, freq
 	ldr r0, =\pll
+	adr r2, W_DP_\freq
+	bl setup_pll_func
+.endm
+
+#define W_DP_OP		0
+#define W_DP_MFD	4
+#define W_DP_MFN	8
+
+setup_pll_func:
 	ldr r1, =0x00001232
 	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
 	mov r1, #0x2
 	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
 
-	ldr r1, W_DP_OP_\freq
+	ldr r1, [r2, #W_DP_OP]
 	str r1, [r0, #PLL_DP_OP]
 	str r1, [r0, #PLL_DP_HFS_OP]
 
-	ldr r1,	W_DP_MFD_\freq
+	ldr r1, [r2, #W_DP_MFD]
 	str r1, [r0, #PLL_DP_MFD]
 	str r1, [r0, #PLL_DP_HFS_MFD]
 
-	ldr r1,  W_DP_MFN_\freq
+	ldr r1, [r2, #W_DP_MFN]
 	str r1, [r0, #PLL_DP_MFN]
 	str r1, [r0, #PLL_DP_HFS_MFN]

@@ -120,12 +129,13 @@
 1:	ldr r1, [r0, #PLL_DP_CTL]
 	ands r1, r1, #0x1
 	beq 1b
-.endm
+
+	/* r10 saved upper lr */
+	mov pc, lr
 
 .macro setup_pll_errata pll, freq
 	ldr r2, =\pll
-	mov r1, #0x0
-	str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
+	str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
 	ldr r1, =0x00001236
 	str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
 1:	ldr r1, [r2, #PLL_DP_CTL]    /* Wait for lock */

@@ -158,10 +168,9 @@
 	/* Gate of clocks to the peripherals first */
 	ldr r1, =0x3FFFFFFF
 	str r1, [r0, #CLKCTL_CCGR0]
-	ldr r1, =0x0
-	str r1, [r0, #CLKCTL_CCGR1]
-	str r1, [r0, #CLKCTL_CCGR2]
-	str r1, [r0, #CLKCTL_CCGR3]
+	str r4, [r0, #CLKCTL_CCGR1]
+	str r4, [r0, #CLKCTL_CCGR2]
+	str r4, [r0, #CLKCTL_CCGR3]
 
 	ldr r1, =0x00030000
 	str r1, [r0, #CLKCTL_CCGR4]

@@ -184,11 +193,10 @@
 #else
 	ldr r1, =0x3FFFFFFF
 	str r1, [r0, #CLKCTL_CCGR0]
-	ldr r1, =0x0
-	str r1, [r0, #CLKCTL_CCGR1]
-	str r1, [r0, #CLKCTL_CCGR2]
-	str r1, [r0, #CLKCTL_CCGR3]
-	str r1, [r0, #CLKCTL_CCGR7]
+	str r4, [r0, #CLKCTL_CCGR1]
+	str r4, [r0, #CLKCTL_CCGR2]
+	str r4, [r0, #CLKCTL_CCGR3]
+	str r4, [r0, #CLKCTL_CCGR7]
 
 	ldr r1, =0x00030000
 	str r1, [r0, #CLKCTL_CCGR4]

@@ -214,8 +222,7 @@
 
 	/* Switch peripheral to PLL 3 */
 	ldr r0, =CCM_BASE_ADDR
-	ldr r1, =0x000010C0
-	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+	ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	ldr r1, =0x13239145
 	str r1, [r0, #CLKCTL_CBCDR]

@@ -225,8 +232,7 @@
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x19239145
 	str r1, [r0, #CLKCTL_CBCDR]
-	ldr r1, =0x000020C0
-	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+	ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 #endif
 	setup_pll PLL3_BASE_ADDR, 216

@@ -240,8 +246,7 @@
 
 #if defined(CONFIG_MX51)
 	/* Run 3.0@Full speed, for other TO's wait till we increase VDDGP */
-	ldr r1, =0x0
-	ldr r3, [r1, #ROM_SI_REV]
+	ldr r3, [r4, #ROM_SI_REV]
 	cmp r3, #0x10
 	movls r1, #0x1
 	movhi r1, #0

@@ -251,14 +256,12 @@
 	str r1, [r0, #CLKCTL_CACRR]
 
 	/* Switch ARM back to PLL 1 */
-	mov r1, #0
-	str r1, [r0, #CLKCTL_CCSR]
+	str r4, [r0, #CLKCTL_CCSR]
 
 #if defined(CONFIG_MX51)
 	/* setup the rest */
 	/* Use lp_apm (24MHz) source for perclk */
-	ldr r1, =0x000020C2
-	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+	ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
 	ldr r1, =CONFIG_SYS_CLKTL_CBCDR

@@ -289,7 +292,6 @@
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x00808145
 	orr r1, r1, #2 << 10
-	orr r1, r1, #0 << 16
 	orr r1, r1, #1 << 19
 	str r1, [r0, #CLKCTL_CBCDR]

@@ -310,8 +312,7 @@
 	cmp r1, #0x0
 	bne 1b
 
-	mov r1, #0x0
-	str r1, [r0, #CLKCTL_CCDR]
+	str r4, [r0, #CLKCTL_CCDR]
 
 	/* for cko - for ARM div by 8 */
 	mov r1, #0x000A0000

@@ -325,9 +326,10 @@
 	strh r1, [r0]
 .endm
 
-.section ".text.init", "x"
-
 ENTRY(lowlevel_init)
+	mov r10, lr
+	mov r4, #0	/* Fix R4 to 0 */
+
 #if defined(CONFIG_MX51)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]

@@ -346,21 +348,25 @@ ENTRY(lowlevel_init)
 
 	init_clock
 
-	/* r12 saved upper lr*/
-	mov pc,lr
+	mov pc, r10
 ENDPROC(lowlevel_init)
 
 /* Board level setting value */
-W_DP_OP_864:		.word DP_OP_864
-W_DP_MFD_864:		.word DP_MFD_864
-W_DP_MFN_864:		.word DP_MFN_864
+#if defined(CONFIG_MX51_PLL_ERRATA)
+W_DP_864:		.word DP_OP_864
+			.word DP_MFD_864
+			.word DP_MFN_864
 W_DP_MFN_800_DIT:	.word DP_MFN_800_DIT
-W_DP_OP_800:		.word DP_OP_800
-W_DP_MFD_800:		.word DP_MFD_800
-W_DP_MFN_800:		.word DP_MFN_800
-W_DP_OP_665:		.word DP_OP_665
-W_DP_MFD_665:		.word DP_MFD_665
-W_DP_MFN_665:		.word DP_MFN_665
-W_DP_OP_216:		.word DP_OP_216
-W_DP_MFD_216:		.word DP_MFD_216
-W_DP_MFN_216:		.word DP_MFN_216
+#else
+W_DP_800:		.word DP_OP_800
+			.word DP_MFD_800
+			.word DP_MFN_800
+#endif
+#if defined(CONFIG_MX51)
+W_DP_665:		.word DP_OP_665
+			.word DP_MFD_665
+			.word DP_MFN_665
+#endif
+W_DP_216:		.word DP_OP_216
+			.word DP_MFD_216
+			.word DP_MFN_216

Stefano Babic

2012-09-30 12:47 UTC #4 lore raw

PATCH v2 2/4 mx5: Optimize lowlevel_init code size

Quoted 251 lines · Beno?t Th?baudeau

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2:
- Make patch description more detailed.

 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S         |  112 +++++++++++---------
 1 file changed, 59 insertions(+), 53 deletions(-)

arch/arm/cpu/armv7/mx5/lowlevel_init.S +49 ~~-53~~

index a40b84f..529e35b 100644
@@ -24,6 +24,8 @@
 #include <generated/asm-offsets.h>
 #include <linux/linkage.h>
 
+.section ".text.init", "x"
+
 /*
  * L2CC Cache setup/invalidation/disable
  */

@@ -34,15 +36,14 @@
 	mcr 15, 0, r0, c1, c0, 1
 
 	/* reconfigure L2 cache aux control reg */
-	mov r0, #0xC0			/* tag RAM */
-	add r0, r0, #0x4		/* data RAM */
-	orr r0, r0, #1 << 24		/* disable write allocate delay */
-	orr r0, r0, #1 << 23		/* disable write allocate combine */
-	orr r0, r0, #1 << 22		/* disable write allocate */
+	ldr r0, =0xC0 |			/* tag RAM */ \
+	         0x4 |			/* data RAM */ \
+	         1 << 24 |		/* disable write allocate delay */ \
+	         1 << 23 |		/* disable write allocate combine */ \
+	         1 << 22		/* disable write allocate */
 
 #if defined(CONFIG_MX51)
-	ldr r1, =0x0
-	ldr r3, [r1, #ROM_SI_REV]
+	ldr r3, [r4, #ROM_SI_REV]
 	cmp r3, #0x10
 
 	/* disable write combine for TO 2 and lower revs */

@@ -84,8 +85,7 @@
 	ldr r1, =0x00000203
 	str r1, [r0, #0x40]
 
-	ldr r1, =0x0
-	str r1, [r0, #0x44]
+	str r4, [r0, #0x44]
 
 	ldr r1, =0x00120125
 	str r1, [r0, #0x9C]

@@ -98,20 +98,29 @@
 
 .macro setup_pll pll, freq
 	ldr r0, =\pll
+	adr r2, W_DP_\freq
+	bl setup_pll_func
+.endm
+
+#define W_DP_OP		0
+#define W_DP_MFD	4
+#define W_DP_MFN	8
+
+setup_pll_func:
 	ldr r1, =0x00001232
 	str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
 	mov r1, #0x2
 	str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
 
-	ldr r1, W_DP_OP_\freq
+	ldr r1, [r2, #W_DP_OP]
 	str r1, [r0, #PLL_DP_OP]
 	str r1, [r0, #PLL_DP_HFS_OP]
 
-	ldr r1,	W_DP_MFD_\freq
+	ldr r1, [r2, #W_DP_MFD]
 	str r1, [r0, #PLL_DP_MFD]
 	str r1, [r0, #PLL_DP_HFS_MFD]
 
-	ldr r1,  W_DP_MFN_\freq
+	ldr r1, [r2, #W_DP_MFN]
 	str r1, [r0, #PLL_DP_MFN]
 	str r1, [r0, #PLL_DP_HFS_MFN]

@@ -120,12 +129,13 @@
 1:	ldr r1, [r0, #PLL_DP_CTL]
 	ands r1, r1, #0x1
 	beq 1b
-.endm
+
+	/* r10 saved upper lr */
+	mov pc, lr
 
 .macro setup_pll_errata pll, freq
 	ldr r2, =\pll
-	mov r1, #0x0
-	str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
+	str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
 	ldr r1, =0x00001236
 	str r1, [r2, #PLL_DP_CTL]    /* Restart PLL with PLM=1 */
 1:	ldr r1, [r2, #PLL_DP_CTL]    /* Wait for lock */

@@ -158,10 +168,9 @@
 	/* Gate of clocks to the peripherals first */
 	ldr r1, =0x3FFFFFFF
 	str r1, [r0, #CLKCTL_CCGR0]
-	ldr r1, =0x0
-	str r1, [r0, #CLKCTL_CCGR1]
-	str r1, [r0, #CLKCTL_CCGR2]
-	str r1, [r0, #CLKCTL_CCGR3]
+	str r4, [r0, #CLKCTL_CCGR1]
+	str r4, [r0, #CLKCTL_CCGR2]
+	str r4, [r0, #CLKCTL_CCGR3]
 
 	ldr r1, =0x00030000
 	str r1, [r0, #CLKCTL_CCGR4]

@@ -184,11 +193,10 @@
 #else
 	ldr r1, =0x3FFFFFFF
 	str r1, [r0, #CLKCTL_CCGR0]
-	ldr r1, =0x0
-	str r1, [r0, #CLKCTL_CCGR1]
-	str r1, [r0, #CLKCTL_CCGR2]
-	str r1, [r0, #CLKCTL_CCGR3]
-	str r1, [r0, #CLKCTL_CCGR7]
+	str r4, [r0, #CLKCTL_CCGR1]
+	str r4, [r0, #CLKCTL_CCGR2]
+	str r4, [r0, #CLKCTL_CCGR3]
+	str r4, [r0, #CLKCTL_CCGR7]
 
 	ldr r1, =0x00030000
 	str r1, [r0, #CLKCTL_CCGR4]

@@ -214,8 +222,7 @@
 
 	/* Switch peripheral to PLL 3 */
 	ldr r0, =CCM_BASE_ADDR
-	ldr r1, =0x000010C0
-	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+	ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	ldr r1, =0x13239145
 	str r1, [r0, #CLKCTL_CBCDR]

@@ -225,8 +232,7 @@
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x19239145
 	str r1, [r0, #CLKCTL_CBCDR]
-	ldr r1, =0x000020C0
-	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+	ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 #endif
 	setup_pll PLL3_BASE_ADDR, 216

@@ -240,8 +246,7 @@
 
 #if defined(CONFIG_MX51)
 	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
-	ldr r1, =0x0
-	ldr r3, [r1, #ROM_SI_REV]
+	ldr r3, [r4, #ROM_SI_REV]
 	cmp r3, #0x10
 	movls r1, #0x1
 	movhi r1, #0

@@ -251,14 +256,12 @@
 	str r1, [r0, #CLKCTL_CACRR]
 
 	/* Switch ARM back to PLL 1 */
-	mov r1, #0
-	str r1, [r0, #CLKCTL_CCSR]
+	str r4, [r0, #CLKCTL_CCSR]
 
 #if defined(CONFIG_MX51)
 	/* setup the rest */
 	/* Use lp_apm (24MHz) source for perclk */
-	ldr r1, =0x000020C2
-	orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+	ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
 	str r1, [r0, #CLKCTL_CBCMR]
 	/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
 	ldr r1, =CONFIG_SYS_CLKTL_CBCDR

@@ -289,7 +292,6 @@
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x00808145
 	orr r1, r1, #2 << 10
-	orr r1, r1, #0 << 16
 	orr r1, r1, #1 << 19
 	str r1, [r0, #CLKCTL_CBCDR]

@@ -310,8 +312,7 @@
 	cmp r1, #0x0
 	bne 1b
 
-	mov r1, #0x0
-	str r1, [r0, #CLKCTL_CCDR]
+	str r4, [r0, #CLKCTL_CCDR]
 
 	/* for cko - for ARM div by 8 */
 	mov r1, #0x000A0000

@@ -325,9 +326,10 @@
 	strh r1, [r0]
 .endm
 
-.section ".text.init", "x"
-
 ENTRY(lowlevel_init)
+	mov r10, lr
+	mov r4, #0	/* Fix R4 to 0 */
+
 #if defined(CONFIG_MX51)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]

@@ -346,21 +348,25 @@ ENTRY(lowlevel_init)
 
 	init_clock
 
-	/* r12 saved upper lr*/
-	mov pc,lr
+	mov pc, r10
 ENDPROC(lowlevel_init)
 
 /* Board level setting value */
-W_DP_OP_864:		.word DP_OP_864
-W_DP_MFD_864:		.word DP_MFD_864
-W_DP_MFN_864:		.word DP_MFN_864
+#if defined(CONFIG_MX51_PLL_ERRATA)
+W_DP_864:		.word DP_OP_864
+			.word DP_MFD_864
+			.word DP_MFN_864
 W_DP_MFN_800_DIT:	.word DP_MFN_800_DIT
-W_DP_OP_800:		.word DP_OP_800
-W_DP_MFD_800:		.word DP_MFD_800
-W_DP_MFN_800:		.word DP_MFN_800
-W_DP_OP_665:		.word DP_OP_665
-W_DP_MFD_665:		.word DP_MFD_665
-W_DP_MFN_665:		.word DP_MFN_665
-W_DP_OP_216:		.word DP_OP_216
-W_DP_MFD_216:		.word DP_MFD_216
-W_DP_MFN_216:		.word DP_MFN_216
+#else
+W_DP_800:		.word DP_OP_800
+			.word DP_MFD_800

arch/arm/cpu/armv7/mx5/lowlevel_init.S ENTRY(lowlevel_init) · line 372

Quoted 10 lines

arch/arm/cpu/armv7/mx5/lowlevel_init.S +10 -0

+			.word DP_MFN_800
+#endif
+#if defined(CONFIG_MX51)
+W_DP_665:		.word DP_OP_665
+			.word DP_MFD_665
+			.word DP_MFN_665
+#endif
+W_DP_216:		.word DP_OP_216
+			.word DP_MFD_216
+			.word DP_MFN_216

I don't see any issue with this patch.

Tested also on mx53loco.

Tested-by Stefano Babic <[email protected]>

Acked-by Stefano Babic <[email protected]>

Regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2012-09-30 12:49 UTC #5 lore raw

PATCH v2 2/4 mx5: Optimize lowlevel_init code size

In reply to Benoît Thébaudeau

Quoted 11 lines · Beno?t Th?baudeau

Optimize mx5 lowlevel_init.S code size:
- Compute values at compile time rather than at runtime where possible.
- Assign r4 to hold the zero value rather than setting registers to 0 again and again.
- Associate a function to setup_pll rather than expanding its large macro code multiple times.
- Allocate constant values in section only if used.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Stefano Babic <[email protected]>
---

Applied to u-boot-imx, next branch, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Benoît Thébaudeau

author

2012-08-14 14:44 UTC #6 lore raw

PATCH 3/4 mx5: Optimize lowlevel_init for TO 3

In reply to Benoît Thébaudeau

Add an option to optimize away revision-specific code from lowlevel_init.S. This can be useful for recently designed boards that may not be fitted with older revisions.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S         |    4 ++--
 .../doc/README.imx5                                |    7 ++++++-
 2 files changed, 8 insertions(+), 3 deletions(-)

arch/arm/cpu/armv7/mx5/lowlevel_init.S +2 -2

index 529e35b..d0f75fa 100644
@@ -42,7 +42,7 @@
 	         1 << 23 |		/* disable write allocate combine */ \
 	         1 << 22		/* disable write allocate */
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_MX51) && !defined(CONFIG_MX51_TO_3)
 	ldr r3, [r4, #ROM_SI_REV]
 	cmp r3, #0x10

@@ -244,7 +244,7 @@ setup_pll_func:
 
 	ldr r0, =CCM_BASE_ADDR
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_MX51) && !defined(CONFIG_MX51_TO_3)
 	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
 	ldr r3, [r4, #ROM_SI_REV]
 	cmp r3, #0x10

doc/README.imx5 +6 -1

index f7eab7d..938d3da 100644
@@ -6,7 +6,12 @@ i.MX5x SoCs.
 1. CONFIGURATION OPTIONS/SETTINGS
 ---------------------------------
 
-1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata.
+1.1 CONFIG_MX51_TO_3: i.MX51 silicon revision 3 or higher.
+    This option can be enabled for these i.MX51 silicon revisions to optimize
+    away some specific behavior triggered by the detection of older silicon
+    revisions at runtime.
+
+1.2 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata.
     This option should be enabled by all boards using the i.MX51 silicon
     version up until (including) 3.0 running@800MHz.
     The PLL's in the i.MX51 processor can go out of lock due to a metastable

Otavio Salvador

2012-08-14 14:56 UTC #7 lore raw

PATCH 3/4 mx5: Optimize lowlevel_init for TO 3

Quoted 6 lines · Beno?t Th?baudeau

Add an option to optimize away revision-specific code from lowlevel_init.S. This can be useful for recently designed boards that may not be fitted with older revisions.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Stefano Babic <[email protected]>

Looking at code I somewhat understood what you did but the commit log doesn't describe the change you did neither why you did.

Signature · 3 lines

Otavio Salvador                             O.S. Systems
E-mail: otavio at ossystems.com.br  http://www.ossystems.com.br
Mobile: +55 53 9981-7854              http://projetos.ossystems.com.br

Benoît Thébaudeau

author

2012-08-14 15:19 UTC #8 lore raw

PATCH v2 3/4 mx5: Optimize lowlevel_init for TO 3

The mx5 lowlevel_init.S contains code that detects the silicon revision at runtime, and that behaves differently if a silicon revision older than TO 3 is detected. This code is useless for recently designed boards that may not be fitted with older silicon revisions. Hence, this patch adds an option to optimize away this revision-specific code from lowlevel_init.S.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2:
- Make patch description more detailed.

 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S         |    4 ++--
 .../doc/README.imx5                                |    7 ++++++-
 2 files changed, 8 insertions(+), 3 deletions(-)

arch/arm/cpu/armv7/mx5/lowlevel_init.S +2 -2

index 529e35b..d0f75fa 100644
@@ -42,7 +42,7 @@
 	         1 << 23 |		/* disable write allocate combine */ \
 	         1 << 22		/* disable write allocate */
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_MX51) && !defined(CONFIG_MX51_TO_3)
 	ldr r3, [r4, #ROM_SI_REV]
 	cmp r3, #0x10

@@ -244,7 +244,7 @@ setup_pll_func:
 
 	ldr r0, =CCM_BASE_ADDR
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_MX51) && !defined(CONFIG_MX51_TO_3)
 	/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
 	ldr r3, [r4, #ROM_SI_REV]
 	cmp r3, #0x10

doc/README.imx5 +6 -1

index f7eab7d..938d3da 100644
@@ -6,7 +6,12 @@ i.MX5x SoCs.
 1. CONFIGURATION OPTIONS/SETTINGS
 ---------------------------------
 
-1.1 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata.
+1.1 CONFIG_MX51_TO_3: i.MX51 silicon revision 3 or higher.
+    This option can be enabled for these i.MX51 silicon revisions to optimize
+    away some specific behavior triggered by the detection of older silicon
+    revisions at runtime.
+
+1.2 CONFIG_MX51_PLL_ERRATA: Workaround for i.MX51 PLL errata.
     This option should be enabled by all boards using the i.MX51 silicon
     version up until (including) 3.0 running@800MHz.
     The PLL's in the i.MX51 processor can go out of lock due to a metastable

Stefano Babic

2012-08-20 08:20 UTC #9 lore raw

PATCH v2 3/4 mx5: Optimize lowlevel_init for TO 3

Quoted 9 lines · Beno?t Th?baudeau

The mx5 lowlevel_init.S contains code that detects the silicon revision at runtime, and that behaves differently if a silicon revision older than TO 3 is detected. This code is useless for recently designed boards that may not be fitted with older silicon revisions. Hence, this patch adds an option to optimize away this revision-specific code from lowlevel_init.S.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Stefano Babic <[email protected]>
---

Hi Beno?t,

Quoted 7 lines

Changes for v2:
- Make patch description more detailed.

 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S         |    4 ++--
 .../doc/README.imx5                                |    7 ++++++-
 2 files changed, 8 insertions(+), 3 deletions(-)

The ROM revision is currently detected at run time - because this does not fix an evident bug, your patch intends to reduce the footprint.

Then I chacked on a mx51evk, a board thet was shipped by Freescale with TO 2 (and maybe TO 1 ?), and there are surely samples with TO2 or TO3 in the world.

Without the poatch:

Configuring for mx51evk - Board: mx51evk, Options:
IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
text data bss dec hex filename
258168 15872 268464 542504 84728 ./u-boot

With the patch:

Configuring for mx51evk - Board: mx51evk, Options:
IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
text data bss dec hex filename
258140 15872 268492 542504 84728 ./u-boot

We win only 28 bytes - on the other side, we had a CONFIG_ that is not so clear how to be used, mainly if a board as the mx51evk was shipped with both versions.

I think the advantages are negligible here.

Best regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Benoît Thébaudeau

author

2012-08-20 10:12 UTC #10 lore raw

PATCH v2 3/4 mx5: Optimize lowlevel_init for TO 3

Hi Stefano,

Quoted 49 lines · Beno?t Th?baudeau

Quoted 10 lines
The mx5 lowlevel_init.S contains code that detects the silicon revision at
runtime, and that behaves differently if a silicon revision older than TO 3 is
detected. This code is useless for recently designed boards that may not be
fitted with older silicon revisions. Hence, this patch adds an option to
optimize away this revision-specific code from lowlevel_init.S.
Quoted 3 lines
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Stefano Babic <[email protected]>
---
Hi Beno?t,
Quoted 7 lines
Changes for v2:
- Make patch description more detailed.
 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S         |    4 ++--
 .../doc/README.imx5                                |    7 ++++++-
 2 files changed, 8 insertions(+), 3 deletions(-)
The ROM revision is currently detected at run time - because this does
not fix an evident bug, your patch intends to reduce the footprint.
Then I chacked on a mx51evk, a board thet was shipped by Freescale with
TO 2 (and maybe TO 1 ?), and there are surely samples with TO2 or TO3 in
the world.
Without the poatch:
Configuring for mx51evk - Board: mx51evk, Options:
IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
text data bss dec hex filename
258168 15872 268464 542504 84728 ./u-boot
With the patch:
Configuring for mx51evk - Board: mx51evk, Options:
IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
text data bss dec hex filename
258140 15872 268492 542504 84728 ./u-boot

Quoted 4 lines

We win only 28 bytes - on the other side, we had a CONFIG_ that is not
so clear how to be used, mainly if a board as the mx51evk was shipped with both versions.

To make things easier, this config should be used only for boards always shipped with the newer versions.

Quoted 1 line

I think the advantages are negligible here.

Indeed. I needed that for a specific case where any single byte was worth saving. For upstream U-Boot, I let you decide if this is interesting enough or not.

Best regards,
Beno?t

Benoît Thébaudeau

author

2012-08-14 14:44 UTC #11 lore raw

PATCH 4/4 mx5: Mark lowlevel_init board-specific code

In reply to Benoît Thébaudeau

The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S         |    2 +-
 .../doc/README.imx5                                |    5 +++++
 .../include/configs/efikamx.h                      |    1 +
 .../include/configs/mx51evk.h                      |    1 +
 .../include/configs/vision2.h                      |    1 +
 5 files changed, 9 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/mx5/lowlevel_init.S +1 -1

index d0f75fa..b25b3a7 100644
@@ -330,7 +330,7 @@ ENTRY(lowlevel_init)
 	mov r10, lr
 	mov r4, #0	/* Fix R4 to 0 */
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SYS_MAIN_PWR_ON)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]
 	orr r1, r1, #1 << 23

doc/README.imx5 +5 -0

index 938d3da..85d476f 100644
@@ -20,3 +20,8 @@ i.MX5x SoCs.
     mode), which causes the effect of this failure to be much lower (in terms
     of frequency deviation), avoiding system failure, or@least decreasing
     the likelihood of system failure.
+
+1.3 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
+    This option should be enabled for boards having a SYS_ON_OFF_CTL signal
+    connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
+    reference designs.

include/configs/efikamx.h +1 -0

index 143b0f0..792b51b 100644
@@ -270,5 +270,6 @@
 
 #define CONFIG_SYS_DDR_CLKSEL		0
 #define CONFIG_SYS_CLKTL_CBCDR		0x59E35145
+#define CONFIG_SYS_MAIN_PWR_ON
 
 #endif

include/configs/mx51evk.h +1 -0

index e975f54..6867f7b 100644
@@ -242,6 +242,7 @@
 
 #define CONFIG_SYS_DDR_CLKSEL	0
 #define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
+#define CONFIG_SYS_MAIN_PWR_ON
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization

include/configs/vision2.h +1 -0

index ed004a6..3ce4906 100644
@@ -203,6 +203,7 @@
 /* 166 MHz DDR RAM */
 #define CONFIG_SYS_DDR_CLKSEL		0
 #define CONFIG_SYS_CLKTL_CBCDR		0x19239100
+#define CONFIG_SYS_MAIN_PWR_ON
 
 #define CONFIG_SYS_NO_FLASH

Benoît Thébaudeau

author

2012-08-15 14:34 UTC #12 lore raw

PATCH 4/4 mx5: Mark lowlevel_init board-specific code

Quoted 11 lines

The mx5 lowlevel_init.S contains board-specific code based on the reference
design. Let's keep it since it avoids creating new lowlevel_init files and it
may be used by many boards. But add a config to make it optional in order not to
cause issues on boards not following this part of the reference design.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Stefano Babic <[email protected]>

Adding missing board maintainers to Cc.

Quoted 79 lines

---
 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S         |    2 +-
 .../doc/README.imx5                                |    5 +++++
 .../include/configs/efikamx.h                      |    1 +
 .../include/configs/mx51evk.h                      |    1 +
 .../include/configs/vision2.h                      |    1 +
 5 files changed, 9 insertions(+), 1 deletion(-)

(quoted diff) +0 -0

u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index d0f75fa..b25b3a7 100644

arch/arm/cpu/armv7/mx5/lowlevel_init.S +1 -1

@@ -330,7 +330,7 @@ ENTRY(lowlevel_init)
 	mov r10, lr
 	mov r4, #0	/* Fix R4 to 0 */
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SYS_MAIN_PWR_ON)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]
 	orr r1, r1, #1 << 23

(quoted diff) +0 -0

u-boot-4d3c95f/doc/README.imx5
index 938d3da..85d476f 100644

doc/README.imx5 +3 -0

@@ -20,3 +20,8 @@ i.MX5x SoCs.
     mode), which causes the effect of this failure to be much lower
     (in terms
     of frequency deviation), avoiding system failure, or at least
     decreasing
     the likelihood of system failure.
+
+1.3 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
+    This option should be enabled for boards having a SYS_ON_OFF_CTL

signal
+ connected to GPIO1[23] and triggering the MAIN_PWR_ON signal
like in the

doc/README.imx5 +1 -0

+    reference designs.

(quoted diff) +0 -0

u-boot-4d3c95f/include/configs/efikamx.h
index 143b0f0..792b51b 100644

include/configs/efikamx.h +1 -0

@@ -270,5 +270,6 @@
 
 #define CONFIG_SYS_DDR_CLKSEL		0
 #define CONFIG_SYS_CLKTL_CBCDR		0x59E35145
+#define CONFIG_SYS_MAIN_PWR_ON
 
 #endif

(quoted diff) +0 -0

u-boot-4d3c95f/include/configs/mx51evk.h
index e975f54..6867f7b 100644

include/configs/mx51evk.h +1 -0

@@ -242,6 +242,7 @@
 
 #define CONFIG_SYS_DDR_CLKSEL	0
 #define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
+#define CONFIG_SYS_MAIN_PWR_ON
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization

(quoted diff) +0 -0

u-boot-4d3c95f/include/configs/vision2.h
index ed004a6..3ce4906 100644

include/configs/vision2.h +1 -0

@@ -203,6 +203,7 @@
 /* 166 MHz DDR RAM */
 #define CONFIG_SYS_DDR_CLKSEL		0
 #define CONFIG_SYS_CLKTL_CBCDR		0x19239100
+#define CONFIG_SYS_MAIN_PWR_ON
 
 #define CONFIG_SYS_NO_FLASH

Benoît Thébaudeau

author

2012-11-05 20:07 UTC #13 lore raw

PATCH v2 1/1 mx5: Mark lowlevel_init board-specific code

In reply to Benoît Thébaudeau

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Matt Sealey <[email protected]>

---
Note for mx51_efikamx and vision2 board maintainers: Check if CONFIG_SYS_MAIN_PWR_ON should be defined or not for your hardware (I don't have your schematics). Anyway, this patch does not change the behavior for these boards, but it allows to fix a possible existing issue for these boards if they differ from the mx51evk on this point.

This patch supersedes http://patchwork.ozlabs.org/patch/177296/ . Changes for v2:
- Rebase after other patch dropped in the original series (changes section number in doc/README.imx5).
- Rebase after efikamx renamed to mx51_efikamx.

 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S                        |    2 +-
 {u-boot-imx-bad05afe.orig => u-boot-imx-bad05afe}/doc/README.imx5 |    5 +++++
 .../include/configs/mx51_efikamx.h                                |    1 +
 .../include/configs/mx51evk.h                                     |    1 +
 .../include/configs/vision2.h                                     |    1 +
 5 files changed, 9 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/mx5/lowlevel_init.S +1 -1

index 29ec957..6d9396a 100644
@@ -396,7 +396,7 @@ ENTRY(lowlevel_init)
 	mov r10, lr
 	mov r4, #0	/* Fix R4 to 0 */
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SYS_MAIN_PWR_ON)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]
 	orr r1, r1, #1 << 23

doc/README.imx5 +5 -0

index f7eab7d..e08941e 100644
@@ -15,3 +15,8 @@ i.MX5x SoCs.
     mode), which causes the effect of this failure to be much lower (in terms
     of frequency deviation), avoiding system failure, or@least decreasing
     the likelihood of system failure.
+
+1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
+    This option should be enabled for boards having a SYS_ON_OFF_CTL signal
+    connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
+    reference designs.

include/configs/mx51_efikamx.h +1 -0

index ffe771f..a056566 100644
@@ -261,5 +261,6 @@
 
 #define CONFIG_SYS_DDR_CLKSEL		0
 #define CONFIG_SYS_CLKTL_CBCDR		0x59E35145
+#define CONFIG_SYS_MAIN_PWR_ON
 
 #endif

include/configs/mx51evk.h +1 -0

index 8cf59fe..122871f 100644
@@ -235,6 +235,7 @@
 
 #define CONFIG_SYS_DDR_CLKSEL	0
 #define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
+#define CONFIG_SYS_MAIN_PWR_ON
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization

include/configs/vision2.h +1 -0

index 848df88..13c5702 100644
@@ -196,6 +196,7 @@
 /* 166 MHz DDR RAM */
 #define CONFIG_SYS_DDR_CLKSEL		0
 #define CONFIG_SYS_CLKTL_CBCDR		0x19239100
+#define CONFIG_SYS_MAIN_PWR_ON
 
 #define CONFIG_SYS_NO_FLASH

Stefano Babic

2012-11-07 14:29 UTC #14 lore raw

PATCH v2 1/1 mx5: Mark lowlevel_init board-specific code

Quoted 4 lines · Beno?t Th?baudeau

The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design.

Right, and it is correct that this initialisation is not done for all boards.

Acked-by Stefano Babic <[email protected]>

Best regards,
Stefano Babic

Quoted 86 lines

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

Cc Matt Sealey <[email protected]>

 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S                        |    2 +-
 {u-boot-imx-bad05afe.orig => u-boot-imx-bad05afe}/doc/README.imx5 |    5 +++++
 .../include/configs/mx51_efikamx.h                                |    1 +
 .../include/configs/mx51evk.h                                     |    1 +
 .../include/configs/vision2.h                                     |    1 +
 5 files changed, 9 insertions(+), 1 deletion(-)

arch/arm/cpu/armv7/mx5/lowlevel_init.S +1 -1

index 29ec957..6d9396a 100644
@@ -396,7 +396,7 @@ ENTRY(lowlevel_init)
 	mov r10, lr
 	mov r4, #0	/* Fix R4 to 0 */
 
-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SYS_MAIN_PWR_ON)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]
 	orr r1, r1, #1 << 23

doc/README.imx5 +5 -0

index f7eab7d..e08941e 100644
@@ -15,3 +15,8 @@ i.MX5x SoCs.
     mode), which causes the effect of this failure to be much lower (in terms
     of frequency deviation), avoiding system failure, or at least decreasing
     the likelihood of system failure.
+
+1.2 CONFIG_SYS_MAIN_PWR_ON: Trigger MAIN_PWR_ON upon startup.
+    This option should be enabled for boards having a SYS_ON_OFF_CTL signal
+    connected to GPIO1[23] and triggering the MAIN_PWR_ON signal like in the
+    reference designs.

include/configs/mx51_efikamx.h +1 -0

index ffe771f..a056566 100644
@@ -261,5 +261,6 @@
 
 #define CONFIG_SYS_DDR_CLKSEL		0
 #define CONFIG_SYS_CLKTL_CBCDR		0x59E35145
+#define CONFIG_SYS_MAIN_PWR_ON
 
 #endif

include/configs/mx51evk.h +1 -0

index 8cf59fe..122871f 100644
@@ -235,6 +235,7 @@
 
 #define CONFIG_SYS_DDR_CLKSEL	0
 #define CONFIG_SYS_CLKTL_CBCDR	0x59E35100
+#define CONFIG_SYS_MAIN_PWR_ON
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization

include/configs/vision2.h +1 -0

index 848df88..13c5702 100644
@@ -196,6 +196,7 @@
 /* 166 MHz DDR RAM */
 #define CONFIG_SYS_DDR_CLKSEL		0
 #define CONFIG_SYS_CLKTL_CBCDR		0x19239100
+#define CONFIG_SYS_MAIN_PWR_ON
 
 #define CONFIG_SYS_NO_FLASH

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Benoît Thébaudeau

author

2012-11-16 22:42 UTC #15 lore raw

PATCH v2 1/1 mx5: Mark lowlevel_init board-specific code

Hi Stefano,

Quoted 10 lines · Stefano Babic

Quoted 8 lines · Beno?t Th?baudeau
The mx5 lowlevel_init.S contains board-specific code based on the reference
design. Let's keep it since it avoids creating new lowlevel_init files and it
may be used by many boards. But add a config to make it optional in order not to
cause issues on boards not following this part of the reference design.

Quoted 4 lines

Right, and it is correct that this initialisation is not done for all boards.
Acked-by Stefano Babic <[email protected]>

You seem to have forgotten this one in your last couple of application rounds.

Best regards,
Beno?t

Stefano Babic

2012-11-19 07:42 UTC #16 lore raw

PATCH v2 1/1 mx5: Mark lowlevel_init board-specific code

Quoted 13 lines · Beno?t Th?baudeau

Hi Stefano,
Quoted 10 lines · Stefano Babic
Quoted 8 lines · Beno?t Th?baudeau
The mx5 lowlevel_init.S contains board-specific code based on the reference
design. Let's keep it since it avoids creating new lowlevel_init files and it
may be used by many boards. But add a config to make it optional in order not to
cause issues on boards not following this part of the reference design.

Quoted 6 lines

Quoted 4 lines
Right, and it is correct that this initialisation is not done for all boards.
Acked-by Stefano Babic <[email protected]>
You seem to have forgotten this one in your last couple of application rounds.

That's right, I will push it - thanks.

Best regards,
Stefano

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2012-11-19 07:57 UTC #17 lore raw

PATCH v2 1/1 mx5: Mark lowlevel_init board-specific code

In reply to Benoît Thébaudeau

Quoted 9 lines · Beno?t Th?baudeau

The mx5 lowlevel_init.S contains board-specific code based on the reference design. Let's keep it since it avoids creating new lowlevel_init files and it may be used by many boards. But add a config to make it optional in order not to cause issues on boards not following this part of the reference design.
Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Stefano Babic <[email protected]>
Cc Matt Sealey <[email protected]>
---

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Otavio Salvador

2012-08-14 14:51 UTC #18 lore raw

PATCH 1/4 mx5: cosmetic: Clean up lowlevel_init

In reply to Benoît Thébaudeau

Quoted 2 lines · Beno?t Th?baudeau

Signed-off-by Beno?t Th?baudeau <[email protected]>
Cc Stefano Babic <[email protected]>

The patch seems to be just code style changes, but it is not clear from the commit description.

Signature · 3 lines

Otavio Salvador                             O.S. Systems
E-mail: otavio at ossystems.com.br  http://www.ossystems.com.br
Mobile: +55 53 9981-7854              http://projetos.ossystems.com.br

Benoît Thébaudeau

author

2012-08-14 15:18 UTC #19 lore raw

PATCH v2 1/4 mx5: cosmetic: Clean up lowlevel_init

Coding style cleanup:
- Remove useless parentheses.
- Use tabs for indentations and alignments.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2:
- Make patch description more detailed.

 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S         |   46 ++++++++++----------
 1 file changed, 23 insertions(+), 23 deletions(-)

arch/arm/cpu/armv7/mx5/lowlevel_init.S +23 ~~-23~~

index 683a7b5..a40b84f 100644
@@ -36,9 +36,9 @@
 	/* reconfigure L2 cache aux control reg */
 	mov r0, #0xC0			/* tag RAM */
 	add r0, r0, #0x4		/* data RAM */
-	orr r0, r0, #(1 << 24)		/* disable write allocate delay */
-	orr r0, r0, #(1 << 23)		/* disable write allocate combine */
-	orr r0, r0, #(1 << 22)		/* disable write allocate */
+	orr r0, r0, #1 << 24		/* disable write allocate delay */
+	orr r0, r0, #1 << 23		/* disable write allocate combine */
+	orr r0, r0, #1 << 22		/* disable write allocate */
 
 #if defined(CONFIG_MX51)
 	ldr r1, =0x0

@@ -46,7 +46,7 @@
 	cmp r3, #0x10
 
 	/* disable write combine for TO 2 and lower revs */
-	orrls r0, r0, #(1 << 25)
+	orrls r0, r0, #1 << 25
 #endif
 
 	mcr 15, 1, r0, c9, c0, 2

@@ -247,9 +247,9 @@
 	movhi r1, #0
 #else
 	mov r1, #0
-
 #endif
 	str r1, [r0, #CLKCTL_CACRR]
+
 	/* Switch ARM back to PLL 1 */
 	mov r1, #0
 	str r1, [r0, #CLKCTL_CCSR]

@@ -288,9 +288,9 @@
 	/* Switch peripheral to PLL2 */
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x00808145
-	orr r1, r1, #(2 << 10)
-	orr r1, r1, #(0 << 16)
-	orr r1, r1, #(1 << 19)
+	orr r1, r1, #2 << 10
+	orr r1, r1, #0 << 16
+	orr r1, r1, #1 << 19
 	str r1, [r0, #CLKCTL_CBCDR]
 
 	ldr r1, =0x00016154

@@ -331,10 +331,10 @@ ENTRY(lowlevel_init)
 #if defined(CONFIG_MX51)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]
-	orr r1, r1, #(1 << 23)
+	orr r1, r1, #1 << 23
 	str r1, [r0, #0x0]
 	ldr r1, [r0, #0x4]
-	orr r1, r1, #(1 << 23)
+	orr r1, r1, #1 << 23
 	str r1, [r0, #0x4]
 #endif

@@ -351,16 +351,16 @@ ENTRY(lowlevel_init)
 ENDPROC(lowlevel_init)
 
 /* Board level setting value */
-W_DP_OP_864:              .word DP_OP_864
-W_DP_MFD_864:             .word DP_MFD_864
-W_DP_MFN_864:             .word DP_MFN_864
-W_DP_MFN_800_DIT:         .word DP_MFN_800_DIT
-W_DP_OP_800:              .word DP_OP_800
-W_DP_MFD_800:             .word DP_MFD_800
-W_DP_MFN_800:             .word DP_MFN_800
-W_DP_OP_665:              .word DP_OP_665
-W_DP_MFD_665:             .word DP_MFD_665
-W_DP_MFN_665:             .word DP_MFN_665
-W_DP_OP_216:              .word DP_OP_216
-W_DP_MFD_216:             .word DP_MFD_216
-W_DP_MFN_216:             .word DP_MFN_216
+W_DP_OP_864:		.word DP_OP_864
+W_DP_MFD_864:		.word DP_MFD_864
+W_DP_MFN_864:		.word DP_MFN_864
+W_DP_MFN_800_DIT:	.word DP_MFN_800_DIT
+W_DP_OP_800:		.word DP_OP_800
+W_DP_MFD_800:		.word DP_MFD_800
+W_DP_MFN_800:		.word DP_MFN_800
+W_DP_OP_665:		.word DP_OP_665
+W_DP_MFD_665:		.word DP_MFD_665
+W_DP_MFN_665:		.word DP_MFN_665
+W_DP_OP_216:		.word DP_OP_216
+W_DP_MFD_216:		.word DP_MFD_216
+W_DP_MFN_216:		.word DP_MFN_216

Stefano Babic

2012-08-17 11:41 UTC #20 lore raw

PATCH v2 1/4 mx5: cosmetic: Clean up lowlevel_init

Quoted 97 lines · Beno?t Th?baudeau

Coding style cleanup:
- Remove useless parentheses.
- Use tabs for indentations and alignments.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2:
- Make patch description more detailed.

 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S         |   46 ++++++++++----------
 1 file changed, 23 insertions(+), 23 deletions(-)

arch/arm/cpu/armv7/mx5/lowlevel_init.S +13 ~~-23~~

index 683a7b5..a40b84f 100644
@@ -36,9 +36,9 @@
 	/* reconfigure L2 cache aux control reg */
 	mov r0, #0xC0			/* tag RAM */
 	add r0, r0, #0x4		/* data RAM */
-	orr r0, r0, #(1 << 24)		/* disable write allocate delay */
-	orr r0, r0, #(1 << 23)		/* disable write allocate combine */
-	orr r0, r0, #(1 << 22)		/* disable write allocate */
+	orr r0, r0, #1 << 24		/* disable write allocate delay */
+	orr r0, r0, #1 << 23		/* disable write allocate combine */
+	orr r0, r0, #1 << 22		/* disable write allocate */
 
 #if defined(CONFIG_MX51)
 	ldr r1, =0x0

@@ -46,7 +46,7 @@
 	cmp r3, #0x10
 
 	/* disable write combine for TO 2 and lower revs */
-	orrls r0, r0, #(1 << 25)
+	orrls r0, r0, #1 << 25
 #endif
 
 	mcr 15, 1, r0, c9, c0, 2

@@ -247,9 +247,9 @@
 	movhi r1, #0
 #else
 	mov r1, #0
-
 #endif
 	str r1, [r0, #CLKCTL_CACRR]
+
 	/* Switch ARM back to PLL 1 */
 	mov r1, #0
 	str r1, [r0, #CLKCTL_CCSR]

@@ -288,9 +288,9 @@
 	/* Switch peripheral to PLL2 */
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x00808145
-	orr r1, r1, #(2 << 10)
-	orr r1, r1, #(0 << 16)
-	orr r1, r1, #(1 << 19)
+	orr r1, r1, #2 << 10
+	orr r1, r1, #0 << 16
+	orr r1, r1, #1 << 19
 	str r1, [r0, #CLKCTL_CBCDR]
 
 	ldr r1, =0x00016154

@@ -331,10 +331,10 @@ ENTRY(lowlevel_init)
 #if defined(CONFIG_MX51)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]
-	orr r1, r1, #(1 << 23)
+	orr r1, r1, #1 << 23
 	str r1, [r0, #0x0]
 	ldr r1, [r0, #0x4]
-	orr r1, r1, #(1 << 23)
+	orr r1, r1, #1 << 23
 	str r1, [r0, #0x4]
 #endif

@@ -351,16 +351,16 @@ ENTRY(lowlevel_init)
 ENDPROC(lowlevel_init)
 
 /* Board level setting value */
-W_DP_OP_864:              .word DP_OP_864
-W_DP_MFD_864:             .word DP_MFD_864
-W_DP_MFN_864:             .word DP_MFN_864
-W_DP_MFN_800_DIT:         .word DP_MFN_800_DIT
-W_DP_OP_800:              .word DP_OP_800
-W_DP_MFD_800:             .word DP_MFD_800
-W_DP_MFN_800:             .word DP_MFN_800
-W_DP_OP_665:              .word DP_OP_665
-W_DP_MFD_665:             .word DP_MFD_665
-W_DP_MFN_665:             .word DP_MFN_665
-W_DP_OP_216:              .word DP_OP_216
-W_DP_MFD_216:             .word DP_MFD_216
-W_DP_MFN_216:             .word DP_MFN_216
+W_DP_OP_864:		.word DP_OP_864
+W_DP_MFD_864:		.word DP_MFD_864
+W_DP_MFN_864:		.word DP_MFN_864

arch/arm/cpu/armv7/mx5/lowlevel_init.S ENTRY(lowlevel_init) · line 366

Quoted 10 lines

arch/arm/cpu/armv7/mx5/lowlevel_init.S +10 -0

+W_DP_MFN_800_DIT:	.word DP_MFN_800_DIT
+W_DP_OP_800:		.word DP_OP_800
+W_DP_MFD_800:		.word DP_MFD_800
+W_DP_MFN_800:		.word DP_MFN_800
+W_DP_OP_665:		.word DP_OP_665
+W_DP_MFD_665:		.word DP_MFD_665
+W_DP_MFN_665:		.word DP_MFN_665
+W_DP_OP_216:		.word DP_OP_216
+W_DP_MFD_216:		.word DP_MFD_216
+W_DP_MFN_216:		.word DP_MFN_216

Acked-by Stefano Babic <[email protected]>

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

Stefano Babic

2012-08-20 07:56 UTC #21 lore raw

PATCH v2 1/4 mx5: cosmetic: Clean up lowlevel_init

In reply to Benoît Thébaudeau

Quoted 97 lines · Beno?t Th?baudeau

Coding style cleanup:
- Remove useless parentheses.
- Use tabs for indentations and alignments.

Signed-off-by Beno?t Th?baudeau <[email protected]>

Cc Stefano Babic <[email protected]>

---
Changes for v2:
- Make patch description more detailed.

 .../arch/arm/cpu/armv7/mx5/lowlevel_init.S         |   46 ++++++++++----------
 1 file changed, 23 insertions(+), 23 deletions(-)

arch/arm/cpu/armv7/mx5/lowlevel_init.S +13 ~~-23~~

index 683a7b5..a40b84f 100644
@@ -36,9 +36,9 @@
 	/* reconfigure L2 cache aux control reg */
 	mov r0, #0xC0			/* tag RAM */
 	add r0, r0, #0x4		/* data RAM */
-	orr r0, r0, #(1 << 24)		/* disable write allocate delay */
-	orr r0, r0, #(1 << 23)		/* disable write allocate combine */
-	orr r0, r0, #(1 << 22)		/* disable write allocate */
+	orr r0, r0, #1 << 24		/* disable write allocate delay */
+	orr r0, r0, #1 << 23		/* disable write allocate combine */
+	orr r0, r0, #1 << 22		/* disable write allocate */
 
 #if defined(CONFIG_MX51)
 	ldr r1, =0x0

@@ -46,7 +46,7 @@
 	cmp r3, #0x10
 
 	/* disable write combine for TO 2 and lower revs */
-	orrls r0, r0, #(1 << 25)
+	orrls r0, r0, #1 << 25
 #endif
 
 	mcr 15, 1, r0, c9, c0, 2

@@ -247,9 +247,9 @@
 	movhi r1, #0
 #else
 	mov r1, #0
-
 #endif
 	str r1, [r0, #CLKCTL_CACRR]
+
 	/* Switch ARM back to PLL 1 */
 	mov r1, #0
 	str r1, [r0, #CLKCTL_CCSR]

@@ -288,9 +288,9 @@
 	/* Switch peripheral to PLL2 */
 	ldr r0, =CCM_BASE_ADDR
 	ldr r1, =0x00808145
-	orr r1, r1, #(2 << 10)
-	orr r1, r1, #(0 << 16)
-	orr r1, r1, #(1 << 19)
+	orr r1, r1, #2 << 10
+	orr r1, r1, #0 << 16
+	orr r1, r1, #1 << 19
 	str r1, [r0, #CLKCTL_CBCDR]
 
 	ldr r1, =0x00016154

@@ -331,10 +331,10 @@ ENTRY(lowlevel_init)
 #if defined(CONFIG_MX51)
 	ldr r0, =GPIO1_BASE_ADDR
 	ldr r1, [r0, #0x0]
-	orr r1, r1, #(1 << 23)
+	orr r1, r1, #1 << 23
 	str r1, [r0, #0x0]
 	ldr r1, [r0, #0x4]
-	orr r1, r1, #(1 << 23)
+	orr r1, r1, #1 << 23
 	str r1, [r0, #0x4]
 #endif

@@ -351,16 +351,16 @@ ENTRY(lowlevel_init)
 ENDPROC(lowlevel_init)
 
 /* Board level setting value */
-W_DP_OP_864:              .word DP_OP_864
-W_DP_MFD_864:             .word DP_MFD_864
-W_DP_MFN_864:             .word DP_MFN_864
-W_DP_MFN_800_DIT:         .word DP_MFN_800_DIT
-W_DP_OP_800:              .word DP_OP_800
-W_DP_MFD_800:             .word DP_MFD_800
-W_DP_MFN_800:             .word DP_MFN_800
-W_DP_OP_665:              .word DP_OP_665
-W_DP_MFD_665:             .word DP_MFD_665
-W_DP_MFN_665:             .word DP_MFN_665
-W_DP_OP_216:              .word DP_OP_216
-W_DP_MFD_216:             .word DP_MFD_216
-W_DP_MFN_216:             .word DP_MFN_216
+W_DP_OP_864:		.word DP_OP_864
+W_DP_MFD_864:		.word DP_MFD_864
+W_DP_MFN_864:		.word DP_MFN_864

arch/arm/cpu/armv7/mx5/lowlevel_init.S ENTRY(lowlevel_init) · line 366

Quoted 10 lines

arch/arm/cpu/armv7/mx5/lowlevel_init.S +10 -0

+W_DP_MFN_800_DIT:	.word DP_MFN_800_DIT
+W_DP_OP_800:		.word DP_OP_800
+W_DP_MFD_800:		.word DP_MFD_800
+W_DP_MFN_800:		.word DP_MFN_800
+W_DP_OP_665:		.word DP_OP_665
+W_DP_MFD_665:		.word DP_MFD_665
+W_DP_MFN_665:		.word DP_MFN_665
+W_DP_OP_216:		.word DP_OP_216
+W_DP_MFD_216:		.word DP_MFD_216
+W_DP_MFN_216:		.word DP_MFN_216

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================