ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412

PATCH New Tomasz Figa 3 participants 3 messages Aug 29, 2012 – Oct 23, 2012

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Arm (32-bit) Arm sub-architectures Arm Samsung Exynos

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Tomasz Figa

author

2012-08-29 14:08 UTC #0 lore raw

PATCH v2 1/1 ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412

Exynos4412 uses different information register for each core. This patch adjusts the bring-up code to take that into account.

Signed-off-by Tomasz Figa <[email protected]>

Signed-off-by Kyungmin Park <[email protected]>

---
 arch/arm/mach-exynos/platsmp.c | 27 +++++++++++++++++++++------
 1 file changed, 21 insertions(+), 6 deletions(-)

arch/arm/mach-exynos/platsmp.c +21 -6

index 36c3984..816a27d 100644
@@ -34,8 +34,19 @@
 
 extern void exynos4_secondary_startup(void);
 
-#define CPU1_BOOT_REG		(samsung_rev() == EXYNOS4210_REV_1_1 ? \
-				S5P_INFORM5 : S5P_VA_SYSRAM)
+static inline void __iomem *cpu_boot_reg_base(void)
+{
+	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
+		return S5P_INFORM5;
+	return S5P_VA_SYSRAM;
+}
+
+static inline void __iomem *cpu_boot_reg(int cpu)
+{
+	if (soc_is_exynos4412())
+		return cpu_boot_reg_base() + 4*cpu;
+	return cpu_boot_reg_base();
+}
 
 /*
  * control for which core is the next to come out of the secondary

@@ -89,6 +100,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	unsigned long timeout;
+	unsigned long phys_cpu = cpu_logical_map(cpu);
 
 	/*
 	 * Set synchronisation state between this boot processor

@@ -104,7 +116,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 	 * Note that "pen_release" is the hardware CPU ID, whereas
 	 * "cpu" is Linux's internal ID.
 	 */
-	write_pen_release(cpu_logical_map(cpu));
+	write_pen_release(phys_cpu);
 
 	if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
 		__raw_writel(S5P_CORE_LOCAL_PWR_EN,

@@ -138,7 +150,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 		smp_rmb();
 
 		__raw_writel(virt_to_phys(exynos4_secondary_startup),
-			CPU1_BOOT_REG);
+							cpu_boot_reg(phys_cpu));
 		gic_raise_softirq(cpumask_of(cpu), 1);
 
 		if (pen_release == -1)

@@ -186,6 +198,8 @@ void __init smp_init_cpus(void)
 
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
+	int i;
+
 	if (!soc_is_exynos5250())
 		scu_enable(scu_base_addr());

@@ -195,6 +209,7 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 	 * until it receives a soft interrupt, and then the
 	 * secondary CPU branches to this address.
 	 */
-	__raw_writel(virt_to_phys(exynos4_secondary_startup),
-			CPU1_BOOT_REG);
+	for (i = 1; i < max_cpus; ++i)
+		__raw_writel(virt_to_phys(exynos4_secondary_startup),
+					cpu_boot_reg(cpu_logical_map(i)));
 }

Signature · 1 line

1.7.12

Kukjin Kim

2012-10-23 11:57 UTC #1 lore raw

PATCH v2 1/1 ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412

Quoted 16 lines · Tomasz Figa

Exynos4412 uses different information register for each core. This patch adjusts the bring-up code to take that into account.
Signed-off-by Tomasz Figa <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
---
 arch/arm/mach-exynos/platsmp.c | 27 +++++++++++++++++++++------
 1 file changed, 21 insertions(+), 6 deletions(-)
arch/arm/mach- renamed from arch/arm/mach-exynos/platsmp.c +0 -0
exynos/platsmp.c
index 36c3984..816a27d 100644

arch/arm/mach-exynos/platsmp.c line 37

Quoted 4 lines

arch/arm/mach-exynos/platsmp.c +0 -1

@@ -34,8 +34,19 @@
 
 extern void exynos4_secondary_startup(void);
 
-#define CPU1_BOOT_REG		(samsung_rev() == EXYNOS4210_REV_1_1

? \

arch/arm/mach-exynos/platsmp.c void __cpuinit platform_secondary_init(unsigned int

Quoted 18 lines

arch/arm/mach-exynos/platsmp.c +13 -1

-				S5P_INFORM5 : S5P_VA_SYSRAM)
+static inline void __iomem *cpu_boot_reg_base(void)
+{
+	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
+		return S5P_INFORM5;
+	return S5P_VA_SYSRAM;
+}
+
+static inline void __iomem *cpu_boot_reg(int cpu)
+{
+	if (soc_is_exynos4412())
+		return cpu_boot_reg_base() + 4*cpu;
+	return cpu_boot_reg_base();
+}
 
 /*
  * control for which core is the next to come out of the secondary

@@ -89,6 +100,7 @@ void __cpuinit platform_secondary_init(unsigned int

cpu)

Quoted 18 lines

arch/arm/mach-exynos/platsmp.c +2 -1

 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
 	unsigned long timeout;
+	unsigned long phys_cpu = cpu_logical_map(cpu);
 
 	/*
 	 * Set synchronisation state between this boot processor

@@ -104,7 +116,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct
 task_struct *idle)
 	 * Note that "pen_release" is the hardware CPU ID, whereas
 	 * "cpu" is Linux's internal ID.
 	 */
-	write_pen_release(cpu_logical_map(cpu));
+	write_pen_release(phys_cpu);
 
 	if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {

arch/arm/mach-exynos/platsmp.c +0 -0

 		__raw_writel(S5P_CORE_LOCAL_PWR_EN,

arch/arm/mach-exynos/platsmp.c int __cpuinit boot_secondary(unsigned int cpu, struct · line 154

Quoted 6 lines

arch/arm/mach-exynos/platsmp.c +1 -1

@@ -138,7 +150,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct
 task_struct *idle)
 		smp_rmb();
 
 		__raw_writel(virt_to_phys(exynos4_secondary_startup),
-			CPU1_BOOT_REG);
+

cpu_boot_reg(phys_cpu));

Quoted 22 lines

arch/arm/mach-exynos/platsmp.c +0 -0

 		gic_raise_softirq(cpumask_of(cpu), 1);

arch/arm/mach-exynos/platsmp.c +5 -2

 		if (pen_release == -1)

@@ -186,6 +198,8 @@ void __init smp_init_cpus(void)
 
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
+	int i;
+
 	if (!soc_is_exynos5250())
 		scu_enable(scu_base_addr());

@@ -195,6 +209,7 @@ void __init platform_smp_prepare_cpus(unsigned int
 max_cpus)
 	 * until it receives a soft interrupt, and then the
 	 * secondary CPU branches to this address.
 	 */
-	__raw_writel(virt_to_phys(exynos4_secondary_startup),
-			CPU1_BOOT_REG);
+	for (i = 1; i < max_cpus; ++i)
+		__raw_writel(virt_to_phys(exynos4_secondary_startup),
+					cpu_boot_reg(cpu_logical_map(i)));

Quoted 3 lines

}
--
1.7.12

Looks ok to me, applied.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Tomasz Figa

2012-10-23 18:21 UTC #2 lore raw

PATCH v2 1/1 ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412

Hi Kgene,

Quoted 113 lines · On Tuesday 23 of October 2012 20:57:33 Kukjin Kim wrote:

Quoted 16 lines · Tomasz Figa

Exynos4412 uses different information register for each core. This patch adjusts the bring-up code to take that into account.
Signed-off-by Tomasz Figa <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
---
 arch/arm/mach-exynos/platsmp.c | 27 +++++++++++++++++++++------
 1 file changed, 21 insertions(+), 6 deletions(-)
arch/arm/mach- renamed from arch/arm/mach-exynos/platsmp.c +0 -0
exynos/platsmp.c
index 36c3984..816a27d 100644

arch/arm/mach-exynos/platsmp.c line 37

Quoted 4 lines

arch/arm/mach-exynos/platsmp.c +0 -1

@@ -34,8 +34,19 @@
 
 extern void exynos4_secondary_startup(void);
 
-#define CPU1_BOOT_REG		(samsung_rev() == EXYNOS4210_REV_1_1

? \

arch/arm/mach-exynos/platsmp.c void __cpuinit platform_secondary_init(unsigned int

Quoted 20 lines

arch/arm/mach-exynos/platsmp.c +13 -1

-				S5P_INFORM5 : S5P_VA_SYSRAM)
+static inline void __iomem *cpu_boot_reg_base(void)
+{
+	if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
+		return S5P_INFORM5;
+	return S5P_VA_SYSRAM;
+}
+
+static inline void __iomem *cpu_boot_reg(int cpu)
+{
+	if (soc_is_exynos4412())
+		return cpu_boot_reg_base() + 4*cpu;
+	return cpu_boot_reg_base();
+}
 
 /*

* control for which core is the next to come out of the secondary

arch/arm/mach-exynos/platsmp.c +0 -0

@@ -89,6 +100,7 @@ void __cpuinit platform_secondary_init(unsigned int

cpu)

Quoted 26 lines

arch/arm/mach-exynos/platsmp.c +1 -0

 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct
 *idle) {
 
 	unsigned long timeout;
 
+	unsigned long phys_cpu = cpu_logical_map(cpu);

arch/arm/mach-exynos/platsmp.c +1 -1

 	/*
 
 	 * Set synchronisation state between this boot processor

@@ -104,7 +116,7 @@ int __cpuinit boot_secondary(unsigned int cpu,
 struct task_struct *idle)
 
 	 * Note that "pen_release" is the hardware CPU ID, whereas
 	 * "cpu" is Linux's internal ID.
 	 */
 
-	write_pen_release(cpu_logical_map(cpu));
+	write_pen_release(phys_cpu);

arch/arm/mach-exynos/platsmp.c +0 -0

 	if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
 
 		__raw_writel(S5P_CORE_LOCAL_PWR_EN,

arch/arm/mach-exynos/platsmp.c int __cpuinit boot_secondary(unsigned int cpu, · line 156

Quoted 8 lines

arch/arm/mach-exynos/platsmp.c +1 -1

@@ -138,7 +150,7 @@ int __cpuinit boot_secondary(unsigned int cpu,
 struct task_struct *idle)
 
 		smp_rmb();
 
 		__raw_writel(virt_to_phys(exynos4_secondary_startup),
 
-			CPU1_BOOT_REG);
+

cpu_boot_reg(phys_cpu));

Quoted 29 lines

arch/arm/mach-exynos/platsmp.c +2 -0

 		gic_raise_softirq(cpumask_of(cpu), 1);
 
 		if (pen_release == -1)

@@ -186,6 +198,8 @@ void __init smp_init_cpus(void)
 
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
 
+	int i;
+
 
 	if (!soc_is_exynos5250())

arch/arm/mach-exynos/platsmp.c +3 -2

 		scu_enable(scu_base_addr());

@@ -195,6 +209,7 @@ void __init platform_smp_prepare_cpus(unsigned int
 max_cpus)
 
 	 * until it receives a soft interrupt, and then the
 	 * secondary CPU branches to this address.
 	 */
 
-	__raw_writel(virt_to_phys(exynos4_secondary_startup),
-			CPU1_BOOT_REG);
+	for (i = 1; i < max_cpus; ++i)
+		__raw_writel(virt_to_phys(exynos4_secondary_startup),
+					cpu_boot_reg(cpu_logical_map(i)));

Quoted 8 lines

Quoted 4 lines
}
--
1.7.12
Looks ok to me, applied.
Thanks.

This is an old version of the patch. A new one was posted as a part of the series adding support for firmware ops, with corrections for received comments.

Best regards,
Tomasz Figa