two more dts changes for Rockchip Cortex-A9 SoCs

Hi Arnd, Olof,

as it late in the cycle, this may not be appropriate anymore, but if it is still applicable, please pull

The following changes since commit 08567053f5cc4255ab53b75277b6102a3202bd75:

ARM: dts: rk3188-radxarock: add GPIO IR receiver node (2014-07-27 00:25:59 +0200)

are available in the git repository at:

git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/v3.17-rockchip-rk3xxx-dts-2

for you to fetch changes up to eb2b9d47dd907eba5d766d942723811393454346:

ARM: dts: rockchip: add watchdog node (2014-07-30 12:14:44 +0200)

----------------------------------------------------------------
Watchdog nodes and a duplicate pinctrl property.

----------------------------------------------------------------
Heiko Stuebner (2):
ARM: dts: rockchip: remove pinctrl setting from radxarock uart2
ARM: dts: rockchip: add watchdog node

 arch/arm/boot/dts/rk3066a-bqcurie2.dts | 4 ++++
 arch/arm/boot/dts/rk3066a.dtsi         | 4 ++++
 arch/arm/boot/dts/rk3188-radxarock.dts | 6 ++++--
 arch/arm/boot/dts/rk3188.dtsi          | 4 ++++
 arch/arm/boot/dts/rk3xxx.dtsi          | 8 ++++++++
 5 files changed, 24 insertions(+), 2 deletions(-)

We set default pinctrl settings for the uarts in rk3188.dtsi already, so remove forgotten duplicate.

---
 arch/arm/boot/dts/rk3188-radxarock.dts | 2 --
 1 file changed, 2 deletions(-)

index b7f3423..4195f5a 100644
@@ -215,8 +215,6 @@
 };
 
 &uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart2_xfer>;
 	status = "okay";
 };
 

2.0.1

This adds the Designware compatible watchdog found on RK3xxx Cortex-A9 SoCs.

---
 arch/arm/boot/dts/rk3066a-bqcurie2.dts | 4 ++++
 arch/arm/boot/dts/rk3066a.dtsi         | 4 ++++
 arch/arm/boot/dts/rk3188-radxarock.dts | 4 ++++
 arch/arm/boot/dts/rk3188.dtsi          | 4 ++++
 arch/arm/boot/dts/rk3xxx.dtsi          | 8 ++++++++
 5 files changed, 24 insertions(+)

index 8b479f7..042f821d 100644
@@ -188,3 +188,7 @@
 &uart3 {
 	status = "okay";
 };
+
+&wdt {
+	status = "okay";
+};

index 9c34da4..879a818 100644
@@ -425,3 +425,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart3_xfer>;
 };
+
+&wdt {
+	compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
+};

index 4195f5a..171b610 100644
@@ -221,3 +221,7 @@
 &uart3 {
 	status = "okay";
 };
+
+&wdt {
+	status = "okay";
+};

index 27215e0..ee801a9 100644
@@ -400,3 +400,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart3_xfer>;
 };
+
+&wdt {
+	compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
+};

index c6f0561..8caf85d 100644
@@ -174,6 +174,14 @@
 		status = "disabled";
 	};
 
+	wdt: watchdog at 2004c000 {
+		compatible = "snps,dw-wdt";
+		reg = <0x2004c000 0x100>;
+		clocks = <&cru PCLK_WDT>;
+		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+		status = "disabled";
+	};
+
 	pwm2: pwm at 20050020 {
 		compatible = "rockchip,rk2928-pwm";
 		reg = <0x20050020 0x10>;

2.0.1

Grmbl, I set myself up for this one didn't I? :)

Merged. That's it though. I'm going to be a lot more picky from here on, merge window is almost upon us.

-Olof

Am Mittwoch, 30. Juli 2014, 22:42:03 schrieb Olof Johansson:

08567053f5cc4255ab53b75277b6102a3202bd75:

don't worry, I haven't anything more at this point. As you know, everything else would depend on driver changes that won't make it into 3.17 ... so you're safe ;-) .