Skip to contentSkip to conversation

Renesas R8A7743 CPG/MSSR clock support

PATCH Superseded Sergei Shtylyov 2 participants 5 messages Oct 21, 2016 – Oct 26, 2016

Subsystems (3)

v3 of 6 Superseded Latest is v6 →

lore
Share & tools
lore
#0 lore raw

v3 cover Renesas R8A7743 CPG/MSSR clock support

Hello.

Here's the set of 2 patches against the 'clk-next' branch of CLK group's
'linux.git' repo. I've splitted them from the R-Car gen2 common support patch. As the DT patches in the R8A7743/SK-RZG1M board support series depend on the patch #1 of this series, it might make sense to merge this patch to the 'renesas.git' repo as well...

[1/2] ARM: shmobile: r8a7743: add CPG clock index macros [2/2] clk: renesas: cpg-mssr: add R8A7743 support

MBR, Sergei

#1 lore raw

PATCH v3 1/2 ARM: shmobile: r8a7743: add CPG clock index macros

Add macros usable by the device tree sources to reference the R8A7743 CPG clocks by index. The data comes from the table 7.2b in the revision 0.50 of the RZ/G Series User's Manual.

---
Changes in version 3:
- renumbered the #define's in order to match the R8A7791 CPG clocks;
- added the reference to the manaual to the patch description.

Changes in version 2:
- reduced the macro value indentation.

 include/dt-bindings/clock/r8a7743-cpg-mssr.h |   43 +++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
include/dt-bindings/clock/r8a7743-cpg-mssr.h new file +43 -0
Index: linux/include/dt-bindings/clock/r8a7743-cpg-mssr.h
===================================================================
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
+#define __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__
+
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+
+/* r8a7743 CPG Core Clocks */
+#define R8A7743_CLK_Z		0
+#define R8A7743_CLK_ZG		1
+#define R8A7743_CLK_ZTR		2
+#define R8A7743_CLK_ZTRD2	3
+#define R8A7743_CLK_ZT		4
+#define R8A7743_CLK_ZX		5
+#define R8A7743_CLK_ZS		6
+#define R8A7743_CLK_HP		7
+#define R8A7743_CLK_B		9
+#define R8A7743_CLK_LB		10
+#define R8A7743_CLK_P		11
+#define R8A7743_CLK_CL		12
+#define R8A7743_CLK_M2		13
+#define R8A7743_CLK_ZB3		15
+#define R8A7743_CLK_ZB3D2	16
+#define R8A7743_CLK_DDR		17
+#define R8A7743_CLK_SDH		18
+#define R8A7743_CLK_SD0		19
+#define R8A7743_CLK_SD2		20
+#define R8A7743_CLK_SD3		21
+#define R8A7743_CLK_MMC0	22
+#define R8A7743_CLK_MP		23
+#define R8A7743_CLK_QSPI	26
+#define R8A7743_CLK_CP		27
+#define R8A7743_CLK_RCAN	28
+#define R8A7743_CLK_R		29
+#define R8A7743_CLK_OSC		30
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7743_CPG_MSSR_H__ */
Reviewed-by on v3 1/2
#2 lore raw

Re: [PATCH v3 1/2] ARM: shmobile: r8a7743: add CPG clock index macros

Quoted 5 lines · Sergei Shtylyov

Add macros usable by the device tree sources to reference the R8A7743 CPG clocks by index. The data comes from the table 7.2b in the revision 0.50 of the RZ/G Series User's Manual.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

#3 lore raw

PATCH v3 2/2 clk: renesas: cpg-mssr: add R8A7743 support

In reply to Sergei Shtylyov

Add RZ/G1M (R8A7743) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen2 (and RZ/G) code.

Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven <[email protected]>.

---
Changes in version 3:
- exchanged Audio-DMAC0/1 entries in r8a7743_mod_clks[];
- renamed the I2C6 entry to IICDVFS;
- fixed the comment to the INTC-SYS entry in r8a7743_crit_mod_clks[];
- removed the useless EXTAL divisor check from r8a7743_cpg_mssr_init();
- added Rob's ACK and Geert's tag.

Changes in version 2:
- documented the R8A7743 device tree binding;
- fixed whitespace errors/warnings reported by checkpatch.pl;
- used tabs instead of spaces for indentation;
- fixed the PLL3 column name in the PLL table.

 Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt |    4 
 drivers/clk/renesas/Kconfig                                  |    1 
 drivers/clk/renesas/Makefile                                 |    1 
 drivers/clk/renesas/r8a7743-cpg-mssr.c                       |  264 +++++++++++
 drivers/clk/renesas/renesas-cpg-mssr.c                       |    6 
 drivers/clk/renesas/renesas-cpg-mssr.h                       |    1 
 6 files changed, 276 insertions(+), 1 deletion(-)
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt +3 -1
Index: linux/Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt
===================================================================
@@ -13,6 +13,7 @@ They provide the following functionaliti
 
 Required Properties:
   - compatible: Must be one of:
+      - "renesas,r8a7743-cpg-mssr" for the r8a7743 SoC (RZ/G1M)
       - "renesas,r8a7795-cpg-mssr" for the r8a7795 SoC (R-Car H3)
       - "renesas,r8a7796-cpg-mssr" for the r8a7796 SoC (R-Car M3-W)
 
@@ -22,7 +23,8 @@ Required Properties:
   - clocks: References to external parent clocks, one entry for each entry in
     clock-names
   - clock-names: List of external parent clock names. Valid names are:
-      - "extal" (r8a7795, r8a7796)
+      - "extal" (r8a7743, r8a7795, r8a7796)
+      - "usb_extal" (r8a7743)
       - "extalr" (r8a7795, r8a7796)
 
   - #clock-cells: Must be 2
drivers/clk/renesas/Kconfig +1 -0
Index: linux/drivers/clk/renesas/Kconfig
===================================================================
@@ -1,5 +1,6 @@
 config CLK_RENESAS_CPG_MSSR
 	bool
+	default y if ARCH_R8A7743
 	default y if ARCH_R8A7795
 	default y if ARCH_R8A7796
 
drivers/clk/renesas/Makefile +1 -0
Index: linux/drivers/clk/renesas/Makefile
===================================================================
@@ -2,6 +2,7 @@ obj-$(CONFIG_ARCH_EMEV2)		+= clk-emev2.o
 obj-$(CONFIG_ARCH_R7S72100)		+= clk-rz.o
 obj-$(CONFIG_ARCH_R8A73A4)		+= clk-r8a73a4.o clk-div6.o
 obj-$(CONFIG_ARCH_R8A7740)		+= clk-r8a7740.o clk-div6.o
+obj-$(CONFIG_ARCH_R8A7743)		+= r8a7743-cpg-mssr.o rcar-gen2-cpg.o
 obj-$(CONFIG_ARCH_R8A7778)		+= clk-r8a7778.o
 obj-$(CONFIG_ARCH_R8A7779)		+= clk-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790)		+= clk-rcar-gen2.o clk-div6.o
drivers/clk/renesas/r8a7743-cpg-mssr.c new file +264 -0

264 lines not on this page · raw message

drivers/clk/renesas/renesas-cpg-mssr.c +6 -0
Index: linux/drivers/clk/renesas/renesas-cpg-mssr.c
===================================================================
@@ -503,6 +503,12 @@ static int __init cpg_mssr_add_clk_domai
 }
 
 static const struct of_device_id cpg_mssr_match[] = {
+#ifdef CONFIG_ARCH_R8A7743
+	{
+		.compatible = "renesas,r8a7743-cpg-mssr",
+		.data = &r8a7743_cpg_mssr_info,
+	},
+#endif
 #ifdef CONFIG_ARCH_R8A7795
 	{
 		.compatible = "renesas,r8a7795-cpg-mssr",
drivers/clk/renesas/renesas-cpg-mssr.h +1 -0
Index: linux/drivers/clk/renesas/renesas-cpg-mssr.h
===================================================================
@@ -130,6 +130,7 @@ struct cpg_mssr_info {
 					struct clk **clks, void __iomem *base);
 };
 
+extern const struct cpg_mssr_info r8a7743_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7795_cpg_mssr_info;
 extern const struct cpg_mssr_info r8a7796_cpg_mssr_info;
 #endif
#4 lore raw

Re: [PATCH v3 2/2] clk: renesas: cpg-mssr: add R8A7743 support

drivers/clk/renesas/r8a7743-cpg-mssr.c line 238

Quoted 8 lines · Sergei Shtylyov
drivers/clk/renesas/r8a7743-cpg-mssr.c new file +4 -0
@@ -0,0 +1,264 @@
 
+static int __init r8a7743_cpg_mssr_init(struct device *dev)
+{
+       const struct rcar_gen2_cpg_pll_config *cpg_pll_config;
+       u32 cpg_mode = rcar_gen2_read_modemr();

It would be good if we could appply "[PATCH v4 00/23] soc: renesas: Add R-Car RST driver for obtaining mode pin state" first, and change this driveer to use rcar_rst_read_mode_pins() instead.

drivers/clk/renesas/r8a7743-cpg-mssr.c line 243

Quoted 4 lines
drivers/clk/renesas/r8a7743-cpg-mssr.c new file +4 -0
+       cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
+
+       return rcar_gen2_cpg_init(cpg_pll_config);
+}

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds