imx: mx6q DDR3 init: Fix tMRD

PATCH New Benoît Thébaudeau 3 participants 11 messages Jan 30, 2013 – Feb 12, 2013 Arm i.MX and Layerscape

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Benoît Thébaudeau

author

2013-01-30 21:19 UTC #0 lore raw

PATCH 1/6 imx: mx6q DDR3 init: Fix tMRD

MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.

For all DDR3 speed bins:
tMRD(min) = 4 nCK
tMOD(min) = max(12 nCK, 15 ns)

Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].

Signed-off-by Beno?t Th?baudeau <[email protected]>

---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +1 -1

index c86cd40..9ac8027 100644
@@ -110,7 +110,7 @@ DATA 4 0x021b0018 0x00081740
 
 DATA 4 0x021b001c 0x00008000
 DATA 4 0x021b000c 0x555A7975
-DATA 4 0x021b0010 0xFF538E64
+DATA 4 0x021b0010 0xFF538F64
 DATA 4 0x021b0014 0x01FF00DB
 DATA 4 0x021b002c 0x000026D2

Signature · 1 line

1.7.10.4

Benoît Thébaudeau

author

2013-01-30 21:19 UTC #1 lore raw

PATCH 2/6 imx: mx6q DDR3 init: Fix tXPR

MMDC1_MDOR.tXPR should be set as specified for the JEDEC DDR3 timing tXPR.

For all DDR3 speed bins:
tXPR(min) = max(5 nCK, tRFC(min) + 10 ns)
tRFC(2 Gb) = 160 ns

All the users of mx6q_4x_mt41j128.cfg have a 2-Gb density (Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and Micron MT41K128M16JT-125:K for i.MX6 SABRE SD).

Hence, MMDC1_MDOR.tXPR should be set to max(5 nCK, 170 ns), which is 170 ns and 91 nCK at 532 MHz, encoded as 0x5A in the bit-field MMDC1_MDOR[23:16].

Signed-off-by Beno?t Th?baudeau <[email protected]>

---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +1 -1

index 9ac8027..1c24da8 100644
@@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64
 DATA 4 0x021b0014 0x01FF00DB
 DATA 4 0x021b002c 0x000026D2
 
-DATA 4 0x021b0030 0x005B0E21
+DATA 4 0x021b0030 0x005A0E21
 DATA 4 0x021b0008 0x09444040
 DATA 4 0x021b0004 0x00025576
 DATA 4 0x021b0040 0x00000027

Signature · 1 line

1.7.10.4

Benoît Thébaudeau

author

2013-01-30 21:19 UTC #2 lore raw

PATCH 3/6 imx: mx6q DDR3 init: Fix SDE_to_RST

In reply to Benoît Thébaudeau

MMDC1_MDOR.SDE_to_RST should be set to 200 ?s according to the JEDEC specification for DDR3. With a cycle of 15.258 ?s, this gives 14 cycles encoded as 0x10 for the bit-field MMDC1_MDOR[13:8].

Signed-off-by Beno?t Th?baudeau <[email protected]>

---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +1 -1

index 1c24da8..73317b5 100644
@@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64
 DATA 4 0x021b0014 0x01FF00DB
 DATA 4 0x021b002c 0x000026D2
 
-DATA 4 0x021b0030 0x005A0E21
+DATA 4 0x021b0030 0x005A1021
 DATA 4 0x021b0008 0x09444040
 DATA 4 0x021b0004 0x00025576
 DATA 4 0x021b0040 0x00000027

Signature · 1 line

1.7.10.4

Benoît Thébaudeau

author

2013-01-30 21:19 UTC #3 lore raw

PATCH 4/6 imx: mx6q DDR3 init: Fix RST_to_CKE

In reply to Benoît Thébaudeau

MMDC1_MDOR.RST_to_CKE should be set to 500 ?s according to the JEDEC specification for DDR3. With a cycle of 15.258 ?s, this gives 33 cycles encoded as 0x23 for the bit-field MMDC1_MDOR[5:0].

Signed-off-by Beno?t Th?baudeau <[email protected]>

---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +1 -1

index 73317b5..51f8c35 100644
@@ -114,7 +114,7 @@ DATA 4 0x021b0010 0xFF538F64
 DATA 4 0x021b0014 0x01FF00DB
 DATA 4 0x021b002c 0x000026D2
 
-DATA 4 0x021b0030 0x005A1021
+DATA 4 0x021b0030 0x005A1023
 DATA 4 0x021b0008 0x09444040
 DATA 4 0x021b0004 0x00025576
 DATA 4 0x021b0040 0x00000027

Signature · 1 line

1.7.10.4

Benoît Thébaudeau

author

2013-01-30 21:19 UTC #4 lore raw

PATCH 5/6 imx: mx6q DDR3 init: Fix MR0.PPD

In reply to Benoît Thébaudeau

MR0.PPD should be set as in MMDCx_MDPDC.SLOW_PD, i.e. to fast-exit mode, which is encoded as 1 in MRS.LMR.MR0.A12 and MMDCx_MDSCR[28].

Signed-off-by Beno?t Th?baudeau <[email protected]>

---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +2 -2

index 51f8c35..d50858d 100644
@@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x00008033
 DATA 4 0x021b001c 0x0000803B
 DATA 4 0x021b001c 0x00428031
 DATA 4 0x021b001c 0x00428039
-DATA 4 0x021b001c 0x09408030
-DATA 4 0x021b001c 0x09408038
+DATA 4 0x021b001c 0x19408030
+DATA 4 0x021b001c 0x19408038
 
 DATA 4 0x021b001c 0x04008040
 DATA 4 0x021b001c 0x04008048

Signature · 1 line

1.7.10.4

Benoît Thébaudeau

author

2013-01-30 21:19 UTC #5 lore raw

PATCH 6/6 imx: mx6q DDR3 init: Benefit from available CL = 7

In reply to Benoît Thébaudeau

All the users of mx6q_4x_mt41j128.cfg (DDR3-1333H Micron MT41J128M16HA-15E or SK hynix H5TQ2G63BFR-H9C for i.MX6Q SABRE Lite, and DDR3-1600K Micron MT41K128M16JT-125:K for i.MX6 SABRE SD) support the optional down binning to DDR3-1066F (CL = 7, CWL = 6), which is possible at 532 MHz, so use it.

In these conditions:
tRCD(min) = 13.125 ns
tRP(min) = 13.125 ns
tRC(min) = max(tRAS(min, DDR3-1333H), tRAS(min, DDR3-1600K)) + tRP(min) tRAS(min, DDR3-1333H) = 36 ns
tRAS(min, DDR3-1600K) = 35 ns

MMDC1_MDCFG0.tCL should be set to 7 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG0[3:0].

MR0.CL should be set as in MMDC1_MDCFG0.tCL, i.e. to 7 nCK, which is encoded as 0x6 in MRS.LMR.MR0.{A6:A4, A2} and MMDC1_MDSCR[22:20, 18].

MMDC1_MDCFG1.tCWL should be set to 6 nCK, encoded as 0x4 in the bit-field MMDC1_MDCFG1[2:0].

MMDC1_MDCFG1.tRCD should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[31:29].

MMDC1_MDCFG1.tRP should be set to 13.125 ns, which is 7 nCK at 532 MHz, encoded as 0x6 in the bit-field MMDC1_MDCFG1[28:26].

MMDC1_MDCFG1.tRC should be set to 49.125 ns, which is 27 nCK at 532 MHz, encoded as 0x1A in the bit-field MMDC1_MDCFG1[25:21].

Signed-off-by Beno?t Th?baudeau <[email protected]>

---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +4 -4

index d50858d..f4cae5e 100644
@@ -109,8 +109,8 @@ DATA 4 0x021b4828 0x33333333
 DATA 4 0x021b0018 0x00081740
 
 DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b000c 0x555A7975
-DATA 4 0x021b0010 0xFF538F64
+DATA 4 0x021b000c 0x555A7974
+DATA 4 0x021b0010 0xDB538F64
 DATA 4 0x021b0014 0x01FF00DB
 DATA 4 0x021b002c 0x000026D2

@@ -126,8 +126,8 @@ DATA 4 0x021b001c 0x00008033
 DATA 4 0x021b001c 0x0000803B
 DATA 4 0x021b001c 0x00428031
 DATA 4 0x021b001c 0x00428039
-DATA 4 0x021b001c 0x19408030
-DATA 4 0x021b001c 0x19408038
+DATA 4 0x021b001c 0x19308030
+DATA 4 0x021b001c 0x19308038
 
 DATA 4 0x021b001c 0x04008040
 DATA 4 0x021b001c 0x04008048

Signature · 1 line

1.7.10.4

Eric Nelson

2013-01-31 23:14 UTC #6 lore raw

PATCH 1/6 imx: mx6q DDR3 init: Fix tMRD

In reply to Benoît Thébaudeau

Quoted 20 lines · Beno?t Th?baudeau

MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.
For all DDR3 speed bins:
tMRD(min) = 4 nCK
tMOD(min) = max(12 nCK, 15 ns)
Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].
Signed-off-by Beno?t Th?baudeau <[email protected]>
---
  board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +0 -0
index c86cd40..9ac8027 100644

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg DATA 4 0x021b0018 0x00081740 · line 116

Quoted 8 lines

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +1 -1

@@ -110,7 +110,7 @@ DATA 4 0x021b0018 0x00081740
 
  DATA 4 0x021b001c 0x00008000
  DATA 4 0x021b000c 0x555A7975
-DATA 4 0x021b0010 0xFF538E64
+DATA 4 0x021b0010 0xFF538F64
  DATA 4 0x021b0014 0x01FF00DB
  DATA 4 0x021b002c 0x000026D2

Hi Beno?t,

I've been able to confirm operation of this complete patch set on a SABRE Lite here, but only that (boots normally).

I'll try to scare up a board we can place on an extended burn-in.

What prompted you to walk the list? Was there a specific failure that this addressed?

Please advise,

Eric

Benoît Thébaudeau

author

2013-01-31 23:25 UTC #7 lore raw

PATCH 1/6 imx: mx6q DDR3 init: Fix tMRD

Hi Eric,

Quoted 34 lines · Eric Nelson

Quoted 22 lines · Beno?t Th?baudeau
MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.
For all DDR3 speed bins:
tMRD(min) = 4 nCK
tMOD(min) = max(12 nCK, 15 ns)
Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK
at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].
Signed-off-by Beno?t Th?baudeau <[email protected]>
---
  board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +0 -0
index c86cd40..9ac8027 100644
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg DATA 4 0x021b0018 0x00081740 · line 116
Quoted 8 lines
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +1 -1
@@ -110,7 +110,7 @@ DATA 4 0x021b0018 0x00081740
 
  DATA 4 0x021b001c 0x00008000
  DATA 4 0x021b000c 0x555A7975
-DATA 4 0x021b0010 0xFF538E64
+DATA 4 0x021b0010 0xFF538F64
  DATA 4 0x021b0014 0x01FF00DB
  DATA 4 0x021b002c 0x000026D2
 
Hi Beno?t,

Quoted 2 lines

I've been able to confirm operation of this complete patch set on a SABRE Lite here, but only that (boots normally).

Great.

Quoted 1 line

I'll try to scare up a board we can place on an extended burn-in.

That'd be good.

Quoted 2 lines

What prompted you to walk the list? Was there a specific failure that this addressed?

No specific failure. The only issue that I get from time to time is errors in the Linux SD driver, but this is probably unrelated.

The only reason was that I was looking for possible better performance on the RAM side because I am working on very intensive RAM accessing applications. So I checked the init code to see if it was optimal, and I found these issues besides the small possible performance gain.

So far, the default mtest passed on my board. The alternate mtest and more Linux stress tests might be interesting too.

Best regards,
Beno?t

Eric Nelson

2013-02-01 18:28 UTC #8 lore raw

PATCH 1/6 imx: mx6q DDR3 init: Fix tMRD

Hi Beno?t,

Quoted 16 lines · Beno?t Th?baudeau

Quoted 15 lines · Eric Nelson
Quoted 11 lines · Beno?t Th?baudeau
MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.
For all DDR3 speed bins:
tMRD(min) = 4 nCK
tMOD(min) = max(12 nCK, 15 ns)
Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK
at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].
Signed-off-by Beno?t Th?baudeau <[email protected]>
Hi Beno?t,

Quoted 9 lines

Quoted 2 lines
I've been able to confirm operation of this complete patch set on a SABRE Lite here, but only that (boots normally).
Great.
Quoted 1 line
I'll try to scare up a board we can place on an extended burn-in.
That'd be good.

I tested one board overnight running a Linux-based memory test and things worked perfectly.

I also tested using CONFIG_SYS_ALT_MEMTEST and measured the performance difference between

Nitrogen6x board (old memory timings):

	U-Boot > time mtest 10000000 10400000 0 10
	Testing 10000000 ... 10400000:
	Tested 16 iteration(s) with 0 errors.

	time: 1 minutes, 11.311 seconds, 71311 ticks

SABRE Lite board (new memory timings):

	MX6QSABRELITE U-Boot > dcache off
	MX6QSABRELITE U-Boot > time mtest 10000000 10400000 0 10
	Testing 10000000 ... 10400000:
	Tested 16 iteration(s) with 0 errors.

	time: 1 minutes, 10.143 seconds, 70143 ticks

I also tested with cache enabled and things worked perfectly.

Quoted 6 lines

Quoted 2 lines
What prompted you to walk the list? Was there a specific failure that this addressed?
No specific failure. The only issue that I get from time to time is errors in the Linux SD driver, but this is probably unrelated.

Quoted 8 lines

The only reason was that I was looking for possible better performance on the RAM side because I am working on very intensive RAM accessing applications. So I checked the init code to see if it was optimal, and I found these issues besides the small possible performance gain.
So far, the default mtest passed on my board. The alternate mtest and more Linux stress tests might be interesting too.

For the series:

Tested-by Eric Nelson <[email protected]>

Benoît Thébaudeau

author

2013-02-01 18:29 UTC #9 lore raw

PATCH 1/6 imx: mx6q DDR3 init: Fix tMRD

Hi Eric,

Quoted 67 lines · Eric Nelson

Hi Beno?t,
Quoted 16 lines · Beno?t Th?baudeau
Quoted 15 lines · Eric Nelson
Quoted 11 lines · Beno?t Th?baudeau
MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.
For all DDR3 speed bins:
tMRD(min) = 4 nCK
tMOD(min) = max(12 nCK, 15 ns)
Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK
at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].
Signed-off-by Beno?t Th?baudeau <[email protected]>
Hi Beno?t,
Quoted 9 lines
Quoted 2 lines
I've been able to confirm operation of this complete patch set on a SABRE Lite here, but only that (boots normally).
Great.
Quoted 1 line
I'll try to scare up a board we can place on an extended burn-in.
That'd be good.
I tested one board overnight running a Linux-based memory test and things worked perfectly.
I also tested using CONFIG_SYS_ALT_MEMTEST and measured the performance difference between
Nitrogen6x board (old memory timings):
	U-Boot > time mtest 10000000 10400000 0 10
	Testing 10000000 ... 10400000:
	Tested 16 iteration(s) with 0 errors.

	time: 1 minutes, 11.311 seconds, 71311 ticks
SABRE Lite board (new memory timings):
	MX6QSABRELITE U-Boot > dcache off
	MX6QSABRELITE U-Boot > time mtest 10000000 10400000 0 10
	Testing 10000000 ... 10400000:
	Tested 16 iteration(s) with 0 errors.

	time: 1 minutes, 10.143 seconds, 70143 ticks
I also tested with cache enabled and things worked perfectly.
Quoted 15 lines
Quoted 2 lines
What prompted you to walk the list? Was there a specific failure that this addressed?
No specific failure. The only issue that I get from time to time is errors in
the Linux SD driver, but this is probably unrelated.
The only reason was that I was looking for possible better performance on the
RAM side because I am working on very intensive RAM accessing applications. So I
checked the init code to see if it was optimal, and I found these issues besides
the small possible performance gain.

Quoted 7 lines

Quoted 4 lines
So far, the default mtest passed on my board. The alternate mtest and more Linux
stress tests might be interesting too.
For the series:
Tested-by Eric Nelson <[email protected]>

Thank you very much for your thorough tests!

Best regards,
Beno?t

Stefano Babic

2013-02-12 12:53 UTC #10 lore raw

PATCH 1/6 imx: mx6q DDR3 init: Fix tMRD

In reply to Benoît Thébaudeau

Quoted 19 lines · Beno?t Th?baudeau

MMDC1_MDCFG1.tMRD should be set to max(tMRD, tMOD) for DDR3.
For all DDR3 speed bins:
tMRD(min) = 4 nCK
tMOD(min) = max(12 nCK, 15 ns)
Hence, MMDC1_MDCFG1.tMRD should be set to max(12 nCK, 15 ns), which is 12 nCK at 532 MHz, encoded as 0xB in the bit-field MMDC1_MDCFG1[8:5].
Signed-off-by Beno?t Th?baudeau <[email protected]>
---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +0 -0
index c86cd40..9ac8027 100644

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg DATA 4 0x021b0018 0x00081740 · line 116

Quoted 8 lines

board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +1 -1

@@ -110,7 +110,7 @@ DATA 4 0x021b0018 0x00081740
 
 DATA 4 0x021b001c 0x00008000
 DATA 4 0x021b000c 0x555A7975
-DATA 4 0x021b0010 0xFF538E64
+DATA 4 0x021b0010 0xFF538F64
 DATA 4 0x021b0014 0x01FF00DB
 DATA 4 0x021b002c 0x000026D2

Applied (whole series) to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

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