clk: rockchip: fix rk3066 pll lock bit location
Subsystems (2)
Heiko Stübner
maintainerPATCH 1/1 clk: rockchip: fix rk3066 pll lock bit location
The bit locations indicating the locking status of the plls on rk3066 are shifted by one to the right when compared to the rk3188, bits [7:4] instead of [8:5] on the rk3188, thus indicating the locking state of the wrong pll or a completely different information in case of the gpll.
The recently introduced pll init code exposed that problem on some rk3066 boards when it tried to bring the boot-pll value in line with the value from the rate table.
Fix this by defining separate pll definitions for rk3066 with the correct locking indices.
--- drivers/clk/rockchip/clk-rk3188.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-)
drivers/clk/rockchip/clk-rk3188.c +13 -2
@@ -210,6 +210,17 @@ PNAME(mux_sclk_hsadc_p) = { "hsadc_src", "hsadc_frac", "ext_hsadc" };PNAME (mux_mac_p) = {"gpll" ,"dpll" };PNAME (mux_sclk_macref_p) = {"mac_src" ,"ext_rmii" }; +static struct rockchip_pll_clock rk3066_pll_clks[]__initdata = { + [apll] =PLL (pll_rk3066,PLL_APLL ,"apll" , mux_pll_p,0 ,RK2928_PLL_CON (0 ), +RK2928_MODE_CON ,0 ,5 ,0 , rk3188_pll_rates), + [dpll] =PLL (pll_rk3066,PLL_DPLL ,"dpll" , mux_pll_p,0 ,RK2928_PLL_CON (4 ), +RK2928_MODE_CON ,4 ,4 ,0 ,NULL ), + [cpll] =PLL (pll_rk3066,PLL_CPLL ,"cpll" , mux_pll_p,0 ,RK2928_PLL_CON (8 ), +RK2928_MODE_CON ,8 ,6 ,ROCKCHIP_PLL_SYNC_RATE , rk3188_pll_rates), + [gpll] =PLL (pll_rk3066,PLL_GPLL ,"gpll" , mux_pll_p,0 ,RK2928_PLL_CON (12 ), +RK2928_MODE_CON ,12 ,7 ,ROCKCHIP_PLL_SYNC_RATE , rk3188_pll_rates), +}; +static struct rockchip_pll_clock rk3188_pll_clks[]__initdata = { [apll] =PLL (pll_rk3066,PLL_APLL ,"apll" , mux_pll_p,0 ,RK2928_PLL_CON (0 ),RK2928_MODE_CON ,0 ,6 ,0 , rk3188_pll_rates),
@@ -735,8 +746,8 @@ static void __init rk3188_common_clk_init(struct device_node *np)static void __init rk3066a_clk_init (struct device_node *np) {rk3188_common_clk_init (np); -rockchip_clk_register_plls (rk3188_pll_clks, -ARRAY_SIZE (rk3188_pll_clks), +rockchip_clk_register_plls (rk3066_pll_clks, +ARRAY_SIZE (rk3066_pll_clks),RK3066_GRF_SOC_STATUS );rockchip_clk_register_branches (rk3066a_clk_branches,ARRAY_SIZE (rk3066a_clk_branches));
Signature · 1 line
2.1.1
PATCH 1/1 clk: rockchip: fix rk3066 pll lock bit location
hi,
Quoted 9 lines · Heiko St?bner
The bit locations indicating the locking status of the plls on rk3066 are shifted by one to the right when compared to the rk3188, bits [7:4] instead of [8:5] on the rk3188, thus indicating the locking state of the wrong pll or a completely different information in case of the gpll.
The recently introduced pll init code exposed that problem on some rk3066 boards when it tried to bring the boot-pll value in line with the value from the rate table.
Quoted 7 lines
Fix this by defining separate pll definitions for rk3066 with the correct locking indices.
Signed-off-by Heiko Stuebner <[email protected]>--- drivers/clk/rockchip/clk-rk3188.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-)
it worked fine on ChipSPARK Rayeager PX2(=RK3066) board, thanks!
Heiko Stübner
maintainerPATCH 1/1 clk: rockchip: fix rk3066 pll lock bit location
In reply to Heiko StübnerAm Mittwoch, 24. Dezember 2014, 15:11:00 schrieb Heiko St?bner:
Quoted 5 lines
The bit locations indicating the locking status of the plls on rk3066 are shifted by one to the right when compared to the rk3188, bits [7:4] instead of [8:5] on the rk3188, thus indicating the locking state of the wrong pll or a completely different information in case of the gpll.
Quoted 8 lines
The recently introduced pll init code exposed that problem on some rk3066 boards when it tried to bring the boot-pll value in line with the value from the rate table.
Fix this by defining separate pll definitions for rk3066 with the correct locking indices.
Signed-off-by Heiko Stuebner <[email protected]>
applied to my clk-fixes branch with naobsd's tested-by.
I've also received another positive response of the patch fixing the issue on IRC.
Heiko