ARM: dts: exynos4: Use drive strength 3 for SD pins
Subsystems (2)
PATCH 1/1 ARM: dts: exynos4: Use drive strength 3 for SD pins
This patch modifies pin control groups of SD pins on Exynos4210 and Exynos4x12 to use drive strength 3, which corresponds to S5P_GPIO_DRVSTR_LV4 in legacy non-DT code.
This is needed at least on Origen board for sdhci2 to work.
--- arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 56 +++++++++++++++---------------- arch/arm/boot/dts/exynos4x12-pinctrl.dtsi | 56 +++++++++++++++---------------- 2 files changed, 56 insertions(+), 56 deletions(-)
arch/arm/boot/dts/exynos4210-pinctrl.dtsi +28 -28
@@ -482,196 +482,196 @@ samsung,pins = "gpk0-0"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd0_cmd: sd0-cmd { samsung,pins = "gpk0-1"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd0_cd: sd0-cd { samsung,pins = "gpk0-2"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd0_bus1: sd0-bus-width1 { samsung,pins = "gpk0-3"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd0_bus4: sd0-bus-width4 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd0_bus8: sd0-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_clk: sd4-clk { samsung,pins = "gpk0-0"; samsung,pin-function = <3>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_cmd: sd4-cmd { samsung,pins = "gpk0-1"; samsung,pin-function = <3>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_cd: sd4-cd { samsung,pins = "gpk0-2"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_bus1: sd4-bus-width1 { samsung,pins = "gpk0-3"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_bus4: sd4-bus-width4 { samsung,pins = "gpk0-3", "gpk0-4", "gpk0-5", "gpk0-6"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd4_bus8: sd4-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <3>; samsung,pin-pud = <4>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd1_clk: sd1-clk { samsung,pins = "gpk1-0"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd1_cmd: sd1-cmd { samsung,pins = "gpk1-1"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd1_cd: sd1-cd { samsung,pins = "gpk1-2"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd1_bus1: sd1-bus-width1 { samsung,pins = "gpk1-3"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd1_bus4: sd1-bus-width4 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_clk: sd2-clk { samsung,pins = "gpk2-0"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_cmd: sd2-cmd { samsung,pins = "gpk2-1"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_cd: sd2-cd { samsung,pins = "gpk2-2"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_bus1: sd2-bus-width1 { samsung,pins = "gpk2-3"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_bus4: sd2-bus-width4 { samsung,pins = "gpk2-3", "gpk2-4", "gpk2-5", "gpk2-6"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd2_bus8: sd2-bus-width8 { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = <3>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd3_clk: sd3-clk { samsung,pins = "gpk3-0"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd3_cmd: sd3-cmd { samsung,pins = "gpk3-1"; samsung,pin-function = <2>; samsung,pin-pud = <0>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd3_cd: sd3-cd { samsung,pins = "gpk3-2"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd3_bus1: sd3-bus-width1 { samsung,pins = "gpk3-3"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; sd3_bus4: sd3-bus-width4 { samsung,pins = "gpk3-3", "gpk3-4", "gpk3-5", "gpk3-6"; samsung,pin-function = <2>; samsung,pin-pud = <3>; - samsung,pin-drv = <0>; + samsung,pin-drv = <3>; }; eint0: ext-int0 {
arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +28 -28
224 lines not on this page · raw message
Signature · 1 line
1.8.0
PATCH 1/1 ARM: dts: exynos4: Use drive strength 3 for SD pins
Quoted 5 lines · Tomasz Figa
This patch modifies pin control groups of SD pins on Exynos4210 and Exynos4x12 to use drive strength 3, which corresponds to
S5P_GPIO_DRVSTR_LV4in legacy non-DT code.
Well, the value of drive strength depends on board not SoC. So if required, it should be moved to board DT stuff.
BTW, we can use the value as a default...I need to think about that again for exynos4210 and 4x12.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.
Quoted 10 lines
This is needed at least on Origen board for sdhci2 to work.
Signed-off-by Tomasz Figa <[email protected]>Signed-off-by Kyungmin Park <[email protected]>--- arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 56 +++++++++++++++----------- ----- arch/arm/boot/dts/exynos4x12-pinctrl.dtsi | 56 +++++++++++++++----------- ----- 2 files changed, 56 insertions(+), 56 deletions(-)
PATCH 1/1 ARM: dts: exynos4: Use drive strength 3 for SD pins
Hi Kgene,
Quoted 7 lines · On Tuesday 20 of November 2012 18:18:44 Kukjin Kim wrote:
Quoted 3 lines · Tomasz Figa
This patch modifies pin control groups of SD pins on Exynos4210 and Exynos4x12 to use drive strength 3, which corresponds to
S5P_GPIO_DRVSTR_LV4in legacy non-DT code.Well, the value of drive strength depends on board not SoC. So if required, it should be moved to board DT stuff.
Yes, I fully agree.
I've been thinking whether to change the defaults or just override them for Origen, but I came to a conclusion that 3 (LV4) was the default in non-DT code, so it probably should be also the default in DT variant.
Quoted 2 lines
BTW, we can use the value as a default...I need to think about that again for exynos4210 and 4x12.
I wonder which default value is more appropriate, 0 or 3?
Best regards,
Signature · 3 lines
Tomasz Figa Samsung Poland R&D Center SW Solution Development, Linux Platform
PATCH 1/1 ARM: dts: exynos4: Use drive strength 3 for SD pins
Quoted 9 lines · Tomasz Figa
Hi Kgene,
Quoted 5 lines · On Tuesday 20 of November 2012 18:18:44 Kukjin Kim wrote:
Quoted 3 lines · Tomasz Figa
This patch modifies pin control groups of SD pins on Exynos4210 and Exynos4x12 to use drive strength 3, which corresponds to
S5P_GPIO_DRVSTR_LV4in legacy non-DT code.
Quoted 9 lines
Quoted 2 lines
Well, the value of drive strength depends on board not SoC. So if required, it should be moved to board DT stuff.
Yes, I fully agree.
I've been thinking whether to change the defaults or just override them for Origen, but I came to a conclusion that 3 (LV4) was the default in non-DT code, so it probably should be also the default in DT variant.
OK.
Quoted 5 lines
Quoted 2 lines
BTW, we can use the value as a default...I need to think about that again for exynos4210 and 4x12.
I wonder which default value is more appropriate, 0 or 3?
In this case, yes, '3' is more useful...so can you re-submit this patch with editing commit?
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.
PATCH 1/1 ARM: dts: exynos4: Use drive strength 3 for SD pins
Hi Kgene,
Quoted 22 lines · On Tuesday 20 of November 2012 20:10:25 Kukjin Kim wrote:
Quoted 12 lines · Tomasz Figa
Hi Kgene,
Quoted 8 lines · On Tuesday 20 of November 2012 18:18:44 Kukjin Kim wrote:
Quoted 4 lines · Tomasz Figa
This patch modifies pin control groups of SD pins on Exynos4210 and
Exynos4x12 to use drive strength 3, which corresponds toS5P_GPIO_DRVSTR_LV4in legacy non-DT code.Well, the value of drive strength depends on board not SoC. So if required, it should be moved to board DT stuff.
Quoted 6 lines
Yes, I fully agree.
I've been thinking whether to change the defaults or just override them
for Origen, but I came to a conclusion that 3 (LV4) was the default in non-DT code, so it probably should be also the default in DT variant.OK.
Quoted 7 lines
Quoted 4 lines
Quoted 2 lines
BTW, we can use the value as a default...I need to think about that again for exynos4210 and 4x12.
I wonder which default value is more appropriate, 0 or 3?
In this case, yes, '3' is more useful...so can you re-submit this patch with editing commit?
I can resubmit this patch, but I'm not sure what you expect me to edit. Could you explain?
If possible, it would be nice to get this included in 3.8 as it's required for Origen board to boot with device tree.
Best regards,
Signature · 3 lines
Tomasz Figa Samsung Poland R&D Center SW Solution Development, Linux Platform
PATCH 1/1 ARM: dts: exynos4: Use drive strength 3 for SD pins
Quoted 29 lines · Tomasz Figa
Hi Kgene,
Quoted 25 lines · On Tuesday 20 of November 2012 20:10:25 Kukjin Kim wrote:
Quoted 12 lines · Tomasz Figa
Hi Kgene,
Quoted 8 lines · On Tuesday 20 of November 2012 18:18:44 Kukjin Kim wrote:
Quoted 4 lines · Tomasz Figa
This patch modifies pin control groups of SD pins on Exynos4210 and
Exynos4x12 to use drive strength 3, which corresponds toS5P_GPIO_DRVSTR_LV4in legacy non-DT code.Well, the value of drive strength depends on board not SoC. So if required, it should be moved to board DT stuff.
Quoted 6 lines
Yes, I fully agree.
I've been thinking whether to change the defaults or just override them
for Origen, but I came to a conclusion that 3 (LV4) was the default in non-DT code, so it probably should be also the default in DT variant.OK.
Quoted 3 lines
Quoted 2 lines
BTW, we can use the value as a default...I need to think about that again for exynos4210 and 4x12.
Quoted 8 lines
Quoted 4 lines
Quoted 1 line
I wonder which default value is more appropriate, 0 or 3?
In this case, yes, '3' is more useful...so can you re-submit this patch with editing commit?
I can resubmit this patch, but I'm not sure what you expect me to edit. Could you explain?
Hmm, I mean the commit message needs explanation is why to use '3' as a default value is more useful. OK, if you don't mind, I will edit it when I apply.
Quoted 3 lines
If possible, it would be nice to get this included in 3.8 as it's required for Origen board to boot with device tree.
OK, as we discussed, I agree with this.
Will apply, thanks.
Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.