pinctrl: rockchip: generalize perpin driver-strength setting

PATCH New Heiko Stübner 2 participants 4 messages Jun 12, 2015 – Jun 17, 2015

Subsystems (4)

Device tree bindings GPIO Arm Rockchip Pin control

lore

Share & tools

lore

Heiko Stübner

author maintainer

2015-06-12 21:50 UTC #0 lore raw

PATCH 1/2 pinctrl: rockchip: generalize perpin driver-strength setting

The upcoming support for the RK3368 ARM64 SoC also supports perpin drive strength settings (at different register positions), so generalize the register and offset calculation to easily support this one too.

Signed-off-by Heiko Stuebner <[email protected]>

---
 drivers/pinctrl/pinctrl-rockchip.c | 36 +++++++++++++++++++++++-------------
 1 file changed, 23 insertions(+), 13 deletions(-)

drivers/pinctrl/pinctrl-rockchip.c +23 ~~-13~~

index dee7d5f..70423ae 100644
@@ -163,6 +163,9 @@ struct rockchip_pin_ctrl {
 	void	(*pull_calc_reg)(struct rockchip_pin_bank *bank,
 				    int pin_num, struct regmap **regmap,
 				    int *reg, u8 *bit);
+	void	(*drv_calc_reg)(struct rockchip_pin_bank *bank,
+				    int pin_num, struct regmap **regmap,
+				    int *reg, u8 *bit);
 };
 
 struct rockchip_pin_config {

@@ -581,7 +584,6 @@ static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
 #define RK3288_DRV_BITS_PER_PIN		2
 #define RK3288_DRV_PINS_PER_REG		8
 #define RK3288_DRV_BANK_STRIDE		16
-static int rk3288_drv_list[] = { 2, 4, 8, 12 };
 
 static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 				    int pin_num, struct regmap **regmap,

@@ -611,14 +613,19 @@ static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
 	}
 }
 
-static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
+static int rockchip_perpin_drv_list[] = { 2, 4, 8, 12 };
+
+static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
+				     int pin_num)
 {
+	struct rockchip_pinctrl *info = bank->drvdata;
+	struct rockchip_pin_ctrl *ctrl = info->ctrl;
 	struct regmap *regmap;
 	int reg, ret;
 	u32 data;
 	u8 bit;
 
-	rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 
 	ret = regmap_read(regmap, reg, &data);
 	if (ret)

@@ -627,24 +634,25 @@ static int rk3288_get_drive(struct rockchip_pin_bank *bank, int pin_num)
 	data >>= bit;
 	data &= (1 << RK3288_DRV_BITS_PER_PIN) - 1;
 
-	return rk3288_drv_list[data];
+	return rockchip_perpin_drv_list[data];
 }
 
-static int rk3288_set_drive(struct rockchip_pin_bank *bank, int pin_num,
-			    int strength)
+static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
+				     int pin_num, int strength)
 {
 	struct rockchip_pinctrl *info = bank->drvdata;
+	struct rockchip_pin_ctrl *ctrl = info->ctrl;
 	struct regmap *regmap;
 	unsigned long flags;
 	int reg, ret, i;
 	u32 data, rmask;
 	u8 bit;
 
-	rk3288_calc_drv_reg_and_bit(bank, pin_num, &regmap, &reg, &bit);
+	ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
 
 	ret = -EINVAL;
-	for (i = 0; i < ARRAY_SIZE(rk3288_drv_list); i++) {
-		if (rk3288_drv_list[i] == strength) {
+	for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list); i++) {
+		if (rockchip_perpin_drv_list[i] == strength) {
 			ret = i;
 			break;
 		}

@@ -983,10 +991,11 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 			break;
 		case PIN_CONFIG_DRIVE_STRENGTH:
 			/* rk3288 is the first with per-pin drive-strength */
-			if (info->ctrl->type != RK3288)
+			if (!info->ctrl->drv_calc_reg)
 				return -ENOTSUPP;
 
-			rc = rk3288_set_drive(bank, pin - bank->pin_base, arg);
+			rc = rockchip_set_drive_perpin(bank,
+						pin - bank->pin_base, arg);
 			if (rc < 0)
 				return rc;
 			break;

@@ -1041,10 +1050,10 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 		break;
 	case PIN_CONFIG_DRIVE_STRENGTH:
 		/* rk3288 is the first with per-pin drive-strength */
-		if (info->ctrl->type != RK3288)
+		if (!info->ctrl->drv_calc_reg)
 			return -ENOTSUPP;
 
-		rc = rk3288_get_drive(bank, pin - bank->pin_base);
+		rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
 		if (rc < 0)
 			return rc;

@@ -2056,6 +2065,7 @@ static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
 		.grf_mux_offset		= 0x0,
 		.pmu_mux_offset		= 0x84,
 		.pull_calc_reg		= rk3288_calc_pull_reg_and_bit,
+		.drv_calc_reg		= rk3288_calc_drv_reg_and_bit,
 };
 
 static const struct of_device_id rockchip_pinctrl_dt_match[] = {

Signature · 1 line

2.1.4

Heiko Stübner

author maintainer

2015-06-12 21:51 UTC #1 lore raw

PATCH 2/2 pinctrl: rockchip: add support for the rk3368

The rk3368 is the first ARM64 soc from Rockchip, but seems to share most peripherals with the ARM32 soc, including the pinctrl functionality. The only notable difference is - as with every Rockchip soc - that the offsets in the General Register Files moved around and a split of the pmu section of the rk3288 into pmu and pmugrf (pmu general register files) sections. The pinctrl driver of course only needs the pmugrf registers for controlling the pin settings.

Signed-off-by Heiko Stuebner <[email protected]>

---
 .../bindings/pinctrl/rockchip,pinctrl.txt          |  5 +-
 drivers/pinctrl/pinctrl-rockchip.c                 | 91 ++++++++++++++++++++++
 2 files changed, 94 insertions(+), 2 deletions(-)

Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt +3 -2

index 388b213..391ef4b 100644
@@ -21,14 +21,15 @@ defined as gpio sub-nodes of the pinmux controller.
 Required properties for iomux controller:
   - compatible: one of "rockchip,rk2928-pinctrl", "rockchip,rk3066a-pinctrl"
 		       "rockchip,rk3066b-pinctrl", "rockchip,rk3188-pinctrl"
-		       "rockchip,rk3288-pinctrl"
+		       "rockchip,rk3288-pinctrl", "rockchip,rk3368-pinctrl"
   - rockchip,grf: phandle referencing a syscon providing the
 	 "general register files"
 
 Optional properties for iomux controller:
   - rockchip,pmu: phandle referencing a syscon providing the pmu registers
 	 as some SoCs carry parts of the iomux controller registers there.
-	 Required for at least rk3188 and rk3288.
+	 Required for at least rk3188 and rk3288. On the rk3368 this should
+	 point to the PMUGRF syscon.
 
 Deprecated properties for iomux controller:
   - reg: first element is the general register space of the iomux controller

drivers/pinctrl/pinctrl-rockchip.c +91 -0

133 lines not on this page · raw message

Signature · 1 line

2.1.4

Linus Walleij

2015-06-17 08:21 UTC #2 lore raw

PATCH 2/2 pinctrl: rockchip: add support for the rk3368

Quoted 9 lines · Heiko St?bner

The rk3368 is the first ARM64 soc from Rockchip, but seems to share most peripherals with the ARM32 soc, including the pinctrl functionality. The only notable difference is - as with every Rockchip soc - that the offsets in the General Register Files moved around and a split of the pmu section of the rk3288 into pmu and pmugrf (pmu general register files) sections. The pinctrl driver of course only needs the pmugrf registers for controlling the pin settings.
Signed-off-by Heiko Stuebner <[email protected]>

Patch applied.

Yours,
Linus Walleij

Linus Walleij

2015-06-17 08:20 UTC #3 lore raw

PATCH 1/2 pinctrl: rockchip: generalize perpin driver-strength setting

In reply to Heiko Stübner

Quoted 5 lines · Heiko St?bner

The upcoming support for the RK3368 ARM64 SoC also supports perpin drive strength settings (at different register positions), so generalize the register and offset calculation to easily support this one too.
Signed-off-by Heiko Stuebner <[email protected]>

Patch applied.

Yours,
Linus Walleij