sunxi: video: Add support for HDMI output on A64/H3/H5

deleted file mode 100644
index 0b51d40882..0000000000
@@ -1,456 +0,0 @@
-/*
- * Copyright (c) 2015 Google, Inc
- * Copyright 2014 Rockchip Inc.
- * Copyright (C) 2011 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_HDMI_H
-#define _ASM_ARCH_HDMI_H
-
-
-#define HDMI_EDID_BLOCK_SIZE            128
-
-struct rk3288_hdmi {
-	u32 reserved0[0x100];
-	u32 ih_fc_stat0;
-	u32 ih_fc_stat1;
-	u32 ih_fc_stat2;
-	u32 ih_as_stat0;
-	u32 ih_phy_stat0;
-	u32 ih_i2cm_stat0;
-	u32 ih_cec_stat0;
-	u32 ih_vp_stat0;
-	u32 ih_i2cmphy_stat0;
-	u32 ih_ahbdmaaud_stat0;
-	u32 reserved1[0x17f-0x109];
-	u32 ih_mute_fc_stat0;
-	u32 ih_mute_fc_stat1;
-	u32 ih_mute_fc_stat2;
-	u32 ih_mute_as_stat0;
-	u32 ih_mute_phy_stat0;
-	u32 ih_mute_i2cm_stat0;
-	u32 ih_mute_cec_stat0;
-	u32 ih_mute_vp_stat0;
-	u32 ih_mute_i2cmphy_stat0;
-	u32 ih_mute_ahbdmaaud_stat0;
-	u32 reserved2[0x1fe - 0x189];
-	u32 ih_mute;
-	u32 tx_invid0;
-	u32 tx_instuffing;
-	u32 tx_gydata0;
-	u32 tx_gydata1;
-	u32 tx_rcrdata0;
-	u32 tx_rcrdata1;
-	u32 tx_bcbdata0;
-	u32 tx_bcbdata1;
-	u32 reserved3[0x7ff-0x207];
-	u32 vp_status;
-	u32 vp_pr_cd;
-	u32 vp_stuff;
-	u32 vp_remap;
-	u32 vp_conf;
-	u32 vp_stat;
-	u32 vp_int;
-	u32 vp_mask;
-	u32 vp_pol;
-	u32 reserved4[0xfff-0x808];
-	u32 fc_invidconf;
-	u32 fc_inhactv0;
-	u32 fc_inhactv1;
-	u32 fc_inhblank0;
-	u32 fc_inhblank1;
-	u32 fc_invactv0;
-	u32 fc_invactv1;
-	u32 fc_invblank;
-	u32 fc_hsyncindelay0;
-	u32 fc_hsyncindelay1;
-	u32 fc_hsyncinwidth0;
-	u32 fc_hsyncinwidth1;
-	u32 fc_vsyncindelay;
-	u32 fc_vsyncinwidth;
-	u32 fc_infreq0;
-	u32 fc_infreq1;
-	u32 fc_infreq2;
-	u32 fc_ctrldur;
-	u32 fc_exctrldur;
-	u32 fc_exctrlspac;
-	u32 fc_ch0pream;
-	u32 fc_ch1pream;
-	u32 fc_ch2pream;
-	u32 fc_aviconf3;
-	u32 fc_gcp;
-	u32 fc_aviconf0;
-	u32 fc_aviconf1;
-	u32 fc_aviconf2;
-	u32 fc_avivid;
-	u32 fc_avietb0;
-	u32 fc_avietb1;
-	u32 fc_avisbb0;
-	u32 fc_avisbb1;
-	u32 fc_avielb0;
-	u32 fc_avielb1;
-	u32 fc_avisrb0;
-	u32 fc_avisrb1;
-	u32 fc_audiconf0;
-	u32 fc_audiconf1;
-	u32 fc_audiconf2;
-	u32 fc_audiconf3;
-	u32 fc_vsdieeeid0;
-	u32 fc_vsdsize;
-	u32 reserved7[0x2fff-0x102a];
-	u32 phy_conf0;
-	u32 phy_tst0;
-	u32 phy_tst1;
-	u32 phy_tst2;
-	u32 phy_stat0;
-	u32 phy_int0;
-	u32 phy_mask0;
-	u32 phy_pol0;
-	u32 reserved8[0x301f-0x3007];
-	u32 phy_i2cm_slave_addr;
-	u32 phy_i2cm_address_addr;
-	u32 phy_i2cm_datao_1_addr;
-	u32 phy_i2cm_datao_0_addr;
-	u32 phy_i2cm_datai_1_addr;
-	u32 phy_i2cm_datai_0_addr;
-	u32 phy_i2cm_operation_addr;
-	u32 phy_i2cm_int_addr;
-	u32 phy_i2cm_ctlint_addr;
-	u32 phy_i2cm_div_addr;
-	u32 phy_i2cm_softrstz_addr;
-	u32 phy_i2cm_ss_scl_hcnt_1_addr;
-	u32 phy_i2cm_ss_scl_hcnt_0_addr;
-	u32 phy_i2cm_ss_scl_lcnt_1_addr;
-	u32 phy_i2cm_ss_scl_lcnt_0_addr;
-	u32 phy_i2cm_fs_scl_hcnt_1_addr;
-	u32 phy_i2cm_fs_scl_hcnt_0_addr;
-	u32 phy_i2cm_fs_scl_lcnt_1_addr;
-	u32 phy_i2cm_fs_scl_lcnt_0_addr;
-	u32 reserved9[0x30ff-0x3032];
-	u32 aud_conf0;
-	u32 aud_conf1;
-	u32 aud_int;
-	u32 aud_conf2;
-	u32 aud_int1;
-	u32 reserved32[0x31ff-0x3104];
-	u32 aud_n1;
-	u32 aud_n2;
-	u32 aud_n3;
-	u32 aud_cts1;
-	u32 aud_cts2;
-	u32 aud_cts3;
-	u32 aud_inputclkfs;
-	u32 reserved12[0x3fff-0x3206];
-	u32 mc_sfrdiv;
-	u32 mc_clkdis;
-	u32 mc_swrstz;
-	u32 mc_opctrl;
-	u32 mc_flowctrl;
-	u32 mc_phyrstz;
-	u32 mc_lockonclock;
-	u32 mc_heacphy_rst;
-	u32 reserved13[0x40ff-0x4007];
-	u32 csc_cfg;
-	u32 csc_scale;
-	struct {
-		u32 msb;
-		u32 lsb;
-	} csc_coef[3][4];
-	u32 reserved17[0x7dff-0x4119];
-	u32 i2cm_slave;
-	u32 i2c_address;
-	u32 i2cm_datao;
-	u32 i2cm_datai;
-	u32 i2cm_operation;
-	u32 i2cm_int;
-	u32 i2cm_ctlint;
-	u32 i2cm_div;
-	u32 i2cm_segaddr;
-	u32 i2cm_softrstz;
-	u32 i2cm_segptr;
-	u32 i2cm_ss_scl_hcnt_1_addr;
-	u32 i2cm_ss_scl_hcnt_0_addr;
-	u32 i2cm_ss_scl_lcnt_1_addr;
-	u32 i2cm_ss_scl_lcnt_0_addr;
-	u32 i2cm_fs_scl_hcnt_1_addr;
-	u32 i2cm_fs_scl_hcnt_0_addr;
-	u32 i2cm_fs_scl_lcnt_1_addr;
-	u32 i2cm_fs_scl_lcnt_0_addr;
-	u32 reserved18[0x7e1f-0x7e12];
-	u32 i2cm_buf0;
-};
-check_member(rk3288_hdmi, i2cm_buf0, 0x1f880);
-
-enum {
-	/* HDMI PHY registers define */
-	PHY_OPMODE_PLLCFG = 0x06,
-	PHY_CKCALCTRL = 0x05,
-	PHY_CKSYMTXCTRL = 0x09,
-	PHY_VLEVCTRL = 0x0e,
-	PHY_PLLCURRCTRL = 0x10,
-	PHY_PLLPHBYCTRL = 0x13,
-	PHY_PLLGMPCTRL = 0x15,
-	PHY_PLLCLKBISTPHASE = 0x17,
-	PHY_TXTERM = 0x19,
-
-	/* ih_phy_stat0 field values */
-	HDMI_IH_PHY_STAT0_HPD = 0x1,
-
-	/* ih_mute field values */
-	HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
-	HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
-
-	/* tx_invid0 field values */
-	HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
-	HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
-	HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
-
-	/* tx_instuffing field values */
-	HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
-	HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
-	HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
-
-	/* vp_pr_cd field values */
-	HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
-	HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
-	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
-	HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
-
-	/* vp_stuff field values */
-	HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
-	HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
-	HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
-	HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
-	HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
-	HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
-	HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
-	HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
-
-	/* vp_conf field values */
-	HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
-	HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
-	HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
-	HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
-	HDMI_VP_CONF_PR_EN_MASK = 0x10,
-	HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
-	HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
-	HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
-	HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
-	HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
-	HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
-	HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
-
-	/* vp_remap field values */
-	HDMI_VP_REMAP_YCC422_16BIT = 0x0,
-
-	/* fc_invidconf field values */
-	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
-	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
-	HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
-	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
-	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
-	HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
-	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
-	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
-	HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
-	HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
-	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
-	HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
-	HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
-	HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
-	HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
-	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
-	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
-	HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
-	HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
-	HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
-	HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
-
-
-	/* fc_aviconf0-fc_aviconf3 field values */
-	HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
-	HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
-	HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
-	HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
-	HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
-	HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
-	HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
-	HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
-	HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
-	HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
-	HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
-	HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
-	HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
-	HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
-	HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
-	HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
-
-	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
-	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
-	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
-	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
-	HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
-	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
-	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
-	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
-	HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
-	HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
-	HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
-	HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
-	HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
-	HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
-
-	HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
-	HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
-	HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
-	HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
-	HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
-	HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
-	HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
-	HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
-	HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
-	HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
-	HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
-	HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
-	HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
-
-	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
-	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
-	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
-	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
-	HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
-	HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
-	HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
-	HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
-
-	/* fc_gcp field values*/
-	HDMI_FC_GCP_SET_AVMUTE = 0x02,
-	HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
-
-	/* phy_conf0 field values */
-	HDMI_PHY_CONF0_PDZ_MASK = 0x80,
-	HDMI_PHY_CONF0_PDZ_OFFSET = 7,
-	HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
-	HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
-	HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
-	HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
-	HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
-	HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
-	HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
-	HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
-	HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
-	HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
-	HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
-	HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
-
-	/* phy_tst0 field values */
-	HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
-	HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
-
-	/* phy_stat0 field values */
-	HDMI_PHY_HPD = 0x02,
-	HDMI_PHY_TX_PHY_LOCK = 0x01,
-
-	/* phy_i2cm_slave_addr field values */
-	HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
-
-	/* phy_i2cm_operation_addr field values */
-	HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
-
-	/* hdmi_phy_i2cm_int_addr */
-	HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
-
-	/* hdmi_phy_i2cm_ctlint_addr */
-	HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
-	HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
-
-	/* aud_conf0 field values */
-	HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
-	HDMI_AUD_CONF0_I2S_SELECT = 0x20,
-	HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
-	HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
-	HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
-	HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
-
-	/* aud_conf0 field values */
-	HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
-	HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
-
-	/* aud_n3 field values */
-	HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
-	HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
-
-	/* aud_cts3 field values */
-	HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
-	HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
-	HDMI_AUD_CTS3_N_SHIFT_1 = 0,
-	HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
-	HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
-	HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
-	HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
-	HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
-	HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
-	HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
-
-	/* aud_inputclkfs filed values */
-	HDMI_AUD_INPUTCLKFS_128 = 0x0,
-
-	/* mc_clkdis field values */
-	HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
-	HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
-	HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
-
-	/* mc_swrstz field values */
-	HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
-	HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
-
-	/* mc_flowctrl field values */
-	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
-	HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
-
-	/* mc_phyrstz field values */
-	HDMI_MC_PHYRSTZ_ASSERT = 0x0,
-	HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
-
-	/* mc_heacphy_rst field values */
-	HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
-
-	/* csc_cfg field values */
-	HDMI_CSC_CFG_INTMODE_DISABLE = 0x00,
-
-	/* csc_scale field values */
-	HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK = 0xf0,
-	HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP = 0x00,
-	HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP = 0x50,
-	HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP = 0x60,
-	HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP = 0x70,
-	HDMI_CSC_SCALE_CSCSCALE_MASK = 0x03,
-
-	/* i2cm filed values */
-	HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
-	HDMI_I2CM_SEGADDR_DDC = 0x30,
-	HDMI_I2CM_OPT_RD8_EXT = 0x8,
-	HDMI_I2CM_OPT_RD8 = 0x4,
-	HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
-	HDMI_I2CM_DIV_FAST_MODE = 0x8,
-	HDMI_I2CM_DIV_STD_MODE = 0x0,
-	HDMI_I2CM_SOFTRSTZ = 0x1,
-};
-
-/*
-struct display_timing;
-struct rk3288_grf;
-
-int rk_hdmi_init(struct rk3288_grf *grf, u32 vop_id);
-int rk_hdmi_enable(const struct display_timing *edid);
-int rk_hdmi_get_edid(struct rk3288_grf *grf, struct display_timing *edid);
-*/
-
-#endif

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index aeecb5815b..bc02f800dc 100644
@@ -20,7 +20,6 @@
 #include <asm/arch/cru_rk3288.h>
 #include <asm/arch/grf_rk3288.h>
 #include <asm/arch/edp_rk3288.h>
-#include <asm/arch/hdmi_rk3288.h>
 #include <asm/arch/vop_rk3288.h>
 #include <dm/device-internal.h>
 #include <dm/uclass-internal.h>

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index b64f310b8b..93803addfb 100644
@@ -157,52 +157,6 @@ struct sunxi_de_be_reg {
 	u32 output_color_coef[12];	/* 0x9d0 */
 };
 
-struct sunxi_lcdc_reg {
-	u32 ctrl;			/* 0x00 */
-	u32 int0;			/* 0x04 */
-	u32 int1;			/* 0x08 */
-	u8 res0[0x04];			/* 0x0c */
-	u32 tcon0_frm_ctrl;		/* 0x10 */
-	u32 tcon0_frm_seed[6];		/* 0x14 */
-	u32 tcon0_frm_table[4];		/* 0x2c */
-	u8 res1[4];			/* 0x3c */
-	u32 tcon0_ctrl;			/* 0x40 */
-	u32 tcon0_dclk;			/* 0x44 */
-	u32 tcon0_timing_active;	/* 0x48 */
-	u32 tcon0_timing_h;		/* 0x4c */
-	u32 tcon0_timing_v;		/* 0x50 */
-	u32 tcon0_timing_sync;		/* 0x54 */
-	u32 tcon0_hv_intf;		/* 0x58 */
-	u8 res2[0x04];			/* 0x5c */
-	u32 tcon0_cpu_intf;		/* 0x60 */
-	u32 tcon0_cpu_wr_dat;		/* 0x64 */
-	u32 tcon0_cpu_rd_dat0;		/* 0x68 */
-	u32 tcon0_cpu_rd_dat1;		/* 0x6c */
-	u32 tcon0_ttl_timing0;		/* 0x70 */
-	u32 tcon0_ttl_timing1;		/* 0x74 */
-	u32 tcon0_ttl_timing2;		/* 0x78 */
-	u32 tcon0_ttl_timing3;		/* 0x7c */
-	u32 tcon0_ttl_timing4;		/* 0x80 */
-	u32 tcon0_lvds_intf;		/* 0x84 */
-	u32 tcon0_io_polarity;		/* 0x88 */
-	u32 tcon0_io_tristate;		/* 0x8c */
-	u32 tcon1_ctrl;			/* 0x90 */
-	u32 tcon1_timing_source;	/* 0x94 */
-	u32 tcon1_timing_scale;		/* 0x98 */
-	u32 tcon1_timing_out;		/* 0x9c */
-	u32 tcon1_timing_h;		/* 0xa0 */
-	u32 tcon1_timing_v;		/* 0xa4 */
-	u32 tcon1_timing_sync;		/* 0xa8 */
-	u8 res3[0x44];			/* 0xac */
-	u32 tcon1_io_polarity;		/* 0xf0 */
-	u32 tcon1_io_tristate;		/* 0xf4 */
-	u8 res4[0x108];			/* 0xf8 */
-	u32 mux_ctrl;			/* 0x200 */
-	u8 res5[0x1c];			/* 0x204 */
-	u32 lvds_ana0;			/* 0x220 */
-	u32 lvds_ana1;			/* 0x224 */
-};
-
 struct sunxi_hdmi_reg {
 	u32 version_id;			/* 0x000 */
 	u32 ctrl;			/* 0x004 */

@@ -347,63 +301,6 @@ struct sunxi_tve_reg {
 #define SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE	1
 
 /*
- * LCDC register constants.
- */
-#define SUNXI_LCDC_X(x)				(((x) - 1) << 16)
-#define SUNXI_LCDC_Y(y)				(((y) - 1) << 0)
-#define SUNXI_LCDC_TCON_VSYNC_MASK		(1 << 24)
-#define SUNXI_LCDC_TCON_HSYNC_MASK		(1 << 25)
-#define SUNXI_LCDC_CTRL_IO_MAP_MASK		(1 << 0)
-#define SUNXI_LCDC_CTRL_IO_MAP_TCON0		(0 << 0)
-#define SUNXI_LCDC_CTRL_IO_MAP_TCON1		(1 << 0)
-#define SUNXI_LCDC_CTRL_TCON_ENABLE		(1 << 31)
-#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666	((1 << 31) | (0 << 4))
-#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565	((1 << 31) | (5 << 4))
-#define SUNXI_LCDC_TCON0_FRM_SEED		0x11111111
-#define SUNXI_LCDC_TCON0_FRM_TAB0		0x01010000
-#define SUNXI_LCDC_TCON0_FRM_TAB1		0x15151111
-#define SUNXI_LCDC_TCON0_FRM_TAB2		0x57575555
-#define SUNXI_LCDC_TCON0_FRM_TAB3		0x7f7f7777
-#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n)	(((n) & 0x1f) << 4)
-#define SUNXI_LCDC_TCON0_CTRL_ENABLE		(1 << 31)
-#define SUNXI_LCDC_TCON0_DCLK_DIV(n)		((n) << 0)
-#define SUNXI_LCDC_TCON0_DCLK_ENABLE		(0xf << 28)
-#define SUNXI_LCDC_TCON0_TIMING_H_BP(n)		(((n) - 1) << 0)
-#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n)	(((n) - 1) << 16)
-#define SUNXI_LCDC_TCON0_TIMING_V_BP(n)		(((n) - 1) << 0)
-#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n)	(((n) * 2) << 16)
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0	(1 << 20)
-#else
-#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0	0 /* NA */
-#endif
-#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n)	((n) << 26)
-#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE	(1 << 31)
-#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x)	((x) << 28)
-#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n)	(((n) & 0x1f) << 4)
-#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE	(1 << 20)
-#define SUNXI_LCDC_TCON1_CTRL_ENABLE		(1 << 31)
-#define SUNXI_LCDC_TCON1_TIMING_H_BP(n)		(((n) - 1) << 0)
-#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n)	(((n) - 1) << 16)
-#define SUNXI_LCDC_TCON1_TIMING_V_BP(n)		(((n) - 1) << 0)
-#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n)	((n) << 16)
-#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK		(0xf << 0)
-#define SUNXI_LCDC_MUX_CTRL_SRC0(x)		((x) << 0)
-#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK		(0xf << 4)
-#define SUNXI_LCDC_MUX_CTRL_SRC1(x)		((x) << 4)
-#ifdef CONFIG_SUNXI_GEN_SUN6I
-#define SUNXI_LCDC_LVDS_ANA0			0x40040320
-#define SUNXI_LCDC_LVDS_ANA0_EN_MB		(1 << 31)
-#define SUNXI_LCDC_LVDS_ANA0_DRVC		(1 << 24)
-#define SUNXI_LCDC_LVDS_ANA0_DRVD(x)		((x) << 20)
-#else
-#define SUNXI_LCDC_LVDS_ANA0			0x3f310000
-#define SUNXI_LCDC_LVDS_ANA0_UPDATE		(1 << 22)
-#endif
-#define SUNXI_LCDC_LVDS_ANA1_INIT1		(0x1f << 26 | 0x1f << 10)
-#define SUNXI_LCDC_LVDS_ANA1_INIT2		(0x1f << 16 | 0x1f << 00)
-
-/*
  * HDMI register constants.
  */
 #define SUNXI_HDMI_X(x)				(((x) - 1) << 0)

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index e4c8c160ed..a751698b4f 100644
@@ -10,7 +10,7 @@
 #ifndef _LCDC_H
 #define _LCDC_H
 
-struct ctfb_res_modes;
+#include <fdtdec.h>
 
 struct sunxi_lcdc_reg {
 	u32 ctrl;			/* 0x00 */

@@ -118,11 +118,11 @@ struct sunxi_lcdc_reg {
 void lcdc_init(struct sunxi_lcdc_reg * const lcdc);
 void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth);
 void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
-			 const struct ctfb_res_modes *mode,
+			 const struct display_timing *mode,
 			 int clk_div, bool for_ext_vga_dac,
 			 int depth, int dclk_phase);
 void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
-			 const struct ctfb_res_modes *mode,
+			 const struct display_timing *mode,
 			 bool ext_hvsync, bool is_composite);
 
 #endif /* _LCDC_H */

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index 48192ef87e..92c9d06054 100644
@@ -721,12 +721,40 @@ static void sunxi_lcdc_backlight_enable(void)
 		gpio_direction_output(pin, PWM_ON);
 }
 
+static void sunxi_ctfb_mode_to_display_timing(const struct ctfb_res_modes *mode,
+					      struct display_timing *timing)
+{
+	timing->pixelclock.typ = mode->pixclock_khz * 1000;
+
+	timing->hactive.typ = mode->xres;
+	timing->hfront_porch.typ = mode->right_margin;
+	timing->hback_porch.typ = mode->left_margin;
+	timing->hsync_len.typ = mode->hsync_len;
+
+	timing->vactive.typ = mode->yres;
+	timing->vfront_porch.typ = mode->lower_margin;
+	timing->vback_porch.typ = mode->upper_margin;
+	timing->vsync_len.typ = mode->vsync_len;
+
+	if (mode->sync & FB_SYNC_HOR_HIGH_ACT)
+		timing->flags |= DISPLAY_FLAGS_HSYNC_HIGH;
+	else
+		timing->flags |= DISPLAY_FLAGS_HSYNC_LOW;
+	if (mode->sync & FB_SYNC_VERT_HIGH_ACT)
+		timing->flags |= DISPLAY_FLAGS_VSYNC_HIGH;
+	else
+		timing->flags |= DISPLAY_FLAGS_VSYNC_LOW;
+	if (mode->vmode == FB_VMODE_INTERLACED)
+		timing->flags |= DISPLAY_FLAGS_INTERLACED;
+}
+
 static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
 				      bool for_ext_vga_dac)
 {
 	struct sunxi_lcdc_reg * const lcdc =
 		(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
 	int clk_div, clk_double, pin;
+	struct display_timing timing;
 
 #if defined CONFIG_MACH_SUN8I && defined CONFIG_VIDEO_LCD_IF_LVDS
 	for (pin = SUNXI_GPD(18); pin <= SUNXI_GPD(27); pin++) {

@@ -746,7 +774,8 @@ static void sunxi_lcdc_tcon0_mode_set(const struct ctfb_res_modes *mode,
 
 	sunxi_lcdc_pll_set(0, mode->pixclock_khz, &clk_div, &clk_double);
 
-	lcdc_tcon0_mode_set(lcdc, mode, clk_div, for_ext_vga_dac,
+	sunxi_ctfb_mode_to_display_timing(mode, &timing);
+	lcdc_tcon0_mode_set(lcdc, &timing, clk_div, for_ext_vga_dac,
 			    sunxi_display.depth, CONFIG_VIDEO_LCD_DCLK_PHASE);
 }
 

@@ -757,8 +786,10 @@ static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode,
 {
 	struct sunxi_lcdc_reg * const lcdc =
 		(struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE;
+	struct display_timing timing;
 
-	lcdc_tcon1_mode_set(lcdc, mode, use_portd_hvsync,
+	sunxi_ctfb_mode_to_display_timing(mode, &timing);
+	lcdc_tcon1_mode_set(lcdc, &timing, use_portd_hvsync,
 			    sunxi_is_composite());
 
 	if (use_portd_hvsync) {

index 1aefd5a64c..a44ea77576 100644
@@ -67,13 +67,22 @@ struct sunxi_ccm_reg {
 	u32 dram_pll_cfg;	/* 0xf8 PLL_DDR cfg register, A33 only */
 	u32 mbus_reset;		/* 0xfc MBUS reset control, A33 only */
 	u32 dram_clk_gate;	/* 0x100 DRAM module gating */
+#ifdef CONFIG_SUNXI_DE2
+	u32 de_clk_cfg;		/* 0x104 DE module clock */
+#else
 	u32 be0_clk_cfg;	/* 0x104 BE0 module clock */
+#endif
 	u32 be1_clk_cfg;	/* 0x108 BE1 module clock */
 	u32 fe0_clk_cfg;	/* 0x10c FE0 module clock */
 	u32 fe1_clk_cfg;	/* 0x110 FE1 module clock */
 	u32 mp_clk_cfg;		/* 0x114 MP module clock */
+#ifdef CONFIG_SUNXI_DE2
+	u32 lcd0_clk_cfg;	/* 0x118 LCD0 module clock */
+	u32 lcd1_clk_cfg;	/* 0x11c LCD1 module clock */
+#else
 	u32 lcd0_ch0_clk_cfg;	/* 0x118 LCD0 CH0 module clock */
 	u32 lcd1_ch0_clk_cfg;	/* 0x11c LCD1 CH0 module clock */
+#endif
 	u32 reserved14[3];
 	u32 lcd0_ch1_clk_cfg;	/* 0x12c LCD0 CH1 module clock */
 	u32 lcd1_ch1_clk_cfg;	/* 0x130 LCD1 CH1 module clock */

@@ -85,7 +94,11 @@ struct sunxi_ccm_reg {
 	u32 dmic_clk_cfg;	/* 0x148 Digital Mic module clock*/
 	u32 reserved15;
 	u32 hdmi_clk_cfg;	/* 0x150 HDMI module clock */
+#ifdef CONFIG_SUNXI_DE2
+	u32 hdmi_slow_clk_cfg;	/* 0x154 HDMI slow module clock */
+#else
 	u32 ps_clk_cfg;		/* 0x154 PS module clock */
+#endif
 	u32 mtc_clk_cfg;	/* 0x158 MTC module clock */
 	u32 mbus0_clk_cfg;	/* 0x15c MBUS0 module clock */
 	u32 mbus1_clk_cfg;	/* 0x160 MBUS1 module clock */

@@ -193,6 +206,7 @@ struct sunxi_ccm_reg {
 #define CCM_PLL3_CTRL_N_MASK		(0x7f << CCM_PLL3_CTRL_N_SHIFT)
 #define CCM_PLL3_CTRL_N(n)		((((n) - 1) & 0x7f) << 8)
 #define CCM_PLL3_CTRL_INTEGER_MODE	(0x1 << 24)
+#define CCM_PLL3_CTRL_LOCK		(0x1 << 28)
 #define CCM_PLL3_CTRL_EN		(0x1 << 31)
 
 #define CCM_PLL5_CTRL_M(n)		((((n) - 1) & 0x3) << 0)

@@ -222,6 +236,16 @@ struct sunxi_ccm_reg {
 #define CCM_MIPI_PLL_CTRL_LDO_EN	(0x3 << 22)
 #define CCM_MIPI_PLL_CTRL_EN		(0x1 << 31)
 
+#define CCM_PLL10_CTRL_M_SHIFT		0
+#define CCM_PLL10_CTRL_M_MASK		(0xf << CCM_PLL10_CTRL_M_SHIFT)
+#define CCM_PLL10_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+#define CCM_PLL10_CTRL_N_SHIFT		8
+#define CCM_PLL10_CTRL_N_MASK		(0x7f << CCM_PLL10_CTRL_N_SHIFT)
+#define CCM_PLL10_CTRL_N(n)		((((n) - 1) & 0x7f) << 8)
+#define CCM_PLL10_CTRL_INTEGER_MODE	(0x1 << 24)
+#define CCM_PLL10_CTRL_LOCK		(0x1 << 28)
+#define CCM_PLL10_CTRL_EN		(0x1 << 31)
+
 #define CCM_PLL11_CTRL_N(n)		((((n) - 1) & 0x3f) << 8)
 #define CCM_PLL11_CTRL_SIGMA_DELTA_EN	(0x1 << 24)
 #define CCM_PLL11_CTRL_UPD		(0x1 << 30)

@@ -273,9 +297,15 @@ struct sunxi_ccm_reg {
 #define AHB_GATE_OFFSET_DRC0		25
 #define AHB_GATE_OFFSET_DE_FE0		14
 #define AHB_GATE_OFFSET_DE_BE0		12
+#define AHB_GATE_OFFSET_DE		12
 #define AHB_GATE_OFFSET_HDMI		11
+#ifndef CONFIG_SUNXI_DE2
 #define AHB_GATE_OFFSET_LCD1		5
 #define AHB_GATE_OFFSET_LCD0		4
+#else
+#define AHB_GATE_OFFSET_LCD1		4
+#define AHB_GATE_OFFSET_LCD0		3
+#endif
 
 #define CCM_MMC_CTRL_M(x)		((x) - 1)
 #define CCM_MMC_CTRL_OCLK_DLY(x)	((x) << 8)

@@ -357,6 +387,12 @@ struct sunxi_ccm_reg {
 #define CCM_LCD_CH1_CTRL_PLL7_2X	(3 << 24)
 #define CCM_LCD_CH1_CTRL_GATE		(0x1 << 31)
 
+#define CCM_LCD0_CTRL_GATE		(0x1 << 31)
+#define CCM_LCD0_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+
+#define CCM_LCD1_CTRL_GATE		(0x1 << 31)
+#define CCM_LCD1_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+
 #define CCM_HDMI_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
 #define CCM_HDMI_CTRL_PLL_MASK		(3 << 24)
 #define CCM_HDMI_CTRL_PLL3		(0 << 24)

@@ -366,6 +402,8 @@ struct sunxi_ccm_reg {
 #define CCM_HDMI_CTRL_DDC_GATE		(0x1 << 30)
 #define CCM_HDMI_CTRL_GATE		(0x1 << 31)
 
+#define CCM_HDMI_SLOW_CTRL_DDC_GATE	(1 << 31)
+
 #if defined(CONFIG_MACH_SUN50I)
 #define MBUS_CLK_DEFAULT		0x81000002 /* PLL6x2 / 3 */
 #elif defined(CONFIG_MACH_SUN8I)

@@ -393,9 +431,16 @@ struct sunxi_ccm_reg {
 #define AHB_RESET_OFFSET_DRC0		25
 #define AHB_RESET_OFFSET_DE_FE0		14
 #define AHB_RESET_OFFSET_DE_BE0		12
+#define AHB_RESET_OFFSET_DE		12
 #define AHB_RESET_OFFSET_HDMI		11
+#define AHB_RESET_OFFSET_HDMI2		10
+#ifndef CONFIG_SUNXI_DE2
 #define AHB_RESET_OFFSET_LCD1		5
 #define AHB_RESET_OFFSET_LCD0		4
+#else
+#define AHB_RESET_OFFSET_LCD1		4
+#define AHB_RESET_OFFSET_LCD0		3
+#endif
 
 /* ahb_reset2 offsets */
 #define AHB_RESET_OFFSET_EPHY		2

@@ -418,6 +463,13 @@ struct sunxi_ccm_reg {
 #define CCM_DE_CTRL_PLL10		(5 << 24)
 #define CCM_DE_CTRL_GATE		(1 << 31)
 
+/* CCM bits common to all Display Engine 2.0 clock ctrl regs */
+#define CCM_DE2_CTRL_M(n)		((((n) - 1) & 0xf) << 0)
+#define CCM_DE2_CTRL_PLL_MASK		(3 << 24)
+#define CCM_DE2_CTRL_PLL6_2X		(0 << 24)
+#define CCM_DE2_CTRL_PLL10		(1 << 24)
+#define CCM_DE2_CTRL_GATE		(0x1 << 31)
+
 /* CCU security switch, H3 only */
 #define CCM_SEC_SWITCH_MBUS_NONSEC	(1 << 2)
 #define CCM_SEC_SWITCH_BUS_NONSEC	(1 << 1)

@@ -426,7 +478,9 @@ struct sunxi_ccm_reg {
 #ifndef __ASSEMBLY__
 void clock_set_pll1(unsigned int hz);
 void clock_set_pll3(unsigned int hz);
+void clock_set_pll3_factors(int m, int n);
 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
+void clock_set_pll10(unsigned int hz);
 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable);
 void clock_set_mipi_pll(unsigned int hz);
 unsigned int clock_get_pll3(void);

index 3c8c53fcf7..7a59f4cd74 100644
@@ -35,7 +35,7 @@ void clock_init_safe(void)
 	clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
 #endif
 
-#ifdef CONFIG_MACH_SUN8I_R40
+#if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
 	/* Set PLL lock enable bits and switch to old lock mode */
 	writel(GENMASK(12, 0), &ccm->pll_lock_ctrl);
 #endif

@@ -150,6 +150,22 @@ void clock_set_pll3(unsigned int clk)
 	       &ccm->pll3_cfg);
 }
 
+#ifdef CONFIG_SUNXI_DE2
+void clock_set_pll3_factors(int m, int n)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	/* PLL3 rate = 24000000 * n / m */
+	writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
+	       CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m),
+	       &ccm->pll3_cfg);
+
+	while (!(readl(&ccm->pll3_cfg) & CCM_PLL3_CTRL_LOCK))
+		;
+}
+#endif
+
 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
 {
 	struct sunxi_ccm_reg * const ccm =

@@ -222,6 +238,28 @@ done:
 }
 #endif
 
+#ifdef CONFIG_SUNXI_DE2
+void clock_set_pll10(unsigned int clk)
+{
+	struct sunxi_ccm_reg * const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	const int m = 2; /* 12 MHz steps */
+
+	if (clk == 0) {
+		clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN);
+		return;
+	}
+
+	/* PLL10 rate = 24000000 * n / m */
+	writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE |
+	       CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m),
+	       &ccm->pll10_cfg);
+
+	while (!(readl(&ccm->pll10_cfg) & CCM_PLL10_CTRL_LOCK))
+		;
+}
+#endif
+
 #if defined(CONFIG_MACH_SUN8I_A33) || defined(CONFIG_MACH_SUN50I)
 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
 {

index 8c8fb2e4ee..7d215b713e 100644
@@ -74,9 +74,11 @@ void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc,
 {
 	int bp, clk_delay, total, val;
 
+#ifndef CONFIG_SUNXI_DE2
 	/* Use tcon0 */
 	clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 			SUNXI_LCDC_CTRL_IO_MAP_TCON0);
+#endif
 
 	clk_delay = lcdc_get_clk_delay(mode, 0);
 	writel(SUNXI_LCDC_TCON0_CTRL_ENABLE |

@@ -149,9 +151,11 @@ void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc,
 {
 	int bp, clk_delay, total, val, yres;
 
+#ifndef CONFIG_SUNXI_DE2
 	/* Use tcon1 */
 	clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK,
 			SUNXI_LCDC_CTRL_IO_MAP_TCON1);
+#endif
 
 	clk_delay = lcdc_get_clk_delay(mode, 1);
 	writel(SUNXI_LCDC_TCON1_CTRL_ENABLE |

index 1b7bfb6c22..146f7f4e1b 100644
@@ -21,6 +21,8 @@
 #define GICD_BASE		0x1c81000
 #define GICC_BASE		0x1c82000
 
+#define CONFIG_SUNXI_DE2
+
 /*
  * Include common sunxi configuration where most the settings are
  */

index a4c3fb69e4..c42b901107 100644
@@ -25,6 +25,10 @@
 	#define CONFIG_SUNXI_USB_PHYS	2
 #endif
 
+#ifdef CONFIG_MACH_SUNXI_H3_H5
+#define CONFIG_SUNXI_DE2
+#endif
+
 /*
  * Include common sunxi configuration where most the settings are
  */

index ea672fe844..3ce46d024e 100644
@@ -18,6 +18,8 @@
 #define SUNXI_SRAM_D_BASE		0x00010000	/* 4 kiB */
 #define SUNXI_SRAM_B_BASE		0x00020000	/* 64 kiB (secure) */
 
+#define SUNXI_DE2_BASE			0x01000000
+
 #ifdef CONFIG_MACH_SUN8I_A83T
 #define SUNXI_CPUCFG_BASE		0x01700000
 #endif

@@ -46,7 +48,9 @@
 #define SUNXI_USB1_BASE			0x01c14000
 #endif
 #define SUNXI_SS_BASE			0x01c15000
+#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
 #define SUNXI_HDMI_BASE			0x01c16000
+#endif
 #define SUNXI_SPI2_BASE			0x01c17000
 #define SUNXI_SATA_BASE			0x01c18000
 #ifdef CONFIG_SUNXI_GEN_SUN4I

@@ -164,6 +168,10 @@ defined(CONFIG_MACH_SUN50I)
 #define SUNXI_MP_BASE			0x01e80000
 #define SUNXI_AVG_BASE			0x01ea0000
 
+#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
+#define SUNXI_HDMI_BASE			0x01ee0000
+#endif
+
 #define SUNXI_RTC_BASE			0x01f00000
 #define SUNXI_PRCM_BASE			0x01f01400
 

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index 5c9657ad13..936eda5c9b 100644
@@ -463,6 +463,11 @@ extern int soft_i2c_gpio_scl;
 #define CONSOLE_STDOUT_SETTINGS \
 	"stdout=serial,vga\0" \
 	"stderr=serial,vga\0"
+#elif CONFIG_DM_VIDEO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONSOLE_STDOUT_SETTINGS \
+	"stdout=serial,vidconsole\0" \
+	"stderr=serial,vidconsole\0"
 #else
 #define CONSOLE_STDOUT_SETTINGS \
 	"stdout=serial\0" \

index 7c57f02792..0ac64a97cf 100644
@@ -36,7 +36,7 @@ int pmic_bus_init(void)
 	if (!needs_init)
 		return 0;
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	p2wi_init();
 	ret = p2wi_change_to_p2wi_mode(AXP221_CHIP_ADDR, AXP221_CTRL_ADDR,

@@ -62,7 +62,7 @@ int pmic_bus_read(u8 reg, u8 *data)
 	return i2c_read(AXP152_I2C_ADDR, reg, 1, data, 1);
 #elif defined CONFIG_AXP209_POWER
 	return i2c_read(AXP209_I2C_ADDR, reg, 1, data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	return p2wi_read(reg, data);
 # else

@@ -77,7 +77,7 @@ int pmic_bus_write(u8 reg, u8 data)
 	return i2c_write(AXP152_I2C_ADDR, reg, 1, &data, 1);
 #elif defined CONFIG_AXP209_POWER
 	return i2c_write(AXP209_I2C_ADDR, reg, 1, &data, 1);
-#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
+#elif defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 # ifdef CONFIG_MACH_SUN6I
 	return p2wi_write(reg, data);
 # else

index 6fd11f1529..28d05e962a 100644
@@ -20,7 +20,7 @@ static int rsb_set_device_mode(void);
 
 static void rsb_cfg_io(void)
 {
-#ifdef CONFIG_MACH_SUN8I
+#if defined CONFIG_MACH_SUN8I || defined CONFIG_MACH_SUN50I
 	sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_GPL_R_RSB);
 	sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_GPL_R_RSB);
 	sunxi_gpio_set_pull(SUNXI_GPL(0), 1);

index b9660128e5..75e53bebbd 100644
@@ -487,26 +487,27 @@ void sunxi_board_init(void)
 #endif
 
 #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
-	defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
-	defined CONFIG_AXP818_POWER
+	defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \
+	defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 	power_failed = axp_init();
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
-	defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \
+	defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
 #endif
 	power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
 	power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
-#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
+#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP803_POWER) && \
+	!defined(CONFIG_AXP818_POWER)
 	power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
 #endif
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
-	defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \
+	defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
 #endif
 
-#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
-	defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP803_POWER || \
+	defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
 #endif
 	power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);

@@ -517,8 +518,8 @@ void sunxi_board_init(void)
 	power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
 #endif
 
-#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
-	defined(CONFIG_AXP818_POWER)
+#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP803_POWER) || \
+	defined(CONFIG_AXP809_POWER) || defined(CONFIG_AXP818_POWER)
 	power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
 	power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
 #if !defined CONFIG_AXP809_POWER

@@ -530,13 +531,17 @@ void sunxi_board_init(void)
 	power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
 #endif
 
-#ifdef CONFIG_AXP818_POWER
+#if defined CONFIG_AXP803_POWER || defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
 	power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
+#endif
+
+#ifdef CONFIG_AXP818_POWER
 	power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
 #endif
 
-#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
+#if defined CONFIG_AXP803_POWER || defined CONFIG_AXP809_POWER || \
+	defined CONFIG_AXP818_POWER
 	power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
 #endif
 #endif

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index af4d7a6903..ad0c330ca5 100644
@@ -162,7 +162,7 @@ int axp_set_dldo(int dldo_num, unsigned int mvolt)
 	cfg = axp818_mvolt_to_cfg(mvolt, 700, 3300, 100);
 	if (dldo_num == 2 && mvolt > 3300)
 		cfg += 1 + axp818_mvolt_to_cfg(mvolt, 3400, 4200, 200);
-	ret = pmic_bus_write(AXP818_ELDO1_CTRL + (dldo_num - 1), cfg);
+	ret = pmic_bus_write(AXP818_DLDO1_CTRL + (dldo_num - 1), cfg);
 	if (ret)
 		return ret;
 

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index d789ad8086..8cb4d5763c 100644
@@ -16,6 +16,9 @@
 #ifdef CONFIG_AXP221_POWER
 #include <axp221.h>
 #endif
+#ifdef CONFIG_AXP803_POWER
+#include <axp803.h>
+#endif
 #ifdef CONFIG_AXP809_POWER
 #include <axp809.h>
 #endif