Update designware pwm driver
Subsystems (2)
v3 cover Update designware pwm driver
From: Xuyang Dong <[email protected]>
There is already a patch [1] for the DesignWare PWM driver, which is posted by Ben and still under review. Based on this patch, this series is a continuation of [1] to add support for IP versions 2.11a and later, which includes support for "Pulse Width Modulation with 0% and 100% Duty Cycle".
Supported chips:
ESWIN EIC7700 series SoC.
Test:
Tested this patch on the Sifive HiFive Premier P550 (which uses the EIC7700 SoC).
[1] https://lore.kernel.org/lkml/[email protected]/
Updates:
Change in v3:
- YAML:
- Added a clear justification for the optional resets property. It is required to support proper controller initialization when no PWM channel is active at boot time, while allowing the driver to skip reset deassertion if any channel is already enabled.
- Driver:
- Update the boundary value check of tmp in __dwc_pwm_configure_timer() for DWC_TIM_CTRL_0N100PWM_EN.
- Replace 'sizeof(struct dwc_pwm_drvdata)' with 'struct_size(data, chips, 1)'.
- Drop devm_clk_get_enabled() in favor of devm_clk_get() with explicit clk_prepare_enable() and clk_disable_unprepare() allowing runtime PM to manage clock state.
- Replace devm_reset_control_get_optional_exclusive_deasserted() with devm_reset_control_get_optional_exclusive() and issue a full reset via reset_control_reset() only when no PWM channel is active at probe time.
- Detect bootloader-enabled PWM channels by reading the enable bit, and initialize runtime PM as active for those channels by calling pm_runtime_set_active() and pm_runtime_get_noresume().
- Remove autosuspend as it is not required for this driver.
- Use explicit pm_runtime_enable() and pm_runtime_disable() instead of the managed devm_pm_runtime_enable() variant to ensure correct cleanup.
- On device removal, recheck the channel enable status. If any channel remains active, call pm_runtime_put_noidle() before disabling clocks via clk_disable_unprepare().
Resume device before register access during removal if it is runtime suspended, and re-suspend it afterward.
- If device is suspended, resume it before register access during system resume/suspend.
- Use pm_ptr() instead of pm_sleep_ptr() for correct PM operation.
- Link to v2: https://lore.kernel.org/all/[email protected]/
Change in v2:
- YAML:
- Remove eswin,eic7700-pwm.yaml. Use snps,dw-apb-timers-pwm2.yaml. The description in snps,dw-apb-timers-pwm2.yaml is better.
- Add the resets property as optional, as defined in the databook.
- Remove snps,pwm-full-range-enable as no additional property is needed.
- Driver:
- Change the file from pwm-dwc-eic7700.c to pwm-dwc-of.c from [1].
- Define DWC_TIM_VERSION_ID_2_11A 2.11a as the baseline version.
- Enable the 0% and 100% duty cycle mode by setting dwc->feature if the version read from the TIMERS_COMP_VERSION register is later than or equal to DWC_TIM_VERSION_ID_2_11A.
- Use the DIV_ROUND_UP_ULL() to calculate width in the .apply and .get_state.
- Additionally, Power Management (PM) support has been added to the pwm-dwc-of.c driver.
- Drop the headers that are not used.
- Use devm_clk_get_enabled() instead of devm_clk_get().
- Drop of_match_ptr.
- Fix build error with 1ULL << 32.
- Link to v1: https://lore.kernel.org/all/[email protected]/
- Link to v9: https://lore.kernel.org/lkml/[email protected]/
Xuyang Dong (2):
dt-bindings: pwm: dwc: add reset optional
pwm: dwc: add of/platform support
.../bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 3 + drivers/pwm/Kconfig | 10 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-dwc-core.c | 101 ++++-- drivers/pwm/pwm-dwc-of.c | 331 ++++++++++++++++++ drivers/pwm/pwm-dwc.h | 25 +- 6 files changed, 442 insertions(+), 29 deletions(-) create mode 100644 drivers/pwm/pwm-dwc-of.c
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2.34.1
PATCH v3 1/2 dt-bindings: pwm: dwc: add reset optional
From: Xuyang Dong <[email protected]>
The DesignWare PWM controller provides separate reset signals for each clock domain, as specified in the hardware documentation. Without asserting and deasserting these resets during probe, PWM outputs may remain in an undefined state after system reboot.
To address this, the driver now supports an optional 'resets' property. A full reset is performed only when no PWM channel is enabled, as determined by reading the enable bit in each channel's control register. This allows safe coexistence with bootloaders that have already configured active PWM channels.
--- .../devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml | 3 +++ 1 file changed, 3 insertions(+)
Documentation/devicetree/bindings/pwm/snps,dw-apb-timers-pwm2.yaml +3 -0
@@ -43,6 +43,9 @@ properties: - const: bus - const: timer + resets: + maxItems: 1 + snps,pwm-number: $ref: /schemas/types.yaml#/definitions/uint32 description: The number of PWM channels configured for this instance
Signature · 1 line
2.34.1
Re: [PATCH v3 1/2] dt-bindings: pwm: dwc: add reset optional
Quoted 3 lines · On Thu, Apr 02, 2026 at 05:18:54PM +0800, [email protected] wrote:
From: Xuyang Dong <[email protected]>
The DesignWare PWM controller provides separate reset signals for each
So one controller has signals. Plural, right? Then why do you define only one reset signal?
Quoted 5 lines
clock domain, as specified in the hardware documentation. Without asserting and deasserting these resets during probe, PWM outputs may remain in an undefined state after system reboot.
To address this, the driver now supports an optional 'resets' property.
This is binding change, not driver.
Quoted 2 lines
A full reset is performed only when no PWM channel is enabled, as determined by reading the enable bit in each channel's control register.
Do you describe hardware or driver behavior? This is not a change about driver. Describe the hardware here - what is expected with that reset.
Quoted 2 lines
This allows safe coexistence with bootloaders that have already configured active PWM channels.
Best regards,
Krzysztof
Re: Re: [PATCH v3 1/2] dt-bindings: pwm: dwc: add reset optional
Quoted 6 lines
Quoted 2 lines
The DesignWare PWM controller provides separate reset signals for each
So one controller has signals. Plural, right? Then why do you define only one reset signal?
Hi Krzysztof,
There are two reset signals matching the two clocks, so maxItems is set to 2.
Quoted 6 lines
Quoted 5 lines
clock domain, as specified in the hardware documentation. Without asserting and deasserting these resets during probe, PWM outputs may remain in an undefined state after system reboot.
To address this, the driver now supports an optional 'resets' property.
Quoted 11 lines
This is binding change, not driver.
Quoted 2 lines
A full reset is performed only when no PWM channel is enabled, as determined by reading the enable bit in each channel's control register.
Do you describe hardware or driver behavior? This is not a change about driver. Describe the hardware here - what is expected with that reset.
Quoted 2 lines
This allows safe coexistence with bootloaders that have already configured active PWM channels.
The improvement commit message for the next version will be revised as follows:
The DesignWare PWM includes separate reset signals dedicated to each clock domain:
The presetn signal resets logic in pclk domain.
The timer_N_resetn signal resets logic in the timer_N_clk domain. The resets are active-low.
In the next version, we will address the changes as described above.
Best regards,
Xuyang Dong
PATCH v3 2/2 pwm: dwc: add of/platform support
In reply to [email protected]From: Xuyang Dong <[email protected]>
The dwc pwm controller can be used in non-PCI systems, so allow either platform or OF based probing.
The controller is reset only when no PWM channel is enabled. Otherwise, clocks are enabled and the runtime PM state is updated to reflect the active hardware configuration.
--- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-dwc-core.c | 101 ++++++++--- drivers/pwm/pwm-dwc-of.c | 331 +++++++++++++++++++++++++++++++++++++ drivers/pwm/pwm-dwc.h | 25 ++- 5 files changed, 439 insertions(+), 29 deletions(-) create mode 100644 drivers/pwm/pwm-dwc-of.c
drivers/pwm/Kconfig +10 -0
@@ -249,6 +249,16 @@ config PWM_DWC To compile this driver as a module, choose M here: the module will be called pwm-dwc. +config PWM_DWC_OF + tristate "DesignWare PWM Controller (OF bus)" + depends on HAS_IOMEM && (OF || COMPILE_TEST) + select PWM_DWC_CORE + help + PWM driver for Synopsys DWC PWM Controller on an OF bus or + a platform bus. + To compile this driver as a module, choose M here: the module + will be called pwm-dwc-of. + config PWM_EP93XX tristate "Cirrus Logic EP93xx PWM support" depends on ARCH_EP93XX || COMPILE_TEST
drivers/pwm/Makefile +1 -0
@@ -20,6 +20,7 @@ obj-$(CONFIG_PWM_CRC) += pwm-crc.o obj-$(CONFIG_PWM_CROS_EC) += pwm-cros-ec.o obj-$(CONFIG_PWM_DWC_CORE) += pwm-dwc-core.o obj-$(CONFIG_PWM_DWC) += pwm-dwc.o +obj-$(CONFIG_PWM_DWC_OF) += pwm-dwc-of.o obj-$(CONFIG_PWM_EP93XX) += pwm-ep93xx.o obj-$(CONFIG_PWM_FSL_FTM) += pwm-fsl-ftm.o obj-$(CONFIG_PWM_GPIO) += pwm-gpio.o
drivers/pwm/pwm-dwc-core.c +79 -22
153 lines not on this page · raw message
drivers/pwm/pwm-dwc-of.c new file +331 -0
331 lines not on this page · raw message
drivers/pwm/pwm-dwc.h +18 -7
@@ -26,12 +26,19 @@ MODULE_IMPORT_NS("dwc_pwm");#define DWC_TIMERS_TOTAL 8/* Timer Control Register */ -#define DWC_TIM_CTRL_EN BIT(0) -#define DWC_TIM_CTRL_MODE BIT(1) -#define DWC_TIM_CTRL_MODE_FREE (0 << 1) -#define DWC_TIM_CTRL_MODE_USER (1 << 1) -#define DWC_TIM_CTRL_INT_MASK BIT(2) -#define DWC_TIM_CTRL_PWM BIT(3) +#define DWC_TIM_CTRL_EN BIT(0) +#define DWC_TIM_CTRL_MODE BIT(1) +#define DWC_TIM_CTRL_MODE_FREE (0 << 1) +#define DWC_TIM_CTRL_MODE_USER BIT(1) +#define DWC_TIM_CTRL_INT_MASK BIT(2) +#define DWC_TIM_CTRL_PWM BIT(3) +#define DWC_TIM_CTRL_0N100PWM_EN BIT(4) + +/* +* The version 2.11a and later add "Pulse Width Modulation with +* 0% and 100% Duty Cycle". +*/ +#define DWC_TIM_VERSION_ID_2_11A 0x3231312astruct dwc_pwm_info {unsigned int nr;
@@ -52,8 +59,12 @@ struct dwc_pwm_ctx {struct dwc_pwm {void __iomem *base; -unsigned int clk_ns; +struct clk *bus_clk; +struct clk *clk; +unsigned long clk_rate; +struct reset_control *rst;struct dwc_pwm_ctx ctx[DWC_TIMERS_TOTAL ]; +u32 features; };static inline struct dwc_pwm *to_dwc_pwm (struct pwm_chip *chip)
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2.34.1