Build and support rk3036 SoC platform
Subsystems (6)
v6 cover Build and support rk3036 SoC platform
Hi,
We need to support rk3036 soc platform via upstream, there are
some primary parts for the initial release of minimum system: dts, clk-pll, smp, and clock tree for rk3036, and additional, we can use these startup and run to init processs.
Thanks.
Changed in v6:
- add hardware timer in dtsi and some the aliases of basic modules
Changed in v5:
- don't use clk_ APIs in the pll init-callback
Changed in v4:
- add some basic IP modules on rk3036.dtsi
- optimized supporting smp codes
Changed in v3:
- optimized some codes based on v2
- removed the patch "initial set time for rtc-hym8563" (useless)
- removed the patch "pinctrl" (approved)
Changed in v2:
- based on v1, add clock controller documentation
- enable timer5 startup
- add smp for cpu1
- initial set time for rtc-hym8563
Changes in v1:
- add dts, pinctrl and clock tree for rk3036 soc platform
The patchset (8):
8) rockchip: make sure timer5 is enabled on rk3036 platforms
7) ARM: dts: enable smp for rk3036
6) ARM: rockchip: add support smp for rk3036
5) ARM: dts: rockchip: add core rk3036 dts
4) clk: rockchip: add clock controller for rk3036
3) clk: rockchip: add new pll-type for rk3036 and similar socs
2) clk: rockchip: add dt-binding header for rk3036
1) dt-bindings: add documentation of rk3036 clock controller
Changes in v6:
Signed-off-by Xing Zheng <[email protected]>
Reviewed-by Heiko Stuebner <[email protected]>
Heiko Stuebner (1):
ARM: rockchip: add support smp for rk3036
Xing Zheng (7):
dt-bindings: add documentation of rk3036 clock controller
clk: rockchip: add dt-binding header for rk3036
clk: rockchip: add new pll-type for rk3036 and similar socs
clk: rockchip: add clock controller for rk3036
ARM: dts: rockchip: add core rk3036 dts
ARM: dts: enable smp for rk3036
rockchip: make sure timer5 is enabled on rk3036 platforms
Documentation/devicetree/bindings/arm/cpus.txt | 1 + .../bindings/clock/rockchip,rk3036-cru.txt | 56 ++ arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3036-evb.dts | 64 +++ arch/arm/boot/dts/rk3036.dtsi | 552 ++++++++++++++++++++ arch/arm/mach-rockchip/platsmp.c | 45 +- arch/arm/mach-rockchip/rockchip.c | 44 +- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-pll.c | 249 ++++++++- drivers/clk/rockchip/clk-rk3036.c | 478 +++++++++++++++++ drivers/clk/rockchip/clk.h | 32 +- include/dt-bindings/clock/rk3036-cru.h | 193 +++++++ 12 files changed, 1685 insertions(+), 31 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt create mode 100644 arch/arm/boot/dts/rk3036-evb.dts create mode 100644 arch/arm/boot/dts/rk3036.dtsi create mode 100644 drivers/clk/rockchip/clk-rk3036.c create mode 100644 include/dt-bindings/clock/rk3036-cru.h
Signature · 1 line
1.7.9.5
PATCH v6 1/8 dt-bindings: add documentation of rk3036 clock controller
Add the devicetree binding for the cru on the rk3036 which quite similar structured as previous clock controllers.
Signed-off-by Xing Zheng <[email protected]>
Reviewed-by Heiko Stuebner <[email protected]>
---
Changes in v6: None
.../bindings/clock/rockchip,rk3036-cru.txt | 56 ++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt
Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt new file +56 -0
@@ -0,0 +1,56 @@ +* Rockchip RK3036 Clock and Reset Unit + +The RK3036 clock controller generates and supplies clock to various +controllers within the SoC and also implements a reset controller for SoC +peripherals. + +Required Properties: + +- compatible: should be "rockchip,rk3036-cru" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Optional Properties: + +- rockchip,grf: phandle to the syscon managing the "general register files" + If missing pll rates are not changeable, due to the missing pll lock status. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be +used in device tree sources. Similar macros exist for the reset sources in +these files. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "xin24m" - crystal input - required, + - "ext_i2s" - external I2S clock - optional, + - "ext_gmac" - external GMAC clock - optional + +Example: Clock controller node: + + cru: cru at 20000000 { + compatible = "rockchip,rk3036-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial at 20060000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20060000 0x100>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART0>; + };
Signature · 1 line
1.7.9.5
Heiko Stuebner
maintainerRe: [PATCH v6 1/8] dt-bindings: add documentation of rk3036 clock controller
Hi,
Am Mittwoch, 4. November 2015, 20:18:16 schrieb Xing Zheng:
Quoted 6 lines
Add the devicetree binding for the cru on the rk3036 which quite similar structured as previous clock controllers.
Signed-off-by Xing Zheng <[email protected]>Reviewed-by Heiko Stuebner <[email protected]>---
your recipient-list is missing the clock maintainers+lists - sorry for not noticing this earlier.
While the devicetree-maintainers may Review it, we expect the clock- maintainers to actually apply all 4 clock-related patches.
Same comment is true for
[PATCH v6 2/8] clk: rockchip: add dt-binding header for rk3036
Heiko
Quoted 70 lines
Changes in v6: None
.../bindings/clock/rockchip,rk3036-cru.txt | 56 ++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txtDocumentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt new file +56
-0@@ -0,0 +1,56 @@ +* Rockchip RK3036 Clock and Reset Unit + +The RK3036 clock controller generates and supplies clock to various +controllers within the SoC and also implements a reset controller for SoC +peripherals. + +Required Properties: + +- compatible: should be "rockchip,rk3036-cru" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Optional Properties: + +- rockchip,grf: phandle to the syscon managing the "general register files" + If missing pll rates are not changeable, due to the missing pll lock status. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be +used in device tree sources. Similar macros exist for the reset sources in +these files. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "xin24m" - crystal input - required, + - "ext_i2s" - external I2S clock - optional, + - "ext_gmac" - external GMAC clock - optional + +Example: Clock controller node: + + cru: cru at 20000000 { + compatible = "rockchip,rk3036-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial at 20060000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20060000 0x100>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART0>; + };
Re: [PATCH v6 1/8] dt-bindings: add documentation of rk3036 clock controller
Quoted 12 lines · Heiko Stuebner
Hi,
Am Mittwoch, 4. November 2015, 20:18:16 schrieb Xing Zheng:
Quoted 6 lines
Add the devicetree binding for the cru on the rk3036 which quite similar structured as previous clock controllers.
Signed-off-by Xing Zheng<[email protected]>Reviewed-by Heiko Stuebner<[email protected]>---
your recipient-list is missing the clock maintainers+lists - sorry for not noticing this earlier.
Quoted 9 lines
While the devicetree-maintainers may Review it, we expect the clock- maintainers to actually apply all 4 clock-related patches.
Same comment is true for
[PATCH v6 2/8] clk: rockchip: add dt-binding header for rk3036Heiko
Sorry, and I will loop them in the next versioin.
Thanks.
Re: [PATCH v6 1/8] dt-bindings: add documentation of rk3036 clock controller
In reply to Xing ZhengQuoted 5 lines · Xing Zheng
Add the devicetree binding for the cru on the rk3036 which quite similar structured as previous clock controllers.
Signed-off-by Xing Zheng <[email protected]>Reviewed-by Heiko Stuebner <[email protected]>
Acked-by Rob Herring <[email protected]>
Quoted 74 lines
---
Changes in v6: None
.../bindings/clock/rockchip,rk3036-cru.txt | 56 ++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3036-cru.txtDocumentation/devicetree/bindings/clock/rockchip,rk3036-cru.txt new file +56
-0@@ -0,0 +1,56 @@ +* Rockchip RK3036 Clock and Reset Unit + +The RK3036 clock controller generates and supplies clock to various +controllers within the SoC and also implements a reset controller for SoC +peripherals. + +Required Properties: + +- compatible: should be "rockchip,rk3036-cru" +- reg: physical base address of the controller and length of memory mapped + region. +- #clock-cells: should be 1. +- #reset-cells: should be 1. + +Optional Properties: + +- rockchip,grf: phandle to the syscon managing the "general register files" + If missing pll rates are not changeable, due to the missing pll lock status. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/rk3036-cru.h headers and can be +used in device tree sources. Similar macros exist for the reset sources in +these files. + +External clocks: + +There are several clocks that are generated outside the SoC. It is expected +that they are defined using standard clock bindings with following +clock-output-names: + - "xin24m" - crystal input - required, + - "ext_i2s" - external I2S clock - optional, + - "ext_gmac" - external GMAC clock - optional + +Example: Clock controller node: + + cru: cru at 20000000 { + compatible = "rockchip,rk3036-cru"; + reg = <0x20000000 0x1000>; + rockchip,grf = <&grf>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart0: serial at 20060000 { + compatible = "snps,dw-apb-uart"; + reg = <0x20060000 0x100>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&cru SCLK_UART0>; + };Signature · 1 line
1.7.9.5
PATCH v6 2/8 clk: rockchip: add dt-binding header for rk3036
In reply to Xing ZhengAdd the dt-bindings header for the rk3036, that gets shared between the clock controller and the clock references in the dts.
Signed-off-by Xing Zheng <[email protected]>
Reviewed-by Heiko Stuebner <[email protected]>
---
Changes in v6: None
include/dt-bindings/clock/rk3036-cru.h | 193 ++++++++++++++++++++++++++++++++ 1 file changed, 193 insertions(+) create mode 100644 include/dt-bindings/clock/rk3036-cru.h
include/dt-bindings/clock/rk3036-cru.h new file +193 -0
@@ -0,0 +1,193 @@ +/* +* Copyright (c) 2015 Rockchip Electronics Co. Ltd. +* Author: Xing Zheng <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +*/ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3036_H + +/* core clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_GPLL 3 +#define ARMCLK 4 + +/* sclk gates (special clocks) */ +#define SCLK_GPU 64 +#define SCLK_SPI 65 +#define SCLK_SDMMC 68 +#define SCLK_SDIO 69 +#define SCLK_EMMC 71 +#define SCLK_NANDC 76 +#define SCLK_UART0 77 +#define SCLK_UART1 78 +#define SCLK_UART2 79 +#define SCLK_I2S 82 +#define SCLK_SPDIF 83 +#define SCLK_TIMER0 85 +#define SCLK_TIMER1 86 +#define SCLK_TIMER2 87 +#define SCLK_TIMER3 88 +#define SCLK_OTGPHY0 93 +#define SCLK_LCDC 100 +#define SCLK_HDMI 109 +#define SCLK_HEVC 111 +#define SCLK_I2S_OUT 113 +#define SCLK_SDMMC_DRV 114 +#define SCLK_SDIO_DRV 115 +#define SCLK_EMMC_DRV 117 +#define SCLK_SDMMC_SAMPLE 118 +#define SCLK_SDIO_SAMPLE 119 +#define SCLK_EMMC_SAMPLE 121 +#define SCLK_PVTM_CORE 123 +#define SCLK_PVTM_GPU 124 +#define SCLK_PVTM_VIDEO 125 +#define SCLK_MAC 151 +#define SCLK_MACREF 152 +#define SCLK_SFC 160 + +/* aclk gates */ +#define ACLK_DMAC2 194 +#define ACLK_LCDC 197 +#define ACLK_VIO 203 +#define ACLK_VCODEC 208 +#define ACLK_CPU 209 +#define ACLK_PERI 210 + +/* pclk gates */ +#define PCLK_GPIO0 320 +#define PCLK_GPIO1 321 +#define PCLK_GPIO2 322 +#define PCLK_GRF 329 +#define PCLK_I2C0 332 +#define PCLK_I2C1 333 +#define PCLK_I2C2 334 +#define PCLK_SPI 338 +#define PCLK_UART0 341 +#define PCLK_UART1 342 +#define PCLK_UART2 343 +#define PCLK_PWM 350 +#define PCLK_TIMER 353 +#define PCLK_HDMI 360 +#define PCLK_CPU 362 +#define PCLK_PERI 363 +#define PCLK_DDRUPCTL 364 +#define PCLK_WDT 368 +#define PCLK_ACODEC 369 + +/* hclk gates */ +#define HCLK_OTG0 449 +#define HCLK_OTG1 450 +#define HCLK_NANDC 453 +#define HCLK_SDMMC 456 +#define HCLK_SDIO 457 +#define HCLK_EMMC 459 +#define HCLK_I2S 462 +#define HCLK_LCDC 465 +#define HCLK_ROM 467 +#define HCLK_VIO_BUS 472 +#define HCLK_VCODEC 476 +#define HCLK_CPU 477 +#define HCLK_PERI 478 + +#define CLK_NR_CLKS (HCLK_PERI + 1) + +/* soft-reset indices */ +#define SRST_CORE0 0 +#define SRST_CORE1 1 +#define SRST_CORE0_DBG 4 +#define SRST_CORE1_DBG 5 +#define SRST_CORE0_POR 8 +#define SRST_CORE1_POR 9 +#define SRST_L2C 12 +#define SRST_TOPDBG 13 +#define SRST_STRC_SYS_A 14 +#define SRST_PD_CORE_NIU 15 + +#define SRST_TIMER2 16 +#define SRST_CPUSYS_H 17 +#define SRST_AHB2APB_H 19 +#define SRST_TIMER3 20 +#define SRST_INTMEM 21 +#define SRST_ROM 22 +#define SRST_PERI_NIU 23 +#define SRST_I2S 24 +#define SRST_DDR_PLL 25 +#define SRST_GPU_DLL 26 +#define SRST_TIMER0 27 +#define SRST_TIMER1 28 +#define SRST_CORE_DLL 29 +#define SRST_EFUSE_P 30 +#define SRST_ACODEC_P 31 + +#define SRST_GPIO0 32 +#define SRST_GPIO1 33 +#define SRST_GPIO2 34 +#define SRST_UART0 39 +#define SRST_UART1 40 +#define SRST_UART2 41 +#define SRST_I2C0 43 +#define SRST_I2C1 44 +#define SRST_I2C2 45 +#define SRST_SFC 47 + +#define SRST_PWM0 48 +#define SRST_DAP 51 +#define SRST_DAP_SYS 52 +#define SRST_GRF 55 +#define SRST_PERIPHSYS_A 57 +#define SRST_PERIPHSYS_H 58 +#define SRST_PERIPHSYS_P 59 +#define SRST_CPU_PERI 61 +#define SRST_EMEM_PERI 62 +#define SRST_USB_PERI 63 + +#define SRST_DMA2 64 +#define SRST_MAC 66 +#define SRST_NANDC 68 +#define SRST_USBOTG0 69 +#define SRST_OTGC0 71 +#define SRST_USBOTG1 72 +#define SRST_OTGC1 74 +#define SRST_DDRMSCH 79 + +#define SRST_MMC0 81 +#define SRST_SDIO 82 +#define SRST_EMMC 83 +#define SRST_SPI0 84 +#define SRST_WDT 86 +#define SRST_DDRPHY 88 +#define SRST_DDRPHY_P 89 +#define SRST_DDRCTRL 90 +#define SRST_DDRCTRL_P 91 + +#define SRST_HDMI_P 96 +#define SRST_VIO_BUS_H 99 +#define SRST_UTMI0 103 +#define SRST_UTMI1 104 +#define SRST_USBPOR 105 + +#define SRST_VCODEC_A 112 +#define SRST_VCODEC_H 113 +#define SRST_VIO1_A 114 +#define SRST_HEVC 115 +#define SRST_VCODEC_NIU_A 116 +#define SRST_LCDC1_A 117 +#define SRST_LCDC1_H 118 +#define SRST_LCDC1_D 119 +#define SRST_GPU 120 +#define SRST_GPU_NIU_A 122 + +#define SRST_DBG_P 131 + +#endif
Signature · 1 line
1.7.9.5
PATCH v6 3/8 clk: rockchip: add new pll-type for rk3036 and similar socs
In reply to Xing ZhengThe rk3036's pll and clock are different with base on the rk3066(rk3188, rk3288, rk3368 use it), there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3066s.
Signed-off-by Xing Zheng <[email protected]>
Reviewed-by Heiko Stuebner <[email protected]>
---
Changes in v6: None
drivers/clk/rockchip/clk-pll.c | 249 +++++++++++++++++++++++++++++++++++++++- drivers/clk/rockchip/clk.h | 32 +++++- 2 files changed, 279 insertions(+), 2 deletions(-)
drivers/clk/rockchip/clk-pll.c +248 -1
@@ -2,6 +2,9 @@* Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <[email protected]> * +* Copyright (c) 2015 Rockchip Electronics Co. Ltd. +* Author: Xing Zheng <[email protected]> +* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or
@@ -19,6 +22,7 @@#include <linux/delay.h> #include <linux/clk-provider.h> #include <linux/regmap.h> +#include <linux/clk.h> #include "clk.h" #define PLL_MODE_MASK 0x3
@@ -108,6 +112,243 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) }/** +* PLL used in RK3036 +*/ + +#define RK3036_PLLCON (i) (i * 0x4) +#define RK3036_PLLCON0_FBDIV_MASK 0xfff +#define RK3036_PLLCON0_FBDIV_SHIFT 0 +#define RK3036_PLLCON0_POSTDIV1_MASK 0x7 +#define RK3036_PLLCON0_POSTDIV1_SHIFT 12 +#define RK3036_PLLCON1_REFDIV_MASK 0x3f +#define RK3036_PLLCON1_REFDIV_SHIFT 0 +#define RK3036_PLLCON1_POSTDIV2_MASK 0x7 +#define RK3036_PLLCON1_POSTDIV2_SHIFT 6 +#define RK3036_PLLCON1_DSMPD_MASK 0x1 +#define RK3036_PLLCON1_DSMPD_SHIFT 12 +#define RK3036_PLLCON2_FRAC_MASK 0xffffff +#define RK3036_PLLCON2_FRAC_SHIFT 0 + +#define RK3036_PLLCON1_PWRDOWN (1 << 13) + +static void rockchip_rk3036_pll_get_params (struct rockchip_clk_pll *pll, +struct rockchip_pll_rate_table *rate) +{ +u32 pllcon; + + pllcon =readl_relaxed (pll->reg_base +RK3036_PLLCON (0 )); + rate->fbdiv = ((pllcon >>RK3036_PLLCON0_FBDIV_SHIFT ) &RK3036_PLLCON0_FBDIV_MASK ); + rate->postdiv1 = ((pllcon >>RK3036_PLLCON0_POSTDIV1_SHIFT ) &RK3036_PLLCON0_POSTDIV1_MASK ); + + pllcon =readl_relaxed (pll->reg_base +RK3036_PLLCON (1 )); + rate->refdiv = ((pllcon >>RK3036_PLLCON1_REFDIV_SHIFT ) &RK3036_PLLCON1_REFDIV_MASK ); + rate->postdiv2 = ((pllcon >>RK3036_PLLCON1_POSTDIV2_SHIFT ) &RK3036_PLLCON1_POSTDIV2_MASK ); + rate->dsmpd = ((pllcon >>RK3036_PLLCON1_DSMPD_SHIFT ) &RK3036_PLLCON1_DSMPD_MASK ); + + pllcon =readl_relaxed (pll->reg_base +RK3036_PLLCON (2 )); + rate->frac = ((pllcon >>RK3036_PLLCON2_FRAC_SHIFT ) &RK3036_PLLCON2_FRAC_MASK ); +} + +static unsigned long rockchip_rk3036_pll_recalc_rate (struct clk_hw *hw, +unsigned long prate) +{ +struct rockchip_clk_pll *pll =to_rockchip_clk_pll (hw); +struct rockchip_pll_rate_table cur; +u64 rate64 = prate; + +rockchip_rk3036_pll_get_params (pll, &cur); + + rate64 *= cur.fbdiv; +do_div (rate64, cur.refdiv); + +if (cur.dsmpd ==0 ) { +/* fractional mode */ +u64 frac_rate64 = prate * cur.frac; + +do_div (frac_rate64, cur.refdiv); + rate64 += frac_rate64 >>24 ; + } + +do_div (rate64, cur.postdiv1); +do_div (rate64, cur.postdiv2); + +return (unsigned long )rate64; +} + +static int rockchip_rk3036_pll_set_params (struct rockchip_clk_pll *pll, +const struct rockchip_pll_rate_table *rate) +{ +const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; +struct clk_mux *pll_mux = &pll->pll_mux; +struct rockchip_pll_rate_table cur; +u32 pllcon; +int rate_change_remuxed =0 ; +int cur_parent; +int ret; + +pr_debug ("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n" , + __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, + rate->postdiv2, rate->dsmpd, rate->frac); + +rockchip_rk3036_pll_get_params (pll, &cur); + cur.rate =0 ; + + cur_parent = pll_mux_ops->get_parent (&pll_mux->hw); +if (cur_parent ==PLL_MODE_NORM ) { + pll_mux_ops->set_parent (&pll_mux->hw,PLL_MODE_SLOW ); + rate_change_remuxed =1 ; + } + +/* update pll values */ +writel_relaxed (HIWORD_UPDATE (rate->fbdiv,RK3036_PLLCON0_FBDIV_MASK , +RK3036_PLLCON0_FBDIV_SHIFT ) | +HIWORD_UPDATE (rate->postdiv1,RK3036_PLLCON0_POSTDIV1_MASK , +RK3036_PLLCON0_POSTDIV1_SHIFT ), + pll->reg_base +RK3036_PLLCON (0 )); + +writel_relaxed (HIWORD_UPDATE (rate->refdiv,RK3036_PLLCON1_REFDIV_MASK , +RK3036_PLLCON1_REFDIV_SHIFT ) | +HIWORD_UPDATE (rate->postdiv2,RK3036_PLLCON1_POSTDIV2_MASK , +RK3036_PLLCON1_POSTDIV2_SHIFT ) | +HIWORD_UPDATE (rate->dsmpd,RK3036_PLLCON1_DSMPD_MASK , +RK3036_PLLCON1_DSMPD_SHIFT ), + pll->reg_base +RK3036_PLLCON (1 )); + +/* GPLL CON2 is not HIWORD_MASK */ + pllcon =readl_relaxed (pll->reg_base +RK3036_PLLCON (2 )); + pllcon &= ~(RK3036_PLLCON2_FRAC_MASK <<RK3036_PLLCON2_FRAC_SHIFT ); + pllcon |= rate->frac <<RK3036_PLLCON2_FRAC_SHIFT ; +writel_relaxed (pllcon, pll->reg_base +RK3036_PLLCON (2 )); + +/* wait for the pll to lock */ + ret =rockchip_pll_wait_lock (pll); +if (ret) { +pr_warn ("%s: pll update unsucessful, trying to restore old params\n" , + __func__); +rockchip_rk3036_pll_set_params (pll, &cur); + } + +if (rate_change_remuxed) + pll_mux_ops->set_parent (&pll_mux->hw,PLL_MODE_NORM ); + +return ret; +} + +static int rockchip_rk3036_pll_set_rate (struct clk_hw *hw,unsigned long drate, +unsigned long prate) +{ +struct rockchip_clk_pll *pll =to_rockchip_clk_pll (hw); +const struct rockchip_pll_rate_table *rate; +unsigned long old_rate =rockchip_rk3036_pll_recalc_rate (hw, prate); +struct regmap *grf =rockchip_clk_get_grf (); + +if (IS_ERR (grf)) { +pr_debug ("%s: grf regmap not available, aborting rate change\n" , + __func__); +return PTR_ERR (grf); + } + +pr_debug ("%s: changing %s from %lu to %lu with a parent rate of %lu\n" , + __func__,__clk_get_name (hw->clk), old_rate, drate, prate); + +/* Get required rate settings from table */ + rate =rockchip_get_pll_settings (pll, drate); +if (!rate) { +pr_err ("%s: Invalid rate : %lu for pll clk %s\n" , __func__, + drate,__clk_get_name (hw->clk)); +return -EINVAL ; + } + +return rockchip_rk3036_pll_set_params (pll, rate); +} + +static int rockchip_rk3036_pll_enable (struct clk_hw *hw) +{ +struct rockchip_clk_pll *pll =to_rockchip_clk_pll (hw); + +writel (HIWORD_UPDATE (0 ,RK3036_PLLCON1_PWRDOWN ,0 ), + pll->reg_base +RK3036_PLLCON (1 )); + +return 0 ; +} + +static void rockchip_rk3036_pll_disable (struct clk_hw *hw) +{ +struct rockchip_clk_pll *pll =to_rockchip_clk_pll (hw); + +writel (HIWORD_UPDATE (RK3036_PLLCON1_PWRDOWN , +RK3036_PLLCON1_PWRDOWN ,0 ), + pll->reg_base +RK3036_PLLCON (1 )); +} + +static int rockchip_rk3036_pll_is_enabled (struct clk_hw *hw) +{ +struct rockchip_clk_pll *pll =to_rockchip_clk_pll (hw); +u32 pllcon =readl (pll->reg_base +RK3036_PLLCON (1 )); + +return !(pllcon &RK3036_PLLCON1_PWRDOWN ); +} + +static void rockchip_rk3036_pll_init (struct clk_hw *hw) +{ +struct rockchip_clk_pll *pll =to_rockchip_clk_pll (hw); +const struct rockchip_pll_rate_table *rate; +struct rockchip_pll_rate_table cur; +unsigned long drate; + +if (!(pll->flags &ROCKCHIP_PLL_SYNC_RATE )) +return ; + + drate =clk_hw_get_rate (hw); + rate =rockchip_get_pll_settings (pll, drate); + +/* when no rate setting for the current rate, rely on clk_set_rate */ +if (!rate) +return ; + +rockchip_rk3036_pll_get_params (pll, &cur); + +pr_debug ("%s: pll %s@%lu: Hz\n" , __func__,__clk_get_name (hw->clk), drate); +pr_debug ("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n" , + cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, cur.dsmpd, cur.frac); +pr_debug ("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n" , + rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, rate->dsmpd, rate->frac); + +if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || + rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || + rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) { +struct clk *parent =clk_get_parent (hw->clk); + +if (!parent) { +pr_warn ("%s: parent of %s not available\n" , + __func__,__clk_get_name (hw->clk)); +return ; + } + +pr_debug ("%s: pll %s: rate params do not match rate table, adjusting\n" , + __func__,__clk_get_name (hw->clk)); +rockchip_rk3036_pll_set_params (pll, rate); + } +} + +static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = { + .recalc_rate = rockchip_rk3036_pll_recalc_rate, + .enable = rockchip_rk3036_pll_enable, + .disable = rockchip_rk3036_pll_disable, + .is_enabled = rockchip_rk3036_pll_is_enabled, +}; + +static const struct clk_ops rockchip_rk3036_pll_clk_ops = { + .recalc_rate = rockchip_rk3036_pll_recalc_rate, + .round_rate = rockchip_pll_round_rate, + .set_rate = rockchip_rk3036_pll_set_rate, + .enable = rockchip_rk3036_pll_enable, + .disable = rockchip_rk3036_pll_disable, + .is_enabled = rockchip_rk3036_pll_is_enabled, + .init = rockchip_rk3036_pll_init, +}; + +/** * PLL used in RK3066, RK3188 and RK3288 */
@@ -376,7 +617,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, pll_mux->lock = lock; pll_mux->hw.init = &init; -if (pll_type == pll_rk3066) +if (pll_type == pll_rk3036 || pll_type == pll_rk3066) pll_mux->flags |=CLK_MUX_HIWORD_MASK ;/* the actual muxing is xin24m, pll-output, xin32k */
@@ -421,6 +662,12 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, }switch (pll_type) { +case pll_rk3036: +if (!pll->rate_table) + init.ops = &rockchip_rk3036_pll_clk_norate_ops; +else + init.ops = &rockchip_rk3036_pll_clk_ops; +break ;case pll_rk3066:if (!pll->rate_table) init.ops = &rockchip_rk3066_pll_clk_norate_ops;
drivers/clk/rockchip/clk.h +31 -1
@@ -2,6 +2,9 @@* Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <[email protected]> * +* Copyright (c) 2015 Rockchip Electronics Co. Ltd. +* Author: Xing Zheng <[email protected]> +* * based on * * samsung/clk.h
@@ -30,7 +33,7 @@ struct clk;#define HIWORD_UPDATE (val, mask, shift) \ ((val) << (shift) | (mask) << ((shift) + 16)) -/* register positions shared by RK2928, RK3066 and RK3188 */ +/* register positions shared by RK2928, RK3036, RK3066 and RK3188 */ #define RK2928_PLL_CON (x) ((x) * 0x4)#define RK2928_MODE_CON 0x40#define RK2928_CLKSEL_CON (x) ((x) * 0x4 + 0x44)
@@ -40,6 +43,13 @@ struct clk;#define RK2928_SOFTRST_CON (x) ((x) * 0x4 + 0x110)#define RK2928_MISC_CON 0x134 +#define RK3036_SDMMC_CON0 0x144 +#define RK3036_SDMMC_CON1 0x148 +#define RK3036_SDIO_CON0 0x14c +#define RK3036_SDIO_CON1 0x150 +#define RK3036_EMMC_CON0 0x154 +#define RK3036_EMMC_CON1 0x158 +#define RK3288_PLL_CON (x) RK2928_PLL_CON(x)#define RK3288_MODE_CON 0x50#define RK3288_CLKSEL_CON (x) ((x) * 0x4 + 0x60)
@@ -74,9 +84,22 @@ struct clk;#define RK3368_EMMC_CON1 0x41cenum rockchip_pll_type { + pll_rk3036, pll_rk3066, }; +#define RK3036_PLL_RATE (_rate, _refdiv, _fbdiv, _postdiv1, \ + _postdiv2, _dsmpd, _frac) \ +{ \ + .rate = _rate##U, \ + .fbdiv = _fbdiv, \ + .postdiv1 = _postdiv1, \ + .refdiv = _refdiv, \ + .postdiv2 = _postdiv2, \ + .dsmpd = _dsmpd, \ + .frac = _frac, \ +} +#define RK3066_PLL_RATE (_rate, _nr, _nf, _no) \ { \ .rate = _rate##U, \
@@ -101,6 +124,13 @@ struct rockchip_pll_rate_table {unsigned int nf;unsigned int no;unsigned int nb; +/* for RK3036 */ +unsigned int fbdiv; +unsigned int postdiv1; +unsigned int refdiv; +unsigned int postdiv2; +unsigned int dsmpd; +unsigned int frac; };/**
Signature · 1 line
1.7.9.5
Heiko Stuebner
maintainerPATCH 3/8 clk: rockchip: add new pll-type for rk3036 and similar socs
The rk3036's pll and clock are different with base on the rk3066(rk3188, rk3288, rk3368 use it), there are different adjust foctors and control registers, so these should be independent and separate from the series of rk3066s.
Signed-off-by Xing Zheng <[email protected]>
Reviewed-by Heiko Stuebner <[email protected]>
---
Hi,
it looks like I described the change in a slightly wrong way on what should move in which patch. I took the liberty in fixing that up and moving the RK3036_EMMC_* etc defines to the clock-controller patch.
Like I said, this patch should add everything related to the new pll-type and the other patch than everything for the rk3036 clock controller.
Heiko
drivers/clk/rockchip/clk-pll.c | 249 ++++++++++++++++++++++++++++++++++++++++- drivers/clk/rockchip/clk.h | 23 ++++ 2 files changed, 271 insertions(+), 1 deletion(-)
drivers/clk/rockchip/clk-pll.c +248 -1
@@ -2,6 +2,9 @@* Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <[email protected]> * +* Copyright (c) 2015 Rockchip Electronics Co. Ltd. +* Author: Xing Zheng <[email protected]> +* * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or
@@ -19,6 +22,7 @@#include <linux/delay.h> #include <linux/clk-provider.h> #include <linux/regmap.h> +#include <linux/clk.h> #include "clk.h" #define PLL_MODE_MASK 0x3
@@ -108,6 +112,243 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll) }/** +* PLL used in RK3036 +*/ + +#define RK3036_PLLCON (i) (i * 0x4) +#define RK3036_PLLCON0_FBDIV_MASK 0xfff +#define RK3036_PLLCON0_FBDIV_SHIFT 0 +#define RK3036_PLLCON0_POSTDIV1_MASK 0x7 +#define RK3036_PLLCON0_POSTDIV1_SHIFT 12 +#define RK3036_PLLCON1_REFDIV_MASK 0x3f +#define RK3036_PLLCON1_REFDIV_SHIFT 0 +#define RK3036_PLLCON1_POSTDIV2_MASK 0x7 +#define RK3036_PLLCON1_POSTDIV2_SHIFT 6 +#define RK3036_PLLCON1_DSMPD_MASK 0x1 +#define RK3036_PLLCON1_DSMPD_SHIFT 12 +#define RK3036_PLLCON2_FRAC_MASK 0xffffff +#define RK3036_PLLCON2_FRAC_SHIFT 0 + +#define RK3036_PLLCON1_PWRDOWN (1 << 13) + +static void rockchip_rk3036_pll_get_params (struct rockchip_clk_pll *pll, +struct rockchip_pll_rate_table *rate) +{ +u32 pllcon; + + pllcon =readl_relaxed (pll->reg_base +RK3036_PLLCON (0 )); + rate->fbdiv = ((pllcon >>RK3036_PLLCON0_FBDIV_SHIFT ) &RK3036_PLLCON0_FBDIV_MASK ); + rate->postdiv1 = ((pllcon >>RK3036_PLLCON0_POSTDIV1_SHIFT ) &RK3036_PLLCON0_POSTDIV1_MASK ); + + pllcon =readl_relaxed (pll->reg_base +RK3036_PLLCON (1 )); + rate->refdiv = ((pllcon >>RK3036_PLLCON1_REFDIV_SHIFT ) &RK3036_PLLCON1_REFDIV_MASK ); + rate->postdiv2 = ((pllcon >>RK3036_PLLCON1_POSTDIV2_SHIFT ) &RK3036_PLLCON1_POSTDIV2_MASK ); + rate->dsmpd = ((pllcon >>RK3036_PLLCON1_DSMPD_SHIFT ) &RK3036_PLLCON1_DSMPD_MASK ); + + pllcon =readl_relaxed (pll->reg_base +RK3036_PLLCON (2 )); + rate->frac = ((pllcon >>RK3036_PLLCON2_FRAC_SHIFT ) &RK3036_PLLCON2_FRAC_MASK ); +} + +static unsigned long rockchip_rk3036_pll_recalc_rate (struct clk_hw *hw, +unsigned long prate) +{ +struct rockchip_clk_pll *pll =to_rockchip_clk_pll (hw); +struct rockchip_pll_rate_table cur; +u64 rate64 = prate; + +rockchip_rk3036_pll_get_params (pll, &cur); + + rate64 *= cur.fbdiv; +do_div (rate64, cur.refdiv); + +if (cur.dsmpd ==0 ) { +/* fractional mode */ +u64 frac_rate64 = prate * cur.frac; + +do_div (frac_rate64, cur.refdiv); + rate64 += frac_rate64 >>24 ; + } + +do_div (rate64, cur.postdiv1); +do_div (rate64, cur.postdiv2); + +return (unsigned long )rate64; +} + +static int rockchip_rk3036_pll_set_params (struct rockchip_clk_pll *pll, +const struct rockchip_pll_rate_table *rate) +{ +const struct clk_ops *pll_mux_ops = pll->pll_mux_ops; +struct clk_mux *pll_mux = &pll->pll_mux; +struct rockchip_pll_rate_table cur; +u32 pllcon; +int rate_change_remuxed =0 ; +int cur_parent; +int ret; + +pr_debug ("%s: rate settings for %lu fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n" , + __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, + rate->postdiv2, rate->dsmpd, rate->frac); + +rockchip_rk3036_pll_get_params (pll, &cur); + cur.rate =0 ; + + cur_parent = pll_mux_ops->get_parent (&pll_mux->hw); +if (cur_parent ==PLL_MODE_NORM ) { + pll_mux_ops->set_parent (&pll_mux->hw,PLL_MODE_SLOW ); + rate_change_remuxed =1 ; + } + +/* update pll values */ +writel_relaxed (HIWORD_UPDATE (rate->fbdiv,RK3036_PLLCON0_FBDIV_MASK , +RK3036_PLLCON0_FBDIV_SHIFT ) | +HIWORD_UPDATE (rate->postdiv1,RK3036_PLLCON0_POSTDIV1_MASK , +RK3036_PLLCON0_POSTDIV1_SHIFT ), + pll->reg_base +RK3036_PLLCON (0 )); + +writel_relaxed (HIWORD_UPDATE (rate->refdiv,RK3036_PLLCON1_REFDIV_MASK , +RK3036_PLLCON1_REFDIV_SHIFT ) | +HIWORD_UPDATE (rate->postdiv2,RK3036_PLLCON1_POSTDIV2_MASK , +RK3036_PLLCON1_POSTDIV2_SHIFT ) | +HIWORD_UPDATE (rate->dsmpd,RK3036_PLLCON1_DSMPD_MASK , +RK3036_PLLCON1_DSMPD_SHIFT ), + pll->reg_base +RK3036_PLLCON (1 )); + +/* GPLL CON2 is not HIWORD_MASK */ + pllcon =readl_relaxed (pll->reg_base +RK3036_PLLCON (2 )); + pllcon &= ~(RK3036_PLLCON2_FRAC_MASK <<RK3036_PLLCON2_FRAC_SHIFT ); + pllcon |= rate->frac <<RK3036_PLLCON2_FRAC_SHIFT ; +writel_relaxed (pllcon, pll->reg_base +RK3036_PLLCON (2 )); + +/* wait for the pll to lock */ + ret =rockchip_pll_wait_lock (pll); +if (ret) { +pr_warn ("%s: pll update unsucessful, trying to restore old params\n" , + __func__); +rockchip_rk3036_pll_set_params (pll, &cur); + } + +if (rate_change_remuxed) + pll_mux_ops->set_parent (&pll_mux->hw,PLL_MODE_NORM ); + +return ret; +} + +static int rockchip_rk3036_pll_set_rate (struct clk_hw *hw,unsigned long drate, +unsigned long prate) +{ +struct rockchip_clk_pll *pll =to_rockchip_clk_pll (hw); +const struct rockchip_pll_rate_table *rate; +unsigned long old_rate =rockchip_rk3036_pll_recalc_rate (hw, prate); +struct regmap *grf =rockchip_clk_get_grf (); + +if (IS_ERR (grf)) { +pr_debug ("%s: grf regmap not available, aborting rate change\n" , + __func__); +return PTR_ERR (grf); + } + +pr_debug ("%s: changing %s from %lu to %lu with a parent rate of %lu\n" , + __func__,__clk_get_name (hw->clk), old_rate, drate, prate); + +/* Get required rate settings from table */ + rate =rockchip_get_pll_settings (pll, drate); +if (!rate) { +pr_err ("%s: Invalid rate : %lu for pll clk %s\n" , __func__, + drate,__clk_get_name (hw->clk)); +return -EINVAL ; + } + +return rockchip_rk3036_pll_set_params (pll, rate); +} + +static int rockchip_rk3036_pll_enable (struct clk_hw *hw) +{ +struct rockchip_clk_pll *pll =to_rockchip_clk_pll (hw); + +writel (HIWORD_UPDATE (0 ,RK3036_PLLCON1_PWRDOWN ,0 ), + pll->reg_base +RK3036_PLLCON (1 )); + +return 0 ; +} + +static void rockchip_rk3036_pll_disable (struct clk_hw *hw) +{ +struct rockchip_clk_pll *pll =to_rockchip_clk_pll (hw); + +writel (HIWORD_UPDATE (RK3036_PLLCON1_PWRDOWN , +RK3036_PLLCON1_PWRDOWN ,0 ), + pll->reg_base +RK3036_PLLCON (1 )); +} + +static int rockchip_rk3036_pll_is_enabled (struct clk_hw *hw) +{ +struct rockchip_clk_pll *pll =to_rockchip_clk_pll (hw); +u32 pllcon =readl (pll->reg_base +RK3036_PLLCON (1 )); + +return !(pllcon &RK3036_PLLCON1_PWRDOWN ); +} + +static void rockchip_rk3036_pll_init (struct clk_hw *hw) +{ +struct rockchip_clk_pll *pll =to_rockchip_clk_pll (hw); +const struct rockchip_pll_rate_table *rate; +struct rockchip_pll_rate_table cur; +unsigned long drate; + +if (!(pll->flags &ROCKCHIP_PLL_SYNC_RATE )) +return ; + + drate =clk_hw_get_rate (hw); + rate =rockchip_get_pll_settings (pll, drate); + +/* when no rate setting for the current rate, rely on clk_set_rate */ +if (!rate) +return ; + +rockchip_rk3036_pll_get_params (pll, &cur); + +pr_debug ("%s: pll %s@%lu: Hz\n" , __func__,__clk_get_name (hw->clk), drate); +pr_debug ("old - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n" , + cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, cur.dsmpd, cur.frac); +pr_debug ("new - fbdiv: %d, postdiv1: %d, refdiv: %d, postdiv2: %d, dsmpd: %d, frac: %d\n" , + rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, rate->dsmpd, rate->frac); + +if (rate->fbdiv != cur.fbdiv || rate->postdiv1 != cur.postdiv1 || + rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || + rate->dsmpd != cur.dsmpd || rate->frac != cur.frac) { +struct clk *parent =clk_get_parent (hw->clk); + +if (!parent) { +pr_warn ("%s: parent of %s not available\n" , + __func__,__clk_get_name (hw->clk)); +return ; + } + +pr_debug ("%s: pll %s: rate params do not match rate table, adjusting\n" , + __func__,__clk_get_name (hw->clk)); +rockchip_rk3036_pll_set_params (pll, rate); + } +} + +static const struct clk_ops rockchip_rk3036_pll_clk_norate_ops = { + .recalc_rate = rockchip_rk3036_pll_recalc_rate, + .enable = rockchip_rk3036_pll_enable, + .disable = rockchip_rk3036_pll_disable, + .is_enabled = rockchip_rk3036_pll_is_enabled, +}; + +static const struct clk_ops rockchip_rk3036_pll_clk_ops = { + .recalc_rate = rockchip_rk3036_pll_recalc_rate, + .round_rate = rockchip_pll_round_rate, + .set_rate = rockchip_rk3036_pll_set_rate, + .enable = rockchip_rk3036_pll_enable, + .disable = rockchip_rk3036_pll_disable, + .is_enabled = rockchip_rk3036_pll_is_enabled, + .init = rockchip_rk3036_pll_init, +}; + +/** * PLL used in RK3066, RK3188 and RK3288 */
@@ -363,7 +604,7 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, pll_mux->lock = lock; pll_mux->hw.init = &init; -if (pll_type == pll_rk3066) +if (pll_type == pll_rk3036 || pll_type == pll_rk3066) pll_mux->flags |=CLK_MUX_HIWORD_MASK ;/* the actual muxing is xin24m, pll-output, xin32k */
@@ -408,6 +649,12 @@ struct clk *rockchip_clk_register_pll(enum rockchip_pll_type pll_type, }switch (pll_type) { +case pll_rk3036: +if (!pll->rate_table) + init.ops = &rockchip_rk3036_pll_clk_norate_ops; +else + init.ops = &rockchip_rk3036_pll_clk_ops; +break ;case pll_rk3066:if (!pll->rate_table) init.ops = &rockchip_rk3066_pll_clk_norate_ops;
drivers/clk/rockchip/clk.h +23 -0
@@ -2,6 +2,9 @@* Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner <[email protected]> * +* Copyright (c) 2015 Rockchip Electronics Co. Ltd. +* Author: Xing Zheng <[email protected]> +* * based on * * samsung/clk.h
@@ -74,9 +77,22 @@ struct clk;#define RK3368_EMMC_CON1 0x41cenum rockchip_pll_type { + pll_rk3036, pll_rk3066, }; +#define RK3036_PLL_RATE (_rate, _refdiv, _fbdiv, _postdiv1, \ + _postdiv2, _dsmpd, _frac) \ +{ \ + .rate = _rate##U, \ + .fbdiv = _fbdiv, \ + .postdiv1 = _postdiv1, \ + .refdiv = _refdiv, \ + .postdiv2 = _postdiv2, \ + .dsmpd = _dsmpd, \ + .frac = _frac, \ +} +#define RK3066_PLL_RATE (_rate, _nr, _nf, _no) \ { \ .rate = _rate##U, \
@@ -101,6 +117,13 @@ struct rockchip_pll_rate_table {unsigned int nf;unsigned int no;unsigned int nb; +/* for RK3036 */ +unsigned int fbdiv; +unsigned int postdiv1; +unsigned int refdiv; +unsigned int postdiv2; +unsigned int dsmpd; +unsigned int frac; };/**
Signature · 1 line
2.6.2
PATCH v6 4/8 clk: rockchip: add clock controller for rk3036
In reply to Xing ZhengAdd the clock tree definition for the new rk3036 SoC.
Signed-off-by Xing Zheng <[email protected]>
Reviewed-by Heiko Stuebner <[email protected]>
---
Changes in v6: None
drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-rk3036.c | 478 +++++++++++++++++++++++++++++++++++++ 2 files changed, 479 insertions(+) create mode 100644 drivers/clk/rockchip/clk-rk3036.c
drivers/clk/rockchip/Makefile +1 -0
@@ -10,6 +10,7 @@ obj-y += clk-inverter.o obj-y += clk-mmc-phase.o obj-$(CONFIG_RESET_CONTROLLER) += softrst.o +obj-y += clk-rk3036.o obj-y += clk-rk3188.o obj-y += clk-rk3288.o obj-y += clk-rk3368.o
drivers/clk/rockchip/clk-rk3036.c new file +478 -0
478 lines not on this page · raw message
Signature · 1 line
1.7.9.5
Heiko Stuebner
maintainerPATCH 4/8 clk: rockchip: add clock controller for rk3036
Add the clock tree definition for the new rk3036 SoC.
Signed-off-by Xing Zheng <[email protected]>
Reviewed-by Heiko Stuebner <[email protected]>
--- drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-rk3036.c | 478 ++++++++++++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.h | 9 +- 3 files changed, 487 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/rockchip/clk-rk3036.c
drivers/clk/rockchip/Makefile +1 -0
@@ -10,6 +10,7 @@ obj-y += clk-inverter.o obj-y += clk-mmc-phase.o obj-$(CONFIG_RESET_CONTROLLER) += softrst.o +obj-y += clk-rk3036.o obj-y += clk-rk3188.o obj-y += clk-rk3288.o obj-y += clk-rk3368.o
drivers/clk/rockchip/clk-rk3036.c new file +478 -0
478 lines not on this page · raw message
drivers/clk/rockchip/clk.h +8 -1
@@ -33,7 +33,7 @@ struct clk;#define HIWORD_UPDATE (val, mask, shift) \ ((val) << (shift) | (mask) << ((shift) + 16)) -/* register positions shared by RK2928, RK3066 and RK3188 */ +/* register positions shared by RK2928, RK3036, RK3066 and RK3188 */ #define RK2928_PLL_CON (x) ((x) * 0x4)#define RK2928_MODE_CON 0x40#define RK2928_CLKSEL_CON (x) ((x) * 0x4 + 0x44)
@@ -43,6 +43,13 @@ struct clk;#define RK2928_SOFTRST_CON (x) ((x) * 0x4 + 0x110)#define RK2928_MISC_CON 0x134 +#define RK3036_SDMMC_CON0 0x144 +#define RK3036_SDMMC_CON1 0x148 +#define RK3036_SDIO_CON0 0x14c +#define RK3036_SDIO_CON1 0x150 +#define RK3036_EMMC_CON0 0x154 +#define RK3036_EMMC_CON1 0x158 +#define RK3288_PLL_CON (x) RK2928_PLL_CON(x)#define RK3288_MODE_CON 0x50#define RK3288_CLKSEL_CON (x) ((x) * 0x4 + 0x60)
Signature · 1 line
2.6.2
PATCH v6 5/8 ARM: dts: rockchip: add core rk3036 dts
In reply to Xing ZhengInitial release for rk3036, node definitions rk3036 sdk board.
Signed-off-by Xing Zheng <[email protected]>
Reviewed-by Heiko Stuebner <[email protected]>
---
Changes in v6: None
arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/rk3036-evb.dts | 64 +++++ arch/arm/boot/dts/rk3036.dtsi | 547 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 612 insertions(+) create mode 100644 arch/arm/boot/dts/rk3036-evb.dts create mode 100644 arch/arm/boot/dts/rk3036.dtsi
arch/arm/boot/dts/Makefile +1 -0
@@ -512,6 +512,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ dtb-$(CONFIG_ARCH_REALVIEW) += \ arm-realview-pb1176.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ + rk3036-evb.dtb \ rk3066a-bqcurie2.dtb \ rk3066a-marsboard.dtb \ rk3066a-rayeager.dtb \
arch/arm/boot/dts/rk3036-evb.dts new file +64 -0
64 lines not on this page · raw message
arch/arm/boot/dts/rk3036.dtsi new file +547 -0
547 lines not on this page · raw message
Signature · 1 line
1.7.9.5
PATCH v6 6/8 ARM: rockchip: add support smp for rk3036
In reply to Xing ZhengFrom: Heiko Stuebner <[email protected]>
The dual-core Cortex A7 rk3036 is a bit special in that it does not allow to control the actual powerdomain of the cpu cores, while the rest of the smp-bringup like reset control and entry address handling stays the same. Its bigger sibling, the quad-core rk3128 again allows powerdomain control.
So allow that case by introducing a separate smp-enable-method, that simply disables powerdomain handling in the common code.
Signed-off-by Heiko Stuebner <[email protected]>
Tested-by Xing Zheng <[email protected]>
Signed-off-by Xing Zheng <[email protected]>
---
Changes in v6: None
Documentation/devicetree/bindings/arm/cpus.txt | 1 + arch/arm/mach-rockchip/platsmp.c | 45 +++++++++++++++++------- 2 files changed, 34 insertions(+), 12 deletions(-)
Documentation/devicetree/bindings/arm/cpus.txt +1 -0
@@ -200,6 +200,7 @@ nodes to be present and contain the properties described below. "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" + "rockchip,rk3036-smp" "rockchip,rk3066-smp" "ste,dbx500-smp"
arch/arm/mach-rockchip/platsmp.c +33 -12
89 lines not on this page · raw message
Signature · 1 line
1.7.9.5
Heiko Stuebner
maintainerRe: [PATCH v6 6/8] ARM: rockchip: add support smp for rk3036
Am Mittwoch, 4. November 2015, 20:25:16 schrieb Xing Zheng:
Quoted 7 lines
From: Heiko Stuebner <[email protected]>
The dual-core Cortex A7 rk3036 is a bit special in that it does not allow to control the actual powerdomain of the cpu cores, while the rest of the smp-bringup like reset control and entry address handling stays the same. Its bigger sibling, the quad-core rk3128 again allows powerdomain control.
Quoted 6 lines
So allow that case by introducing a separate smp-enable-method, that simply disables powerdomain handling in the common code.
Signed-off-by Heiko Stuebner <[email protected]>Tested-by Xing Zheng <[email protected]>Signed-off-by Xing Zheng <[email protected]>
This patch can work standalone, so I took the liberty of applying it to my soc branch for 4.5 already, so you don't need to resend it in future versions.
Re: [PATCH v6 6/8] ARM: rockchip: add support smp for rk3036
Quoted 8 lines · Heiko Stuebner
Am Mittwoch, 4. November 2015, 20:25:16 schrieb Xing Zheng:
Quoted 7 lines
From: Heiko Stuebner<[email protected]>
The dual-core Cortex A7 rk3036 is a bit special in that it does not allow to control the actual powerdomain of the cpu cores, while the rest of the smp-bringup like reset control and entry address handling stays the same. Its bigger sibling, the quad-core rk3128 again allows powerdomain control.
Quoted 11 lines
Quoted 6 lines
So allow that case by introducing a separate smp-enable-method, that simply disables powerdomain handling in the common code.
Signed-off-by Heiko Stuebner<[email protected]>Tested-by Xing Zheng<[email protected]>Signed-off-by Xing Zheng<[email protected]>This patch can work standalone, so I took the liberty of applying it to my soc branch for 4.5 already, so you don't need to resend it in future versions.
OK? thanks Heiko. :)
Re: [PATCH v6 6/8] ARM: rockchip: add support smp for rk3036
In reply to Xing ZhengQuoted 10 lines · Xing Zheng
From: Heiko Stuebner <[email protected]>
The dual-core Cortex A7 rk3036 is a bit special in that it does not allow to control the actual powerdomain of the cpu cores, while the rest of the smp-bringup like reset control and entry address handling stays the same. Its bigger sibling, the quad-core rk3128 again allows powerdomain control.
So allow that case by introducing a separate smp-enable-method, that simply disables powerdomain handling in the common code.
Quoted 8 lines
Signed-off-by Heiko Stuebner <[email protected]>Tested-by Xing Zheng <[email protected]>Signed-off-by Xing Zheng <[email protected]>---
Changes in v6: None
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
Acked-by Rob Herring <[email protected]>
Quoted 119 lines
arch/arm/mach-rockchip/platsmp.c | 45 +++++++++++++++++------- 2 files changed, 34 insertions(+), 12 deletions(-)Documentation/devicetree/bindings/arm/cpus.txt +1
-0@@ -200,6 +200,7 @@ nodes to be present and contain the properties described below. "qcom,gcc-msm8660" "qcom,kpss-acc-v1" "qcom,kpss-acc-v2" + "rockchip,rk3036-smp" "rockchip,rk3066-smp" "ste,dbx500-smp"arch/arm/mach-rockchip/platsmp.c +33
-12@@ -42,6 +42,7 @@ static int ncores;#define PMU_PWRDN_SCU 4static struct regmap *pmu; +static int has_pmu = true;static int pmu_power_domain_is_on (int pd) {@@ -89,20 +90,23 @@ static int pmu_set_power_domain(int pd, bool on)if (!IS_ERR (rstc) && !on)reset_control_assert (rstc); - ret =regmap_update_bits (pmu,PMU_PWRDN_CON ,BIT (pd), val); -if (ret <0 ) { -pr_err ("%s: could not update power domain\n" , __func__); -return ret; - } - - ret =-1 ; -while (ret != on) { - ret =pmu_power_domain_is_on (pd); +if (has_pmu) { + ret =regmap_update_bits (pmu,PMU_PWRDN_CON ,BIT (pd), val);if (ret <0 ) { -pr_err ("%s: could not read power domain state\n" , +pr_err ("%s: could not update power domain\n" , __func__);return ret; } + + ret =-1 ; +while (ret != on) { + ret =pmu_power_domain_is_on (pd); +if (ret <0 ) { +pr_err ("%s: could not read power domain state\n" , + __func__); +return ret; + } + } }if (!IS_ERR (rstc)) {@@ -122,7 +126,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) {int ret; -if (!sram_base_addr || !pmu) { +if (!sram_base_addr || (has_pmu && !pmu)) {pr_err ("%s: sram or pmu missing for cpu boot\n" , __func__);return -ENXIO ; }@@ -275,7 +279,7 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)return ; } -if (rockchip_smp_prepare_pmu ()) +if (has_pmu &&rockchip_smp_prepare_pmu ())return ;if (read_cpuid_part () ==ARM_CPU_PART_CORTEX_A9 ) {@@ -318,6 +322,13 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)pmu_set_power_domain (0 + i, false); } +static void __init rk3036_smp_prepare_cpus (unsigned int max_cpus) +{ + has_pmu = false; + +rockchip_smp_prepare_cpus (max_cpus); +} +#ifdef CONFIG_HOTPLUG_CPU static int rockchip_cpu_kill (unsigned int cpu) {@@ -340,6 +351,15 @@ static void rockchip_cpu_die(unsigned int cpu) }#endif +static struct smp_operations rk3036_smp_ops__initdata = { + .smp_prepare_cpus = rk3036_smp_prepare_cpus, + .smp_boot_secondary = rockchip_boot_secondary, +#ifdef CONFIG_HOTPLUG_CPU + .cpu_kill = rockchip_cpu_kill, + .cpu_die = rockchip_cpu_die, +#endif +}; +static struct smp_operations rockchip_smp_ops__initdata = { .smp_prepare_cpus = rockchip_smp_prepare_cpus, .smp_boot_secondary = rockchip_boot_secondary,@@ -349,4 +369,5 @@ static struct smp_operations rockchip_smp_ops __initdata = {#endif }; +CPU_METHOD_OF_DECLARE (rk3036_smp,"rockchip,rk3036-smp" , &rk3036_smp_ops);CPU_METHOD_OF_DECLARE (rk3066_smp,"rockchip,rk3066-smp" , &rockchip_smp_ops);Signature · 1 line
1.7.9.5
PATCH v6 7/8 ARM: dts: enable smp for rk3036
In reply to Xing ZhengEnable smp for rk3036, and add the smp sram name for adapting.
Signed-off-by Xing Zheng <[email protected]>
Reviewed-by Heiko Stuebner <[email protected]>
---
Changes in v6: None
arch/arm/boot/dts/rk3036.dtsi | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm/boot/dts/rk3036.dtsi +5 -0
@@ -75,6 +75,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "rockchip,rk3036-smp"; cpu0: cpu at f00 { device_type = "cpu";
@@ -157,6 +158,10 @@ #address-cells = <1>; #size-cells = <1>; ranges = <0 0x10080000 0x2000>; + smp-sram at 0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x00 0x10>; + }; }; cru: clock-controller at 20000000 {
Signature · 1 line
1.7.9.5
PATCH v6 8/8 rockchip: make sure timer5 is enabled on rk3036 platforms
In reply to Xing ZhengThe timer5 supplies the architected timer and thus as has to run when the system clocksource and clockevents drivers are registered.
---
Changes in v6:
Signed-off-by Xing Zheng <[email protected]>
Reviewed-by Heiko Stuebner <[email protected]>
arch/arm/mach-rockchip/rockchip.c | 44 +++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 17 deletions(-)
arch/arm/mach-rockchip/rockchip.c +27 -17
@@ -29,31 +29,38 @@#include "core.h" #include "pm.h" +#define RK3036_TIMER_PHYS 0x20044000 +#define RK3288_GRF_SOC_CON0 0x244#define RK3288_TIMER6_7_PHYS 0xff810000 +static void rockchip_init_arch_timer_supply (resource_size_t phys,int offs) +{ +void __iomem *reg_base =ioremap (phys,SZ_16K ); + +/* +* Most/all uboot versions for Rockchip SoCs don't enable +* timer which is needed for the architected timer to work. +* So make sure it is running during early boot. +*/ +if (reg_base) { +writel (0 , reg_base + offs +0x10 ); +writel (0xffffffff , reg_base + offs); +writel (0xffffffff , reg_base + offs +0x04 ); +writel (1 , reg_base + offs +0x10 ); +dsb (); +iounmap (reg_base); + }else { +pr_err ("rockchip: could not map timer registers\n" ); + } +} +static void __init rockchip_timer_init (void ) {if (of_machine_is_compatible ("rockchip,rk3288" )) {struct regmap *grf; -void __iomem *reg_base; -/* -* Most/all uboot versions for rk3288 don't enable timer7 -* which is needed for the architected timer to work. -* So make sure it is running during early boot. -*/ - reg_base =ioremap (RK3288_TIMER6_7_PHYS ,SZ_16K ); -if (reg_base) { -writel (0 , reg_base +0x30 ); -writel (0xffffffff , reg_base +0x20 ); -writel (0xffffffff , reg_base +0x24 ); -writel (1 , reg_base +0x30 ); -dsb (); -iounmap (reg_base); - }else { -pr_err ("rockchip: could not map timer7 registers\n" ); - } +rockchip_init_arch_timer_supply (RK3288_TIMER6_7_PHYS ,0x20 );/* * Disable auto jtag/sdmmc switching that causes issues
@@ -64,6 +71,8 @@ static void __init rockchip_timer_init(void)regmap_write (grf,RK3288_GRF_SOC_CON0 ,0x10000000 ); else pr_err("rockchip: could not get grf syscon\n"); + }else if (of_machine_is_compatible ("rockchip,rk3036" )) { +rockchip_init_arch_timer_supply (RK3036_TIMER_PHYS ,0xa0 ); }of_clk_init (NULL );
@@ -79,6 +88,7 @@ static void __init rockchip_dt_init(void)static const char *const rockchip_board_dt_compat[] = {"rockchip,rk2928" , +"rockchip,rk3036" ,"rockchip,rk3066a" ,"rockchip,rk3066b" ,"rockchip,rk3188" ,
Signature · 1 line
1.7.9.5
Heiko Stuebner
maintainerRe: [PATCH v6 8/8] rockchip: make sure timer5 is enabled on rk3036 platforms
Am Mittwoch, 4. November 2015, 20:25:57 schrieb Xing Zheng:
Quoted 8 lines
The timer5 supplies the architected timer and thus as has to run when the system clocksource and clockevents drivers are registered.
---
Changes in v6:
Signed-off-by Xing Zheng <[email protected]>Reviewed-by Heiko Stuebner <[email protected]>
This patch can work standalone, so I took the liberty of applying it to my soc branch for 4.5 already, so you don't need to resend it in future versions.
I fixed up the subject "ARM: rockchip:...", and moved the Signed-off-by to the correct position above the "---".