powerpc: add denormalisation exception handling for POWER6/7

PATCH In review Michael Neuling 4 participants 9 messages Jul 11, 2011 – Sep 10, 2012 PowerPC

Share & tools

Michael Neuling

author

2011-07-11 05:52 UTC #0 lore raw

PATCH 1/1 powerpc: add denormalisation exception handling for POWER6/7

On POWER6 and POWER7 if the input operand to an instruction is a denormalised single precision binary floating we can take a denormalisation exception where it's expected that the hypervisor (HV=1) will fix up the inputs before the instruction is run.

This adds code to handle this denormalisation exception for POWER6 and POWER7.

It also add a CONFIG_PPC_DENORMALISATION option and sets it in pseries/ppc64_defconfig.

This is useful on bare metal systems only. Based on patch from Milton Miller.

Signed-off-by Michael Neuling <[email protected]>

---
 arch/powerpc/Kconfig                   |    7 +
 arch/powerpc/configs/ppc64_defconfig   |    1 
 arch/powerpc/configs/pseries_defconfig |    1 
 arch/powerpc/include/asm/ppc-opcode.h  |    2 
 arch/powerpc/include/asm/reg.h         |    1 
 arch/powerpc/kernel/exceptions-64s.S   |  125 +++++++++++++++++++++++++++++++++
 6 files changed, 137 insertions(+)

arch/powerpc/Kconfig +7 -0

Index: linux-ozlabs/arch/powerpc/Kconfig
===================================================================
@@ -556,6 +556,13 @@ config SCHED_SMT
 	  when dealing with POWER5 cpus at a cost of slightly increased
 	  overhead in some places. If unsure say N here.
 
+config PPC_DENORMALISATION
+	bool "PowerPC denormalisation exception handling"
+	default "n"
+	---help---
+	  Add support for handling denormalisation of single precision
+	  values.  Useful for bare metal only.  If unsure say Y here.
+
 config CMDLINE_BOOL
 	bool "Default bootloader kernel arguments"

arch/powerpc/configs/ppc64_defconfig +1 -0

Index: linux-ozlabs/arch/powerpc/configs/ppc64_defconfig
===================================================================
@@ -54,6 +54,7 @@ CONFIG_KEXEC=y
 CONFIG_IRQ_ALL_CPUS=y
 CONFIG_MEMORY_HOTREMOVE=y
 CONFIG_SCHED_SMT=y
+CONFIG_PPC_DENORMALISATION=y
 CONFIG_PCCARD=y
 CONFIG_ELECTRA_CF=y
 CONFIG_HOTPLUG_PCI=m

arch/powerpc/configs/pseries_defconfig +1 -0

Index: linux-ozlabs/arch/powerpc/configs/pseries_defconfig
===================================================================
@@ -47,6 +47,7 @@ CONFIG_MEMORY_HOTREMOVE=y
 CONFIG_PPC_64K_PAGES=y
 CONFIG_PPC_SUBPAGE_PROT=y
 CONFIG_SCHED_SMT=y
+CONFIG_PPC_DENORMALISATION=y
 CONFIG_HOTPLUG_PCI=m
 CONFIG_HOTPLUG_PCI_RPA=m
 CONFIG_HOTPLUG_PCI_RPA_DLPAR=m

arch/powerpc/include/asm/ppc-opcode.h +2 -0

Index: linux-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
===================================================================
@@ -157,6 +157,8 @@
 					       VSX_XX1((s), (a), (b)))
 #define XXLOR(t, a, b)		stringify_in_c(.long PPC_INST_XXLOR | \
 					       VSX_XX3((t), (a), (b)))
+#define XVCPSGNDP(t, a, b)	stringify_in_c(.long (0xf0000780 | \
+					       VSX_XX3((t), (a), (b))))
 
 #define PPC_NAP			stringify_in_c(.long PPC_INST_NAP)
 #define PPC_SLEEP		stringify_in_c(.long PPC_INST_SLEEP)

arch/powerpc/include/asm/reg.h +1 -0

Index: linux-ozlabs/arch/powerpc/include/asm/reg.h
===================================================================
@@ -496,6 +496,7 @@
 
 #define SPRN_HSRR0	0x13A	/* Save/Restore Register 0 */
 #define SPRN_HSRR1	0x13B	/* Save/Restore Register 1 */
+#define   HSRR1_DENORM		0x00100000 /* Denorm exception */
 
 #define SPRN_TBCTL	0x35f	/* PA6T Timebase control register */
 #define   TBCTL_FREEZE		0x0000000000000000ull /* Freeze all tbs */

arch/powerpc/kernel/exceptions-64s.S +125 -0

143 lines not on this page · raw message

Kumar Gala

2011-07-12 03:51 UTC #1 lore raw

Quoted 3 lines · Michael Neuling

On POWER6 and POWER7 if the input operand to an instruction is a denormalised single precision binary floating we can take a denormalisation exception where it's expected that the hypervisor =

(HV=3D1)

Quoted 12 lines

will fix up the inputs before the instruction is run.
=20
This adds code to handle this denormalisation exception for POWER6 and POWER7.
=20
It also add a CONFIG_PPC_DENORMALISATION option and sets it in pseries/ppc64_defconfig.=20
=20
This is useful on bare metal systems only. Based on patch from Milton Miller.
=20
Signed-off-by Michael Neuling <[email protected]>

Quoted 8 lines

=20
---

arch/powerpc/Kconfig                   |    7 +
arch/powerpc/configs/ppc64_defconfig   |    1=20
arch/powerpc/configs/pseries_defconfig |    1=20
arch/powerpc/include/asm/ppc-opcode.h  |    2=20
arch/powerpc/include/asm/reg.h         |    1=20
arch/powerpc/kernel/exceptions-64s.S   |  125 =

+++++++++++++++++++++++++++++++++

Quoted 1 line

6 files changed, 137 insertions(+)

Is it possible to run POWER6/7 systems in baremetal if you are not IBM?

Just wondering if this is useful to anyone but IBM.

- k=

Benjamin Herrenschmidt

2011-07-12 04:12 UTC #2 lore raw

Quoted 27 lines · Kumar Gala

Quoted 16 lines · Michael Neuling
On POWER6 and POWER7 if the input operand to an instruction is a denormalised single precision binary floating we can take a denormalisation exception where it's expected that the hypervisor (HV=1) will fix up the inputs before the instruction is run.
This adds code to handle this denormalisation exception for POWER6 and POWER7.
It also add a CONFIG_PPC_DENORMALISATION option and sets it in pseries/ppc64_defconfig.
This is useful on bare metal systems only. Based on patch from Milton Miller.
Signed-off-by Michael Neuling <[email protected]>
Quoted 8 lines
---
arch/powerpc/Kconfig                   |    7 +
arch/powerpc/configs/ppc64_defconfig   |    1 
arch/powerpc/configs/pseries_defconfig |    1 
arch/powerpc/include/asm/ppc-opcode.h  |    2 
arch/powerpc/include/asm/reg.h         |    1 
arch/powerpc/kernel/exceptions-64s.S   |  125 +++++++++++++++++++++++++++++++++
6 files changed, 137 insertions(+)

Quoted 3 lines

Is it possible to run POWER6/7 systems in baremetal if you are not IBM?
Just wondering if this is useful to anyone but IBM.

While I cannot obviously comment on unreleased systems, the fact that we've been contributing all sort of patches to run P7 in "HV" mode and KVM on them should be enough of a hint :-)

Cheers,
Ben.

Kumar Gala

2011-07-13 05:27 UTC #3 lore raw

In reply to Michael Neuling

Quoted 3 lines · Michael Neuling

On POWER6 and POWER7 if the input operand to an instruction is a denormalised single precision binary floating we can take a denormalisation exception where it's expected that the hypervisor =

(HV=3D1)

Quoted 12 lines

will fix up the inputs before the instruction is run.
=20
This adds code to handle this denormalisation exception for POWER6 and POWER7.
=20
It also add a CONFIG_PPC_DENORMALISATION option and sets it in pseries/ppc64_defconfig.=20
=20
This is useful on bare metal systems only. Based on patch from Milton Miller.
=20
Signed-off-by Michael Neuling <[email protected]>

Quoted 8 lines

=20
---

arch/powerpc/Kconfig                   |    7 +
arch/powerpc/configs/ppc64_defconfig   |    1=20
arch/powerpc/configs/pseries_defconfig |    1=20
arch/powerpc/include/asm/ppc-opcode.h  |    2=20
arch/powerpc/include/asm/reg.h         |    1=20
arch/powerpc/kernel/exceptions-64s.S   |  125 =

+++++++++++++++++++++++++++++++++

Quoted 4 lines

6 files changed, 137 insertions(+)
=20
Index: linux-ozlabs/arch/powerpc/Kconfig =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

arch/powerpc/Kconfig config SCHED_SMT · line 560

Quoted 8 lines

arch/powerpc/Kconfig +0 -0

@@ -556,6 +556,13 @@ config SCHED_SMT
 	  when dealing with POWER5 cpus at a cost of slightly increased
 	  overhead in some places. If unsure say N here.

=20

arch/powerpc/Kconfig +2 -0

+config PPC_DENORMALISATION
+	bool "PowerPC denormalisation exception handling"

Should this at least depend on PPC_BOOK3S_64 ?

Quoted 9 lines

arch/powerpc/Kconfig +5 -0
+	default "n"
+	---help---
+	  Add support for handling denormalisation of single precision
+	  values.  Useful for bare metal only.  If unsure say Y here.
+
config CMDLINE_BOOL
bool "Default bootloader kernel arguments"
=20
=20

- k=

Michael Neuling

author

2011-07-13 05:30 UTC #4 lore raw

In message <[email protected]> you wrote :

Quoted 34 lines · Michael Neuling

Quoted 4 lines
On POWER6 and POWER7 if the input operand to an instruction is a denormalised single precision binary floating we can take a denormalisation exception where it's expected that the hypervisor =
(HV=3D1)
Quoted 12 lines
will fix up the inputs before the instruction is run.
=20
This adds code to handle this denormalisation exception for POWER6 and POWER7.
=20
It also add a CONFIG_PPC_DENORMALISATION option and sets it in pseries/ppc64_defconfig.=20
=20
This is useful on bare metal systems only. Based on patch from Milton Miller.
=20
Signed-off-by Michael Neuling <[email protected]>
Quoted 8 lines
=20
---
arch/powerpc/Kconfig                   |    7 +
arch/powerpc/configs/ppc64_defconfig   |    1=20
arch/powerpc/configs/pseries_defconfig |    1=20
arch/powerpc/include/asm/ppc-opcode.h  |    2=20
arch/powerpc/include/asm/reg.h         |    1=20
arch/powerpc/kernel/exceptions-64s.S   |  125 =
+++++++++++++++++++++++++++++++++
Quoted 4 lines
6 files changed, 137 insertions(+)
=20
Index: linux-ozlabs/arch/powerpc/Kconfig =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D

Quoted 10 lines

arch/powerpc/Kconfig config SCHED_SMT · line 560
Quoted 8 lines
arch/powerpc/Kconfig +0 -0
@@ -556,6 +556,13 @@ config SCHED_SMT
 	  when dealing with POWER5 cpus at a cost of slightly increased
 	  overhead in some places. If unsure say N here.
=20
arch/powerpc/Kconfig +2 -0
+config PPC_DENORMALISATION
+	bool "PowerPC denormalisation exception handling"
Should this at least depend on PPC_BOOK3S_64 ?

Yep, thanks!

Mikey

Michael Neuling

author

2012-09-10 06:54 UTC #5 lore raw

PATCH 1/1 powerpc: add denormalisation exception handling for POWER6/7

In reply to Kumar Gala

This adds code to handle this denormalisation exception for POWER6 and POWER7.

It also add a CONFIG_PPC_DENORMALISATION option and sets it in pseries/ppc64_defconfig.

This is useful on bare metal systems only. Based on patch from Milton Miller.

Signed-off-by Michael Neuling <[email protected]>

---
It's been a year since I posted this. I forgot to repost... I guess I got distracted by a dog with a fluffy tail or something.

So here's v2 to address Kumar's concern about the Kconfig dependency and to rebase on a years kernel dev.

If you have any comments, v3 will be out in ~2014.

arch/powerpc/Kconfig +8 -0

index 352f416..a454360 100644
@@ -557,6 +557,14 @@ config SCHED_SMT
 	  when dealing with POWER5 cpus at a cost of slightly increased
 	  overhead in some places. If unsure say N here.
 
+config PPC_DENORMALISATION
+	bool "PowerPC denormalisation exception handling"
+	depends on PPC_BOOK3S_64
+	default "n"
+	---help---
+	  Add support for handling denormalisation of single precision
+	  values.  Useful for bare metal only.  If unsure say Y here.
+
 config CMDLINE_BOOL
 	bool "Default bootloader kernel arguments"

arch/powerpc/configs/ppc64_defconfig +1 -0

index db27c82..e263e6a 100644
@@ -51,6 +51,7 @@ CONFIG_KEXEC=y
 CONFIG_IRQ_ALL_CPUS=y
 CONFIG_MEMORY_HOTREMOVE=y
 CONFIG_SCHED_SMT=y
+CONFIG_PPC_DENORMALISATION=y
 CONFIG_PCCARD=y
 CONFIG_ELECTRA_CF=y
 CONFIG_HOTPLUG_PCI=m

arch/powerpc/configs/pseries_defconfig +1 -0

index 1f65b3c..c169dfb 100644
@@ -48,6 +48,7 @@ CONFIG_MEMORY_HOTREMOVE=y
 CONFIG_PPC_64K_PAGES=y
 CONFIG_PPC_SUBPAGE_PROT=y
 CONFIG_SCHED_SMT=y
+CONFIG_PPC_DENORMALISATION=y
 CONFIG_HOTPLUG_PCI=m
 CONFIG_HOTPLUG_PCI_RPA=m
 CONFIG_HOTPLUG_PCI_RPA_DLPAR=m

arch/powerpc/include/asm/ppc-opcode.h +3 -0

index 4c25319..5f73ce6 100644
@@ -126,6 +126,7 @@
 #define PPC_INST_TLBIVAX		0x7c000624
 #define PPC_INST_TLBSRX_DOT		0x7c0006a5
 #define PPC_INST_XXLOR			0xf0000510
+#define PPC_INST_XVCPSGNDP		0xf0000780
 
 #define PPC_INST_NAP			0x4c000364
 #define PPC_INST_SLEEP			0x4c0003a4

@@ -277,6 +278,8 @@
 					       VSX_XX1((s), a, b))
 #define XXLOR(t, a, b)		stringify_in_c(.long PPC_INST_XXLOR | \
 					       VSX_XX3((t), a, b))
+#define XVCPSGNDP(t, a, b)	stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
+					       VSX_XX3((t), (a), (b))))
 
 #define PPC_NAP			stringify_in_c(.long PPC_INST_NAP)
 #define PPC_SLEEP		stringify_in_c(.long PPC_INST_SLEEP)

arch/powerpc/include/asm/reg.h +1 -0

index 334be34..d352aa4 100644
@@ -524,6 +524,7 @@
 
 #define SPRN_HSRR0	0x13A	/* Save/Restore Register 0 */
 #define SPRN_HSRR1	0x13B	/* Save/Restore Register 1 */
+#define   HSRR1_DENORM		0x00100000 /* Denorm exception */
 
 #define SPRN_TBCTL	0x35f	/* PA6T Timebase control register */
 #define   TBCTL_FREEZE		0x0000000000000000ull /* Freeze all tbs */

arch/powerpc/kernel/exceptions-64s.S +125 -0

143 lines not on this page · raw message

Michael Ellerman

2012-09-10 08:13 UTC #6 lore raw

Quoted 2 lines · Michael Neuling

On POWER6 and POWER7 if the input operand to an instruction is a denormalised single precision binary floating we can take a

                                               ^
                                               point value?

Quoted 13 lines

arch/powerpc/include/asm/ppc-opcode.h +1 -0

index 4c25319..5f73ce6 100644
@@ -126,6 +126,7 @@
 #define PPC_INST_TLBIVAX		0x7c000624
 #define PPC_INST_TLBSRX_DOT		0x7c0006a5
 #define PPC_INST_XXLOR			0xf0000510
+#define PPC_INST_XVCPSGNDP		0xf0000780
 
 #define PPC_INST_NAP			0x4c000364
 #define PPC_INST_SLEEP			0x4c0003a4

arch/powerpc/include/asm/ppc-opcode.h line 282

Quoted 5 lines

arch/powerpc/include/asm/ppc-opcode.h +2 -0

@@ -277,6 +278,8 @@
 					       VSX_XX1((s), a, b))
 #define XXLOR(t, a, b)		stringify_in_c(.long PPC_INST_XXLOR | \
 					       VSX_XX3((t), a, b))
+#define XVCPSGNDP(t, a, b)	stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
+					       VSX_XX3((t), (a), (b))))

If anyone else is wondering, yes the instruction really is "xvcpsgndp".

Quoted 17 lines

arch/powerpc/include/asm/reg.h +1 -0

index 334be34..d352aa4 100644
@@ -524,6 +524,7 @@
 
 #define SPRN_HSRR0	0x13A	/* Save/Restore Register 0 */
 #define SPRN_HSRR1	0x13B	/* Save/Restore Register 1 */
+#define   HSRR1_DENORM		0x00100000 /* Denorm exception */
 
 #define SPRN_TBCTL	0x35f	/* PA6T Timebase control register */
 #define   TBCTL_FREEZE		0x0000000000000000ull /* Freeze all tbs */

arch/powerpc/kernel/exceptions-64s.S +0 -0

index 39aa97d..6bbfbad 100644

arch/powerpc/kernel/exceptions-64s.S vsx_unavailable_pSeries_1: · line 281

Quoted 7 lines

arch/powerpc/kernel/exceptions-64s.S +4 -0

@@ -275,6 +275,31 @@ vsx_unavailable_pSeries_1:
 	STD_EXCEPTION_PSERIES(0x1300, 0x1300, instruction_breakpoint)
 	KVM_HANDLER_PR_SKIP(PACA_EXGEN, EXC_STD, 0x1300)
 
+#ifdef CONFIG_PPC_DENORMALISATION
+	. = 0x1500
+	.global denorm_Hypervisor
+denorm_Hypervisor:

The naming pattern seems to be "foo_exception_hv".

Quoted 6 lines

arch/powerpc/kernel/exceptions-64s.S +6 -0

+	HMT_MEDIUM
+	mtspr	SPRN_SPRG_HSCRATCH0,r13
+	mfspr	r13,SPRN_SPRG_HPACA
+	std	r9,PACA_EXGEN+EX_R9(r13)
+	std	r10,PACA_EXGEN+EX_R10(r13)
+	std	r11,PACA_EXGEN+EX_R11(r13)

arch/powerpc/kernel/exceptions-64s.S vsx_unavailable_pSeries_1: · line 297

Quoted 10 lines

arch/powerpc/kernel/exceptions-64s.S +10 -0

+	std	r12,PACA_EXGEN+EX_R12(r13)
+	mfspr	r9,SPRN_SPRG_HSCRATCH0
+	std	r9,PACA_EXGEN+EX_R13(r13)
+	mfcr	r9
+
+	mfspr	r10,SPRN_HSRR1
+	mfspr	r11,SPRN_HSRR0		/* save HSRR0 */
+	andis.	r10,r10,(HSRR1_DENORM)@h /* denorm? */
+	addi	r11,r11,-4		/* HSRR0 is next instruction */
+	bne+	denorm_assist

I think only this hunk should be inside the #ifdef.

ie. we should always handle the exception but if we have no denorm support you go to unknown_exception(), rather than just landing in fubar land.

Quoted 10 lines

arch/powerpc/kernel/exceptions-64s.S +4 -0

+	EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
+	KVM_HANDLER_SKIP(PACA_EXGEN, EXC_STD, 0x1500)
+#endif

@@ -336,6 +361,103 @@ do_stab_bolted_pSeries:
 	KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x900)
 	KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x982)
 
+#ifdef CONFIG_PPC_DENORMALISATION

arch/powerpc/kernel/exceptions-64s.S do_stab_bolted_pSeries: · line 374

Quoted 10 lines

arch/powerpc/kernel/exceptions-64s.S +10 -0

+denorm_assist:
+BEGIN_FTR_SECTION
+/*
+ * To denormalise we need to move a copy of the register to itself.
+ * For POWER6 do that here for all FP regs.
+ */
+	mfmsr	r10
+	ori	r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
+	xori	r10,r10,(MSR_FE0|MSR_FE1)
+	mtmsrd	r10

So we're enabling FP, and switching the FP exception mode to "ignore". Which is OK because we are going to switch it all back the way it was on the way out when we rfid?

Quoted 28 lines

arch/powerpc/kernel/exceptions-64s.S +28 -0

+	sync
+	fmr	0,0
+	fmr	1,1
+	fmr	2,2
+	fmr	3,3
+	fmr	4,4
+	fmr	5,5
+	fmr	6,6
+	fmr	7,7
+	fmr	8,8
+	fmr	9,9
+	fmr	10,10
+	fmr	11,11
+	fmr	12,12
+	fmr	13,13
+	fmr	14,14
+	fmr	15,15
+	fmr	16,16
+	fmr	17,17
+	fmr	18,18
+	fmr	19,19
+	fmr	20,20
+	fmr	21,21
+	fmr	22,22
+	fmr	23,23
+	fmr	24,24
+	fmr	25,25
+	fmr	26,26

arch/powerpc/kernel/exceptions-64s.S do_stab_bolted_pSeries: · line 412

Quoted 10 lines

arch/powerpc/kernel/exceptions-64s.S +10 -0

+	fmr	27,27
+	fmr	28,28
+	fmr	29,29
+	fmr	30,30
+	fmr	31,31
+FTR_SECTION_ELSE
+/*
+ * To denormalise we need to move a copy of the register to itself.
+ * For POWER7 do that here for the first 32 VSX registers only.
+ */

Why only the first 32?

arch/powerpc/kernel/exceptions-64s.S do_stab_bolted_pSeries: · line 415

Quoted 3 lines

arch/powerpc/kernel/exceptions-64s.S +3 -0
+	mfmsr	r10
+	oris	r10,r10,MSR_VSX@h
+	mtmsrd	r10

Here we just enable VSX and exceptions be damned?

Quoted 25 lines

arch/powerpc/kernel/exceptions-64s.S +25 -0

+	sync
+	XVCPSGNDP(0,0,0)
+	XVCPSGNDP(1,1,1)
+	XVCPSGNDP(2,2,2)
+	XVCPSGNDP(3,3,3)
+	XVCPSGNDP(4,4,4)
+	XVCPSGNDP(5,5,5)
+	XVCPSGNDP(6,6,6)
+	XVCPSGNDP(7,7,7)
+	XVCPSGNDP(8,8,8)
+	XVCPSGNDP(9,9,9)
+	XVCPSGNDP(10,10,10)
+	XVCPSGNDP(11,11,11)
+	XVCPSGNDP(12,12,12)
+	XVCPSGNDP(13,13,13)
+	XVCPSGNDP(14,14,14)
+	XVCPSGNDP(15,15,15)
+	XVCPSGNDP(16,16,16)
+	XVCPSGNDP(17,17,17)
+	XVCPSGNDP(18,18,18)
+	XVCPSGNDP(19,19,19)
+	XVCPSGNDP(20,20,20)
+	XVCPSGNDP(21,21,21)
+	XVCPSGNDP(22,22,22)
+	XVCPSGNDP(23,23,23)

arch/powerpc/kernel/exceptions-64s.S do_stab_bolted_pSeries: · line 450

Quoted 10 lines

arch/powerpc/kernel/exceptions-64s.S +10 -0

+	XVCPSGNDP(24,24,24)
+	XVCPSGNDP(25,25,25)
+	XVCPSGNDP(26,26,26)
+	XVCPSGNDP(27,27,27)
+	XVCPSGNDP(28,28,28)
+	XVCPSGNDP(29,29,29)
+	XVCPSGNDP(30,30,30)
+	XVCPSGNDP(31,31,31)
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
+	mtspr	SPRN_HSRR0,r11

Do we not need to restore HSRR1 too?

Quoted 14 lines

arch/powerpc/kernel/exceptions-64s.S +10 -0

+	mtcrf	0x80,r9
+	ld	r9,PACA_EXGEN+EX_R9(r13)
+	ld	r10,PACA_EXGEN+EX_R10(r13)
+	ld	r11,PACA_EXGEN+EX_R11(r13)
+	ld	r12,PACA_EXGEN+EX_R12(r13)
+	ld	r13,PACA_EXGEN+EX_R13(r13)
+	HRFID
+	b	.
+#endif
+
 	.align	7
 	/* moved from 0xe00 */
 	STD_EXCEPTION_HV(., 0xe02, h_data_storage)

arch/powerpc/kernel/exceptions-64s.S machine_check_common: · line 625

Quoted 9 lines

arch/powerpc/kernel/exceptions-64s.S +3 -0

@@ -495,6 +617,9 @@ machine_check_common:
         STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception)
 	STD_EXCEPTION_COMMON_ASYNC(0xf00, performance_monitor, .performance_monitor_exception)
 	STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
+#ifdef CONFIG_PPC_DENORMALISATION
+	STD_EXCEPTION_COMMON(0x1502, denorm, .unknown_exception)
+#endif
 #ifdef CONFIG_ALTIVEC
 	STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
 #else

Looking forward to your response in 2014 ;)

cheers

Michael Neuling

author

2012-09-10 10:33 UTC #7 lore raw

Quoted 5 lines · Michael Ellerman

Quoted 2 lines · Michael Neuling
On POWER6 and POWER7 if the input operand to an instruction is a denormalised single precision binary floating we can take a
                                               ^
                                               point value?

Thanks

Quoted 13 lines

arch/powerpc/include/asm/ppc-opcode.h +1 -0

index 4c25319..5f73ce6 100644
@@ -126,6 +126,7 @@
 #define PPC_INST_TLBIVAX		0x7c000624
 #define PPC_INST_TLBSRX_DOT		0x7c0006a5
 #define PPC_INST_XXLOR			0xf0000510
+#define PPC_INST_XVCPSGNDP		0xf0000780

Quoted 11 lines

arch/powerpc/include/asm/ppc-opcode.h line 282

Quoted 8 lines

arch/powerpc/include/asm/ppc-opcode.h +2 -0

 #define PPC_INST_NAP			0x4c000364
 #define PPC_INST_SLEEP			0x4c0003a4

@@ -277,6 +278,8 @@
 					       VSX_XX1((s), a, b))
 #define XXLOR(t, a, b)		stringify_in_c(.long PPC_INST_XXLOR | \
 					       VSX_XX3((t), a, b))
+#define XVCPSGNDP(t, a, b)	stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
+					       VSX_XX3((t), (a), (b))))

If anyone else is wondering, yes the instruction really is "xvcpsgndp".

Man, I didn't even notice that. I must have PPC asm Stockholm Syndrome.

Quoted 22 lines

arch/powerpc/include/asm/reg.h +1 -0

index 334be34..d352aa4 100644
@@ -524,6 +524,7 @@
 
 #define SPRN_HSRR0	0x13A	/* Save/Restore Register 0 */
 #define SPRN_HSRR1	0x13B	/* Save/Restore Register 1 */
+#define   HSRR1_DENORM		0x00100000 /* Denorm exception */
 
 #define SPRN_TBCTL	0x35f	/* PA6T Timebase control register */
 #define   TBCTL_FREEZE		0x0000000000000000ull /* Freeze all tbs */

arch/powerpc/kernel/exceptions-64s.S +0 -0

index 39aa97d..6bbfbad 100644
@@ -275,6 +275,31 @@ vsx_unavailable_pSeries_1:
 	STD_EXCEPTION_PSERIES(0x1300, 0x1300, instruction_breakpoint)
 	KVM_HANDLER_PR_SKIP(PACA_EXGEN, EXC_STD, 0x1300)

Quoted 6 lines

arch/powerpc/kernel/exceptions-64s.S vsx_unavailable_pSeries_1: · line 281
Quoted 4 lines
arch/powerpc/kernel/exceptions-64s.S +4 -0
+#ifdef CONFIG_PPC_DENORMALISATION
+	. = 0x1500
+	.global denorm_Hypervisor
+denorm_Hypervisor:
The naming pattern seems to be "foo_exception_hv".

Thanks, changed.

Quoted 20 lines

Quoted 7 lines
arch/powerpc/kernel/exceptions-64s.S +6 -0
+	HMT_MEDIUM
+	mtspr	SPRN_SPRG_HSCRATCH0,r13
+	mfspr	r13,SPRN_SPRG_HPACA
+	std	r9,PACA_EXGEN+EX_R9(r13)
+	std	r10,PACA_EXGEN+EX_R10(r13)
+	std	r11,PACA_EXGEN+EX_R11(r13)
arch/powerpc/kernel/exceptions-64s.S vsx_unavailable_pSeries_1: · line 297
Quoted 10 lines
arch/powerpc/kernel/exceptions-64s.S +10 -0
+	std	r12,PACA_EXGEN+EX_R12(r13)
+	mfspr	r9,SPRN_SPRG_HSCRATCH0
+	std	r9,PACA_EXGEN+EX_R13(r13)
+	mfcr	r9
+
+	mfspr	r10,SPRN_HSRR1
+	mfspr	r11,SPRN_HSRR0		/* save HSRR0 */
+	andis.	r10,r10,(HSRR1_DENORM)@h /* denorm? */
+	addi	r11,r11,-4		/* HSRR0 is next instruction */
+	bne+	denorm_assist
I think only this hunk should be inside the #ifdef.

Quoted 3 lines

ie. we should always handle the exception but if we have no denorm support you go to unknown_exception(), rather than just landing in fubar land.

Yep, thanks.

Quoted 10 lines

arch/powerpc/kernel/exceptions-64s.S +3 -0

+	EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
+	KVM_HANDLER_SKIP(PACA_EXGEN, EXC_STD, 0x1500)
+#endif

@@ -336,6 +361,103 @@ do_stab_bolted_pSeries:
 	KVM_HANDLER_PR(PACA_EXGEN, EXC_STD, 0x900)
 	KVM_HANDLER(PACA_EXGEN, EXC_HV, 0x982)

Quoted 15 lines

arch/powerpc/kernel/exceptions-64s.S do_stab_bolted_pSeries: · line 374
Quoted 11 lines
arch/powerpc/kernel/exceptions-64s.S +11 -0
+#ifdef CONFIG_PPC_DENORMALISATION
+denorm_assist:
+BEGIN_FTR_SECTION
+/*
+ * To denormalise we need to move a copy of the register to itself.
+ * For POWER6 do that here for all FP regs.
+ */
+	mfmsr	r10
+	ori	r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
+	xori	r10,r10,(MSR_FE0|MSR_FE1)
+	mtmsrd	r10
So we're enabling FP, and switching the FP exception mode to "ignore". Which is OK because we are going to switch it all back the way it was on the way out when we rfid?

Yep, RFID will take it from HSRR1.

Quoted 33 lines

arch/powerpc/kernel/exceptions-64s.S +32 -0

+	sync
+	fmr	0,0
+	fmr	1,1
+	fmr	2,2
+	fmr	3,3
+	fmr	4,4
+	fmr	5,5
+	fmr	6,6
+	fmr	7,7
+	fmr	8,8
+	fmr	9,9
+	fmr	10,10
+	fmr	11,11
+	fmr	12,12
+	fmr	13,13
+	fmr	14,14
+	fmr	15,15
+	fmr	16,16
+	fmr	17,17
+	fmr	18,18
+	fmr	19,19
+	fmr	20,20
+	fmr	21,21
+	fmr	22,22
+	fmr	23,23
+	fmr	24,24
+	fmr	25,25
+	fmr	26,26
+	fmr	27,27
+	fmr	28,28
+	fmr	29,29
+	fmr	30,30

Quoted 8 lines

arch/powerpc/kernel/exceptions-64s.S do_stab_bolted_pSeries: · line 412
Quoted 6 lines
arch/powerpc/kernel/exceptions-64s.S +6 -0
+	fmr	31,31
+FTR_SECTION_ELSE
+/*
+ * To denormalise we need to move a copy of the register to itself.
+ * For POWER7 do that here for the first 32 VSX registers only.
+ */
Why only the first 32?

Because it can only happen on the VSX regs that overlap the FP on POWER7, plus, that's what book IV told me..

Quoted 6 lines

arch/powerpc/kernel/exceptions-64s.S do_stab_bolted_pSeries: · line 415
Quoted 4 lines
arch/powerpc/kernel/exceptions-64s.S +3 -0
+	mfmsr	r10
+	oris	r10,r10,MSR_VSX@h
+	mtmsrd	r10
Here we just enable VSX and exceptions be damned?

IRQs are hard off (we never enabled them) and we aren't going to take any page faults with the MMU off also so we shouldn't take any exceptions.

Quoted 30 lines

arch/powerpc/kernel/exceptions-64s.S +29 -0

+	sync
+	XVCPSGNDP(0,0,0)
+	XVCPSGNDP(1,1,1)
+	XVCPSGNDP(2,2,2)
+	XVCPSGNDP(3,3,3)
+	XVCPSGNDP(4,4,4)
+	XVCPSGNDP(5,5,5)
+	XVCPSGNDP(6,6,6)
+	XVCPSGNDP(7,7,7)
+	XVCPSGNDP(8,8,8)
+	XVCPSGNDP(9,9,9)
+	XVCPSGNDP(10,10,10)
+	XVCPSGNDP(11,11,11)
+	XVCPSGNDP(12,12,12)
+	XVCPSGNDP(13,13,13)
+	XVCPSGNDP(14,14,14)
+	XVCPSGNDP(15,15,15)
+	XVCPSGNDP(16,16,16)
+	XVCPSGNDP(17,17,17)
+	XVCPSGNDP(18,18,18)
+	XVCPSGNDP(19,19,19)
+	XVCPSGNDP(20,20,20)
+	XVCPSGNDP(21,21,21)
+	XVCPSGNDP(22,22,22)
+	XVCPSGNDP(23,23,23)
+	XVCPSGNDP(24,24,24)
+	XVCPSGNDP(25,25,25)
+	XVCPSGNDP(26,26,26)
+	XVCPSGNDP(27,27,27)

Quoted 8 lines

arch/powerpc/kernel/exceptions-64s.S do_stab_bolted_pSeries: · line 450
Quoted 6 lines
arch/powerpc/kernel/exceptions-64s.S +6 -0
+	XVCPSGNDP(28,28,28)
+	XVCPSGNDP(29,29,29)
+	XVCPSGNDP(30,30,30)
+	XVCPSGNDP(31,31,31)
+ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
+	mtspr	SPRN_HSRR0,r11
Do we not need to restore HSRR1 too?

We never changed HSSR1, so yes.

Quoted 19 lines

arch/powerpc/kernel/exceptions-64s.S +11 -0

+	mtcrf	0x80,r9
+	ld	r9,PACA_EXGEN+EX_R9(r13)
+	ld	r10,PACA_EXGEN+EX_R10(r13)
+	ld	r11,PACA_EXGEN+EX_R11(r13)
+	ld	r12,PACA_EXGEN+EX_R12(r13)
+	ld	r13,PACA_EXGEN+EX_R13(r13)
+	HRFID
+	b	.
+#endif
+
 	.align	7
 	/* moved from 0xe00 */
 	STD_EXCEPTION_HV(., 0xe02, h_data_storage)

@@ -495,6 +617,9 @@ machine_check_common:
         STD_EXCEPTION_COMMON(0xe60, hmi_exception, .unknown_exception)
 	STD_EXCEPTION_COMMON_ASYNC(0xf00, performance_monitor, .performance_monitor_exception)
 	STD_EXCEPTION_COMMON(0x1300, instruction_breakpoint, .instruction_breakpoint_exception)
+#ifdef CONFIG_PPC_DENORMALISATION

Quoted 8 lines

arch/powerpc/kernel/exceptions-64s.S machine_check_common: · line 625
Quoted 5 lines
arch/powerpc/kernel/exceptions-64s.S +2 -0
+	STD_EXCEPTION_COMMON(0x1502, denorm, .unknown_exception)
+#endif
 #ifdef CONFIG_ALTIVEC
 	STD_EXCEPTION_COMMON(0x1700, altivec_assist, .altivec_assist_exception)
 #else
Looking forward to your response in 2014 ;)

Look at me... confounding expectations!

I'll repost...

Mikey

Michael Neuling

author

2012-09-10 10:35 UTC #8 lore raw

PATCH 1/1 powerpc: add denormalisation exception handling for POWER6/7

On POWER6 and POWER7 if the input operand to an instruction is a denormalised single precision binary floating point value we can take a denormalisation exception where it's expected that the hypervisor (HV=1) will fix up the inputs before the instruction is run.

This adds code to handle this denormalisation exception for POWER6 and POWER7.

It also add a CONFIG_PPC_DENORMALISATION option and sets it in pseries/ppc64_defconfig.

This is useful on bare metal systems only. Based on patch from Milton Miller.

Signed-off-by Michael Neuling <[email protected]>

---

v3 as per mpe's comments.

arch/powerpc/Kconfig +8 -0

index 352f416..a454360 100644
@@ -557,6 +557,14 @@ config SCHED_SMT
 	  when dealing with POWER5 cpus at a cost of slightly increased
 	  overhead in some places. If unsure say N here.
 
+config PPC_DENORMALISATION
+	bool "PowerPC denormalisation exception handling"
+	depends on PPC_BOOK3S_64
+	default "n"
+	---help---
+	  Add support for handling denormalisation of single precision
+	  values.  Useful for bare metal only.  If unsure say Y here.
+
 config CMDLINE_BOOL
 	bool "Default bootloader kernel arguments"

arch/powerpc/configs/ppc64_defconfig +1 -0

index db27c82..e263e6a 100644
@@ -51,6 +51,7 @@ CONFIG_KEXEC=y
 CONFIG_IRQ_ALL_CPUS=y
 CONFIG_MEMORY_HOTREMOVE=y
 CONFIG_SCHED_SMT=y
+CONFIG_PPC_DENORMALISATION=y
 CONFIG_PCCARD=y
 CONFIG_ELECTRA_CF=y
 CONFIG_HOTPLUG_PCI=m

arch/powerpc/configs/pseries_defconfig +1 -0

index 1f65b3c..c169dfb 100644
@@ -48,6 +48,7 @@ CONFIG_MEMORY_HOTREMOVE=y
 CONFIG_PPC_64K_PAGES=y
 CONFIG_PPC_SUBPAGE_PROT=y
 CONFIG_SCHED_SMT=y
+CONFIG_PPC_DENORMALISATION=y
 CONFIG_HOTPLUG_PCI=m
 CONFIG_HOTPLUG_PCI_RPA=m
 CONFIG_HOTPLUG_PCI_RPA_DLPAR=m

arch/powerpc/include/asm/ppc-opcode.h +3 -0

index 4c25319..5f73ce6 100644
@@ -126,6 +126,7 @@
 #define PPC_INST_TLBIVAX		0x7c000624
 #define PPC_INST_TLBSRX_DOT		0x7c0006a5
 #define PPC_INST_XXLOR			0xf0000510
+#define PPC_INST_XVCPSGNDP		0xf0000780
 
 #define PPC_INST_NAP			0x4c000364
 #define PPC_INST_SLEEP			0x4c0003a4

@@ -277,6 +278,8 @@
 					       VSX_XX1((s), a, b))
 #define XXLOR(t, a, b)		stringify_in_c(.long PPC_INST_XXLOR | \
 					       VSX_XX3((t), a, b))
+#define XVCPSGNDP(t, a, b)	stringify_in_c(.long (PPC_INST_XVCPSGNDP | \
+					       VSX_XX3((t), (a), (b))))
 
 #define PPC_NAP			stringify_in_c(.long PPC_INST_NAP)
 #define PPC_SLEEP		stringify_in_c(.long PPC_INST_SLEEP)

arch/powerpc/include/asm/reg.h +1 -0

index 334be34..d352aa4 100644
@@ -524,6 +524,7 @@
 
 #define SPRN_HSRR0	0x13A	/* Save/Restore Register 0 */
 #define SPRN_HSRR1	0x13B	/* Save/Restore Register 1 */
+#define   HSRR1_DENORM		0x00100000 /* Denorm exception */
 
 #define SPRN_TBCTL	0x35f	/* PA6T Timebase control register */
 #define   TBCTL_FREEZE		0x0000000000000000ull /* Freeze all tbs */

arch/powerpc/kernel/exceptions-64s.S +123 -0

141 lines not on this page · raw message