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arm64: dts: rockchip: add rk3399 DSI0 reset

PATCH In review Brian Norris 3 participants 6 messages Nov 29, 2017 – Dec 4, 2017

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Device tree bindings Arm Rockchip
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Brian Norris

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#0 lore raw

PATCH 1/1 arm64: dts: rockchip: add rk3399 DSI0 reset

We've documented this one already, but we didn't add it to the DTSI yet.

Suggested-by Nickey Yang <[email protected]>
Signed-off-by Brian Norris <[email protected]>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 ++
 1 file changed, 2 insertions(+)
arch/arm64/boot/dts/rockchip/rk3399.dtsi +2 -0
index c6dae25a3f23..8940a3dc3670 100644
@@ -1648,6 +1648,8 @@
 			 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
 		clock-names = "ref", "pclk", "phy_cfg", "grf";
 		power-domains = <&power RK3399_PD_VIO>;
+		resets = <&cru SRST_P_MIPI_DSI0>;
+		reset-names = "apb";
 		rockchip,grf = <&grf>;
 		status = "disabled";
Signature · 1 line
2.15.0.531.g2ccb3012c9-goog
author
#1 lore raw

PATCH 1/1 arm64: dts: rockchip: add rk3399 DSI0 reset

From: Nickey Yang <[email protected]>

This patch adds the information for the secondary MIPI DSI controller, e.g., interrupts, grf, clocks, ports and so on. Mirrors the existing definition for dsi0.

Signed-off-by Nickey Yang <[email protected]>
Signed-off-by Brian Norris <[email protected]>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 45 ++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)
arch/arm64/boot/dts/rockchip/rk3399.dtsi +45 -0
index 8940a3dc3670..e7e882d06c68 100644
@@ -1526,6 +1526,11 @@
 				reg = <2>;
 				remote-endpoint = <&hdmi_in_vopl>;
 			};
+
+			vopl_out_mipi1: endpoint at 3 {
+				reg = <3>;
+				remote-endpoint = <&mipi1_in_vopl>;
+			};
 		};
 	};
 

@@ -1573,6 +1578,11 @@
 				reg = <2>;
 				remote-endpoint = <&hdmi_in_vopb>;
 			};
+
+			vopb_out_mipi1: endpoint at 3 {
+				reg = <3>;
+				remote-endpoint = <&mipi1_in_vopb>;
+			};
 		};
 	};
 

@@ -1674,6 +1684,41 @@
 		};
 	};
 
+	mipi_dsi1: mipi at ff968000 {
+		compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
+		reg = <0x0 0xff968000 0x0 0x8000>;
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
+			 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
+		clock-names = "ref", "pclk", "phy_cfg", "grf";
+		power-domains = <&power RK3399_PD_VIO>;
+		resets = <&cru SRST_P_MIPI_DSI1>;
+		reset-names = "apb";
+		rockchip,grf = <&grf>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi1_in: port at 0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mipi1_in_vopb: endpoint at 0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_mipi1>;
+				};
+
+				mipi1_in_vopl: endpoint at 1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_mipi1>;
+				};
+			};
+		};
+	};
+
 	edp: edp at ff970000 {
 		compatible = "rockchip,rk3399-edp";
 		reg = <0x0 0xff970000 0x0 0x8000>;
Signature · 1 line
2.15.0.531.g2ccb3012c9-goog
#2 lore raw

On Wed, Nov 29, 2017 at 05:07:27PM -0800, Brian Norris wrote:

Sorry, I got the wrong $subject, will resend :(

#3 lore raw

PATCH 1/1 arm64: dts: rockchip: add mipi_dsi1 support for rk3399

In reply to Brian Norris

From: Nickey Yang <[email protected]>

This patch adds the information for the secondary MIPI DSI controller, e.g., interrupts, grf, clocks, ports and so on. Mirrors the existing definition for dsi0.

Signed-off-by Nickey Yang <[email protected]>
Signed-off-by Brian Norris <[email protected]>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 45 ++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)
arch/arm64/boot/dts/rockchip/rk3399.dtsi +45 -0
index 8940a3dc3670..e7e882d06c68 100644
@@ -1526,6 +1526,11 @@
 				reg = <2>;
 				remote-endpoint = <&hdmi_in_vopl>;
 			};
+
+			vopl_out_mipi1: endpoint at 3 {
+				reg = <3>;
+				remote-endpoint = <&mipi1_in_vopl>;
+			};
 		};
 	};
 

@@ -1573,6 +1578,11 @@
 				reg = <2>;
 				remote-endpoint = <&hdmi_in_vopb>;
 			};
+
+			vopb_out_mipi1: endpoint at 3 {
+				reg = <3>;
+				remote-endpoint = <&mipi1_in_vopb>;
+			};
 		};
 	};
 

@@ -1674,6 +1684,41 @@
 		};
 	};
 
+	mipi_dsi1: mipi at ff968000 {
+		compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
+		reg = <0x0 0xff968000 0x0 0x8000>;
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
+			 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
+		clock-names = "ref", "pclk", "phy_cfg", "grf";
+		power-domains = <&power RK3399_PD_VIO>;
+		resets = <&cru SRST_P_MIPI_DSI1>;
+		reset-names = "apb";
+		rockchip,grf = <&grf>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			mipi1_in: port at 0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mipi1_in_vopb: endpoint at 0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_mipi1>;
+				};
+
+				mipi1_in_vopl: endpoint at 1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_mipi1>;
+				};
+			};
+		};
+	};
+
 	edp: edp at ff970000 {
 		compatible = "rockchip,rk3399-edp";
 		reg = <0x0 0xff970000 0x0 0x8000>;
Signature · 1 line
2.15.0.531.g2ccb3012c9-goog
maintainer
#4 lore raw

Re: [PATCH] arm64: dts: rockchip: add mipi_dsi1 support for rk3399

Am Mittwoch, 29. November 2017, 17:11:27 CET schrieb Brian Norris:

Quoted 8 lines

From: Nickey Yang <[email protected]>

This patch adds the information for the secondary MIPI DSI controller, e.g., interrupts, grf, clocks, ports and so on. Mirrors the existing definition for dsi0.

Signed-off-by Nickey Yang <[email protected]>
Signed-off-by Brian Norris <[email protected]>

applied for 4.16

Thanks
Heiko