ARM: rockchip: add initial support for rk3288

This is necessary for the new RK3288 soc.

Signed-off-by Heiko Stuebner <[email protected]>

---
 Documentation/devicetree/bindings/arm/cpus.txt | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/arm/cpus.txt +0 -0

index 1fe72a0..620a1a8 100644

Quoted 7 lines · Heiko St?bner

This is necessary for the new RK3288 soc.

Signed-off-by Heiko Stuebner <[email protected]>

---
 Documentation/devicetree/bindings/arm/cpus.txt | 1 +
 1 file changed, 1 insertion(+)

Documentation/devicetree/bindings/arm/cpus.txt nodes to be present and contain the properties described below. · line 157

Quoted 11 lines

Documentation/devicetree/bindings/arm/cpus.txt +1 -0

index 1fe72a0..620a1a8 100644
@@ -152,6 +152,7 @@ nodes to be present and contain the properties described below.
 			    "arm,cortex-a7"
 			    "arm,cortex-a8"
 			    "arm,cortex-a9"
+			    "arm,cortex-a12"
 			    "arm,cortex-a15"
 			    "arm,cortex-a53"

You might as well add -a17 while you're at it, since it's an announced part from ARM.

The uarts on rk3288 are still compatible with the dw_8250, but located at a different position and need DEBUG_UART_8250_WORD enabled.

Signed-off-by Heiko Stuebner <[email protected]>

---
 arch/arm/Kconfig.debug | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

arch/arm/Kconfig.debug +0 -0

index 8f90595..f68def0 100644

Heiko,

Quoted 15 lines · Heiko St?bner

The uarts on rk3288 are still compatible with the dw_8250, but located at a different position and need DEBUG_UART_8250_WORD enabled.

Signed-off-by Heiko Stuebner <[email protected]>

---

 arch/arm/Kconfig.debug | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

arch/arm/Kconfig.debug +0 -0

index 8f90595..f68def0 100644
@@ -613,6 +613,14 @@ choice
 

arch/arm/Kconfig.debug choice · line 616

Quoted 5 lines

arch/arm/Kconfig.debug +1 -0

                  Say Y here if you want kernel low-level debugging
                  support
                  on Rockchip based platforms.
 
+       config DEBUG_RK32_UART2

It's slightly confusing that you didn't rename the old "DEBUG_RK3X_UART2".

Other than that:

Reviewed-by Doug Anderson <[email protected]>

Tested-by Doug Anderson <[email protected]>

Am Dienstag, 15. Juli 2014, 21:13:10 schrieb Doug Anderson:

Quoted 22 lines

Heiko,

Quoted 19 lines · Heiko St?bner

The uarts on rk3288 are still compatible with the dw_8250, but located at a different position and need DEBUG_UART_8250_WORD enabled.

Signed-off-by Heiko Stuebner <[email protected]>

---

 arch/arm/Kconfig.debug | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

arch/arm/Kconfig.debug +0 -0

index 8f90595..f68def0 100644
@@ -613,6 +613,14 @@ choice
 
                  Say Y here if you want kernel low-level debugging
                  support
                  on Rockchip based platforms.
 

Quoted 3 lines

arch/arm/Kconfig.debug choice · line 616

Quoted 1 line

arch/arm/Kconfig.debug +1 -0

+       config DEBUG_RK32_UART2

It's slightly confusing that you didn't rename the old "DEBUG_RK3X_UART2".

My problem is, to what :-) ... DEBUG_RK30_UART2 ?

RK30xx and RK31xx share these, but I guess at least the description should be adapted.

The new rk3288 needs a bigger gpio space, as it has 9 gpio banks.

Signed-off-by Heiko Stuebner <[email protected]>

---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

arch/arm/Kconfig +0 -0

index 87b63fd..8d1dee0 100644

Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible.

Signed-off-by Heiko Stuebner <[email protected]>

---
 arch/arm/mach-rockchip/Kconfig    | 1 +
 arch/arm/mach-rockchip/rockchip.c | 1 +
 2 files changed, 2 insertions(+)

arch/arm/mach-rockchip/Kconfig +0 -0

index e4564c2..d168669 100644

Heiko,

Quoted 14 lines · Heiko St?bner

Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible.

Signed-off-by Heiko Stuebner <[email protected]>

---

 arch/arm/mach-rockchip/Kconfig    | 1 +
 arch/arm/mach-rockchip/rockchip.c | 1 +
 2 files changed, 2 insertions(+)

(quoted diff) +0 -0

b/arch/arm/mach-rockchip/Kconfig index e4564c2..d168669 100644

arch/arm/mach-rockchip/Kconfig config ARCH_ROCKCHIP · line 11

Quoted 6 lines

arch/arm/mach-rockchip/Kconfig +1 -0

@@ -6,6 +6,7 @@ config ARCH_ROCKCHIP
 
        select ARCH_REQUIRE_GPIOLIB
        select ARM_GIC
        select CACHE_L2X0
 
+       select HAVE_ARM_ARCH_TIMER

Do we want to think about allowing someone to enable the A9-based Rockchip SoCs separately than the A12-based ones? I know it doesn't hurt to have the arch timer code present on A9 SoCs (it will figure things out at runtime), but people trying to build an A9-based system might not want the extra code?

Anyway, I don't feel strongly about it, so:

Reviewed-by Doug Anderson <[email protected]>

Tested-by Doug Anderson <[email protected]>

Heiko,

Quoted 8 lines · Heiko St?bner

Enable HAVE_ARM_ARCH_TIMER and add a rockchip,rk3288 compatible.

Signed-off-by Heiko Stuebner <[email protected]>

---
 arch/arm/mach-rockchip/Kconfig    | 1 +
 arch/arm/mach-rockchip/rockchip.c | 1 +
 2 files changed, 2 insertions(+)

arch/arm/mach-rockchip/Kconfig config ARCH_ROCKCHIP · line 9

Quoted 9 lines

arch/arm/mach-rockchip/Kconfig +1 -0

index e4564c2..d168669 100644
@@ -6,6 +6,7 @@ config ARCH_ROCKCHIP
        select ARCH_REQUIRE_GPIOLIB
        select ARM_GIC
        select CACHE_L2X0
+       select HAVE_ARM_ARCH_TIMER

Do we want to think about allowing someone to enable the A9-based Rockchip SoCs separately than the A12-based ones? I know it doesn't hurt to have the arch timer code present on A9 SoCs (it will figure things out at runtime), but people trying to build an A9-based system might not want the extra code?

Node definitions shared by all rk3288 based boards.

Signed-off-by Heiko Stuebner <[email protected]>

---
 arch/arm/boot/dts/rk3288.dtsi | 561 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 561 insertions(+)
 create mode 100644 arch/arm/boot/dts/rk3288.dtsi

arch/arm/boot/dts/rk3288.dtsi new file +19 -0

new file mode 100644
index 0000000..6e36cec
@@ -0,0 +1,561 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include "skeleton.dtsi"
+

arch/arm/boot/dts/rk3288.dtsi new file +12 -0

+			device_type = "cpu";
+			compatible = "arm,cortex-a12";
+			reg = <0x500>;
+		};
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a12";
+			reg = <0x501>;
+		};
+		cpu at 2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a12";

arch/arm/boot/dts/rk3288.dtsi new file +15 -0

+			compatible = "arm,armv7-timer";
+			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+				     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+				     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+				     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+			clock-frequency = <24000000>;
+		};
+
+		gic: interrupt-controller at ffc01000 {
+			compatible = "arm,gic-400";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#address-cells = <0>;
+
+			reg = <0xffc01000 0x1000>,

arch/arm/boot/dts/rk3288.dtsi new file +379 -0

+			compatible = "rockchip,rk3288-pinctrl";
+			rockchip,grf = <&grf>;
+			rockchip,pmu = <&pmu>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			gpio0: gpio0 at ff750000 {
+				compatible = "rockchip,gpio-bank";
+				reg =	<0xff750000 0x100>;
+				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO0>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio1: gpio1 at ff780000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff780000 0x100>;
+				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO1>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio2: gpio2 at ff790000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff790000 0x100>;
+				interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO2>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio3: gpio3 at ff7a0000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff7a0000 0x100>;
+				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO3>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio4: gpio4 at ff7b0000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff7b0000 0x100>;
+				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO4>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio5: gpio5 at ff7c0000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff7c0000 0x100>;
+				interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO5>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio6: gpio6 at ff7d0000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff7d0000 0x100>;
+				interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO6>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio7: gpio7 at ff7e0000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff7e0000 0x100>;
+				interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO7>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			gpio8: gpio8 at ff7f0000 {
+				compatible = "rockchip,gpio-bank";
+				reg = <0xff7f0000 0x100>;
+				interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&cru PCLK_GPIO8>;
+
+				gpio-controller;
+				#gpio-cells = <2>;
+
+				interrupt-controller;
+				#interrupt-cells = <2>;
+			};
+
+			pcfg_pull_up: pcfg_pull_up {
+				bias-pull-up;
+			};
+
+			pcfg_pull_down: pcfg_pull_down {
+				bias-pull-down;
+			};
+
+			pcfg_pull_none: pcfg_pull_none {
+				bias-disable;
+			};
+
+			i2c0 {
+				i2c0_xfer: i2c0-xfer {
+					rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
+							<0 16 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c1 {
+				i2c1_xfer: i2c1-xfer {
+					rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
+							<8 5 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c2 {
+				i2c2_xfer: i2c2-xfer {
+					rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
+							<6 10 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c3 {
+				i2c3_xfer: i2c3-xfer {
+					rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
+							<2 17 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c4 {
+				i2c4_xfer: i2c4-xfer {
+					rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
+							<7 18 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			i2c5 {
+				i2c5_xfer: i2c5-xfer {
+					rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
+							<7 20 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			sdmmc {
+				sdmmc_clk: sdmmc-clk {
+					rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
+				};
+
+				sdmmc_cmd: sdmmc-cmd {
+					rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
+				};
+
+				sdmmc_cd: sdmcc-cd {
+					rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
+				};
+
+				sdmmc_bus1: sdmmc-bus1 {
+					rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
+				};
+
+				sdmmc_bus4: sdmmc-bus4 {
+					rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
+							<6 17 RK_FUNC_1 &pcfg_pull_up>,
+							<6 18 RK_FUNC_1 &pcfg_pull_up>,
+							<6 19 RK_FUNC_1 &pcfg_pull_up>;
+				};
+			};
+
+			emmc {
+				emmc_clk: emmc-clk {
+					rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
+				};
+
+				emmc_cmd: emmc-cmd {
+					rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
+				};
+
+				emmc_pwr: emmc-pwr {
+					rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
+				};
+
+				emmc_bus1: emmc-bus1 {
+					rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
+				};
+
+				emmc_bus4: emmc-bus4 {
+					rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
+							<3 1 RK_FUNC_2 &pcfg_pull_up>,
+							<3 2 RK_FUNC_2 &pcfg_pull_up>,
+							<3 3 RK_FUNC_2 &pcfg_pull_up>;
+				};
+
+				emmc_bus8: emmc-bus8 {
+					rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
+							<3 1 RK_FUNC_2 &pcfg_pull_up>,
+							<3 2 RK_FUNC_2 &pcfg_pull_up>,
+							<3 3 RK_FUNC_2 &pcfg_pull_up>,
+							<3 4 RK_FUNC_2 &pcfg_pull_up>,
+							<3 5 RK_FUNC_2 &pcfg_pull_up>,
+							<3 6 RK_FUNC_2 &pcfg_pull_up>,
+							<3 7 RK_FUNC_2 &pcfg_pull_up>;
+				};
+			};
+
+			uart0 {
+				uart0_xfer: uart0-xfer {
+					rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
+							<4 17 RK_FUNC_1 &pcfg_pull_none>;
+				};
+
+				uart0_cts: uart0-cts {
+					rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
+				};
+
+				uart0_rts: uart0-rts {
+					rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			uart1 {
+				uart1_xfer: uart1-xfer {
+					rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
+							<5 9 RK_FUNC_1 &pcfg_pull_none>;
+				};
+
+				uart1_cts: uart1-cts {
+					rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
+				};
+
+				uart1_rts: uart1-rts {
+					rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			uart2 {
+				uart2_xfer: uart2-xfer {
+					rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
+							<7 23 RK_FUNC_1 &pcfg_pull_none>;
+				};
+				/* no rts / cts for uart2 */
+			};
+
+			uart3 {
+				uart3_xfer: uart3-xfer {
+					rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
+							<7 8 RK_FUNC_1 &pcfg_pull_none>;
+				};
+
+				uart3_cts: uart3-cts {
+					rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
+				};
+
+				uart3_rts: uart3-rts {
+					rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
+				};
+			};
+
+			uart4 {
+				uart4_xfer: uart4-xfer {
+					rockchip,pins = <5 12 3 &pcfg_pull_up>,
+							<5 13 3 &pcfg_pull_none>;
+				};
+
+				uart4_cts: uart4-cts {
+					rockchip,pins = <5 14 3 &pcfg_pull_none>;
+				};
+
+				uart4_rts: uart4-rts {
+					rockchip,pins = <5 15 3 &pcfg_pull_none>;
+				};
+			};
+		};
+
+		i2c0: i2c at ff650000 {
+			compatible = "rockchip,rk3288-i2c";
+			reg = <0xff650000 0x1000>;
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-names = "i2c";
+			clocks = <&cru PCLK_I2C0>;
+
+			status = "disabled";
+		};
+
+		i2c1: i2c at ff140000 {
+			compatible = "rockchip,rk3288-i2c";
+			reg = <0xff140000 0x1000>;
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-names = "i2c";
+			clocks = <&cru PCLK_I2C1>;
+
+			status = "disabled";
+		};
+
+		i2c2: i2c at ff660000 {
+			compatible = "rockchip,rk3288-i2c";
+			reg = <0xff660000 0x1000>;
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-names = "i2c";
+			clocks = <&cru PCLK_I2C2>;
+
+			status = "disabled";
+		};
+
+		i2c3: i2c at ff150000 {
+			compatible = "rockchip,rk3288-i2c";
+			reg = <0xff150000 0x1000>;
+			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-names = "i2c";
+			clocks = <&cru PCLK_I2C3>;
+
+			status = "disabled";
+		};
+
+		i2c4: i2c at ff160000 {
+			compatible = "rockchip,rk3288-i2c";
+			reg = <0xff160000 0x1000>;
+			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			clock-names = "i2c";
+			clocks = <&cru PCLK_I2C4>;
+
+			status = "disabled";
+		};
+
+		i2c5: i2c at ff170000 {
+			compatible = "rockchip,rk3288-i2c";
+			reg = <0xff170000 0x1000>;
+			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+			#address-cells = <1>;

arch/arm/boot/dts/rk3288.dtsi new file +56 -0

+			reg = <0xff180000 0x100>;
+			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart1: serial at ff190000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff190000 0x100>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart2: serial at ff690000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff690000 0x100>;
+			interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart2_xfer>;
+		};
+
+		uart3: serial at ff1b0000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff1b0000 0x100>;
+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+		};
+
+		uart4: serial at ff1c0000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0xff1c0000 0x100>;
+			interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+			clock-names = "baudclk", "apb_pclk";
+			status = "disabled";
+		};
+	};
+};

Signature · 1 line

1.9.0

arch/arm/boot/dts/rk3288.dtsi new file +31 -0

+                       i2c0 {
+                               i2c0_xfer: i2c0-xfer {
+                                       rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
+                                                       <0 16 RK_FUNC_1 &pcfg_pull_none>;
+                               };
+                       };
+
+                       i2c1 {
+                               i2c1_xfer: i2c1-xfer {
+                                       rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
+                                                       <8 5 RK_FUNC_1 &pcfg_pull_none>;
+                               };
+                       };
+
+                       i2c2 {
+                               i2c2_xfer: i2c2-xfer {
+                                       rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
+                                                       <6 10 RK_FUNC_1 &pcfg_pull_none>;
+                               };
+                       };
+
+                       i2c3 {
+                               i2c3_xfer: i2c3-xfer {
+                                       rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
+                                                       <2 17 RK_FUNC_1 &pcfg_pull_none>;
+                               };
+                       };
+
+                       i2c4 {
+                               i2c4_xfer: i2c4-xfer {
+                                       rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,

+&i2c0 {

arch/arm/boot/dts/rk3288-evb-act8846.dts new file +12 -0

+	hym8563 at 51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+
+		interrupt-parent = <&gpio0>;
+		interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&hym8563_int>;
+
+		#clock-cells = <0>;
+		clock-output-names = "xin32k";

arch/arm/boot/dts/rk3288-evb-act8846.dts new file +94 -0

+	regulators {
+		vcc_ddr: REG1 {
+			regulator-name = "VCC_DDR";
+			regulator-min-microvolt = <1200000>;
+			regulator-max-microvolt = <1200000>;
+			regulator-always-on;
+		};
+
+		vcc_io: REG2 {
+			regulator-name = "VCC_IO";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		vdd_log: REG3 {
+			regulator-name = "VDD_LOG";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-always-on;
+		};
+
+		vcc_20: REG4 {
+			regulator-name = "VCC_20";
+			regulator-min-microvolt = <2000000>;
+			regulator-max-microvolt = <2000000>;
+			regulator-always-on;
+		};
+
+		vccio_sd: REG5 {
+			regulator-name = "VCCIO_SD";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		vdd10_lcd: REG6 {
+			regulator-name = "VDD10_LCD";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-always-on;
+		};
+
+		vcca_codec: REG7 {
+			regulator-name = "VCCA_CODEC";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		vcca_tp: REG8 {
+			regulator-name = "VCCA_TP";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		vccio_pmu: REG9 {
+			regulator-name = "VCCIO_PMU";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		vdd_10: REG10 {
+			regulator-name = "VDD_10";
+			regulator-min-microvolt = <1000000>;
+			regulator-max-microvolt = <1000000>;
+			regulator-always-on;
+		};
+
+		vcc_18: REG11 {
+			regulator-name = "VCC_18";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+		};
+
+		vcc18_lcd: REG12 {
+			regulator-name = "VCC18_LCD";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+			regulator-always-on;
+		};
+	};
+};
+
+&pinctrl {
+	hym8563 {
+		hym8563_int: hym8563-int {
+			rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};

arch/arm/boot/dts/rk3288-evb-rk808.dts new file +9 -0

new file mode 100644
index 0000000..c168cb2
@@ -0,0 +1,19 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

arch/arm/boot/dts/rk3288-evb.dtsi new file +19 -0

new file mode 100644
index 0000000..ff642d4
@@ -0,0 +1,77 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "rk3288.dtsi"
+
+/ {
+	aliases {
+		serial0 = &uart0;
+		serial1 = &uart1;
+		serial2 = &uart2;

arch/arm/boot/dts/rk3288-evb.dtsi new file +38 -0

+			compatible = "gpio-keys";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			autorepeat;
+
+			button at 0 {
+				gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+				linux,code = <116>;
+				label = "GPIO Key Power";
+				linux,input-type = <1>;
+				gpio-key,wakeup = <1>;
+				debounce-interval = <100>;
+			};
+		};
+
+		i2c0: i2c at ff650000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_xfer>;
+			status = "okay";
+		};
+
+		watchdog at ff800000 {
+			status = "okay";
+		};
+
+		serial at ff180000 {
+			status = "okay";
+		};
+
+		serial at ff190000 {
+			status = "okay";
+		};
+
+		uart2: serial at ff690000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart2_xfer>;
+			status = "okay";
+		};

arch/arm/boot/dts/rk3288-evb-rk808.dts new file +8 -0

new file mode 100644
index 0000000..c168cb2
@@ -0,0 +1,19 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

arch/arm/boot/dts/rk3288-evb-rk808.dts new file +1 -0

+};

arch/arm/boot/dts/rk3288-evb.dtsi new file +11 -0

new file mode 100644
index 0000000..ff642d4
@@ -0,0 +1,77 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */

arch/arm/boot/dts/rk3288-evb.dtsi new file +22 -0

+
+                       button at 0 {
+                               gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+                               linux,code = <116>;
+                               label = "GPIO Key Power";
+                               linux,input-type = <1>;
+                               gpio-key,wakeup = <1>;
+                               debounce-interval = <100>;
+                       };
+               };
+
+               i2c0: i2c at ff650000 {
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&i2c0_xfer>;
+                       status = "okay";
+               };
+
+               watchdog at ff800000 {
+                       status = "okay";
+               };
+
+               serial at ff180000 {

arch/arm/boot/dts/rk3288-evb.dtsi new file +2 -0

+                       status = "okay";
+               };

Heiko,

Quoted 14 lines · Heiko St?bner

(quoted diff) +0 -0

b/arch/arm/boot/dts/rk3288-evb-rk808.dts new file mode 100644 index 0000000..c168cb2

arch/arm/boot/dts/rk3288-evb-rk808.dts new file +8 -0

@@ -0,0 +1,19 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of

arch/arm/boot/dts/rk3288-evb-rk808.dts line 18

Quoted 10 lines

arch/arm/boot/dts/rk3288-evb-rk808.dts new file +10 -0

+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+#include "rk3288-evb.dtsi"
+
+/ {
+       compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
+

nit: remove extra blank line?

Quoted 18 lines

arch/arm/boot/dts/rk3288-evb-rk808.dts new file +1 -0

+};

(quoted diff) +0 -0

b/arch/arm/boot/dts/rk3288-evb.dtsi new file mode 100644 index 0000000..ff642d4

arch/arm/boot/dts/rk3288-evb.dtsi new file +11 -0

@@ -0,0 +1,77 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */

arch/arm/boot/dts/rk3288-evb.dtsi line 21

Quoted 10 lines

arch/arm/boot/dts/rk3288-evb.dtsi new file +10 -0

+
+#include "rk3288.dtsi"
+
+/ {
+       aliases {
+               serial0 = &uart0;
+               serial1 = &uart1;
+               serial2 = &uart2;
+               serial3 = &uart3;
+               serial4 = &uart4;

Can the aliases go in the main dtsi?

arch/arm/boot/dts/rk3288-evb.dtsi line 33

Quoted 12 lines

arch/arm/boot/dts/rk3288-evb.dtsi new file +12 -0

+       };
+
+       memory {
+               reg = <0x0 0x80000000>;
+       };
+
+       soc {
+               gpio-keys {
+                       compatible = "gpio-keys";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       autorepeat;

I would have expected pinctrl for gpio0-5 to make sure pulls are enabled / disabled as appropriate.

Quoted 26 lines

arch/arm/boot/dts/rk3288-evb.dtsi new file +26 -0

+
+                       button at 0 {
+                               gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+                               linux,code = <116>;
+                               label = "GPIO Key Power";
+                               linux,input-type = <1>;
+                               gpio-key,wakeup = <1>;
+                               debounce-interval = <100>;
+                       };
+               };
+
+               i2c0: i2c at ff650000 {
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&i2c0_xfer>;
+                       status = "okay";
+               };
+
+               watchdog at ff800000 {
+                       status = "okay";
+               };
+
+               serial at ff180000 {
+                       status = "okay";
+               };
+
+               serial at ff190000 {

arch/arm/boot/dts/rk3288-evb.dtsi line 65

Quoted 6 lines

arch/arm/boot/dts/rk3288-evb.dtsi new file +6 -0

+                       status = "okay";
+               };
+
+               uart2: serial at ff690000 {
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&uart2_xfer>;

Why is this pinctrl here?

Quoted 3 lines

arch/arm/boot/dts/rk3288-evb.dtsi new file +2 -0

+                       status = "okay";
+               };

This series adds the initial support for Rockchip rk3288 socs including debug uart and devicetree files for the rk3288 evaluation board and enables these boards to boot into an initramfs.

The series depends on an updated bootloader, which must start the timer supplying the architected timer, which we will hopefully get in the next days. It also depends on the patch
"irqchip: gic: Add binding probe for ARM GIC400"
which will hopefully make it into the irqchip tree shortly.

Heiko Stuebner (6):
dt-bindings: arm: add arm,cortex-a12 cpu compatible property
ARM: rockchip: add debug uart used by rk3288
ARM: Kconfig: set default gpio number for rockchip SoCs
ARM: rockchip: enable support for RK3288 SoCs
ARM: dts: rockchip: add core rk3288 dtsi
ARM: dts: add rk3288 evaluation board