ARM: Meson6: enable SMP

Amlogic Meson6 is a dual-core Cortex-A9. This patchset adds all the necessary pieces to boot the secondary CPU.

---

This is a resend of a patchset already submitted a while ago
http://www.spinics.net/lists/arm-kernel/msg366787.html

Carlo Caione (3):
ARM: Meson6: docs: document bindings
ARM: Meson6: Add SMP support for Amlogic Meson6
ARM: Meson6: enable SMP in DTS/DTSI

 .../bindings/arm/meson/amlogic,meson6-cpuconfig    | 16 +++++
 .../bindings/arm/meson/amlogic,meson6-smp          | 26 +++++++
 arch/arm/boot/dts/meson.dtsi                       |  5 ++
 arch/arm/boot/dts/meson6.dtsi                      |  6 ++
 arch/arm/mach-meson/Kconfig                        |  1 +
 arch/arm/mach-meson/Makefile                       |  1 +
 arch/arm/mach-meson/headsmp.S                      |  7 ++
 arch/arm/mach-meson/platsmp.c                      | 80 ++++++++++++++++++++++
 8 files changed, 142 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/meson/amlogic,meson6-cpuconfig
 create mode 100644 Documentation/devicetree/bindings/arm/meson/amlogic,meson6-smp
 create mode 100644 arch/arm/mach-meson/headsmp.S
 create mode 100644 arch/arm/mach-meson/platsmp.c

1.9.1

Documentation for the devicetree bindings introduced with the SMP support

---
 .../bindings/arm/meson/amlogic,meson6-cpuconfig    | 16 +++++++++++++
 .../bindings/arm/meson/amlogic,meson6-smp          | 26 ++++++++++++++++++++++
 2 files changed, 42 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/meson/amlogic,meson6-cpuconfig
 create mode 100644 Documentation/devicetree/bindings/arm/meson/amlogic,meson6-smp

new file mode 100644
index 0000000..2db4cbb
@@ -0,0 +1,16 @@
+Secondary CPU management unit:
+-------------------------------
+
+This document describes the "amlogic,meson6-cpuconfig" node for enabling the
+secondary CPU.
+
+Required node properties:
+- compatible value : = "amlogic,meson6-cpuconfig";
+- reg : physical base address and the size of the registers window
+
+Example:
+
+	cpuconfig at d901ff80 {
+		compatible = "amlogic,meson6-cpuconfig";
+		reg = <0xd901ff80 0x8>;
+	};

new file mode 100644
index 0000000..4130381
@@ -0,0 +1,26 @@
+Secondary CPU enable-method "amlogic,meson6-smp" binding:
+----------------------------------------------------------
+
+This document describes the "amlogic,meson6-smp" method for enabling secondary
+CPUs. To apply to all CPUs, a single "amlogic,meson6-smp" enable method should
+be defined in the "cpus" node.
+
+Example:
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "amlogic,meson6-smp";
+
+		cpu at 200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x200>;
+		};
+
+		cpu at 201 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0x201>;
+		};
+	};

1.9.1

Amlogic Meson6 is a dual core Cortex-A9. This patch adds the logic to boot up the second CPU.

---
 arch/arm/mach-meson/Kconfig   |  1 +
 arch/arm/mach-meson/Makefile  |  1 +
 arch/arm/mach-meson/headsmp.S |  7 ++++
 arch/arm/mach-meson/platsmp.c | 80 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 89 insertions(+)
 create mode 100644 arch/arm/mach-meson/headsmp.S
 create mode 100644 arch/arm/mach-meson/platsmp.c

index 2c1154e..4e96de4 100644
@@ -2,6 +2,7 @@ menuconfig ARCH_MESON
 	bool "Amlogic Meson SoCs" if ARCH_MULTI_V7
 	select GENERIC_IRQ_CHIP
 	select ARM_GIC
+	select HAVE_ARM_SCU if SMP
 
 if ARCH_MESON
 

index 9d7380e..4691966 100644
@@ -1 +1,2 @@
 obj-$(CONFIG_ARCH_MESON) += meson.o
+obj-$(CONFIG_SMP) += platsmp.o headsmp.o

new file mode 100644
index 0000000..3347d88
@@ -0,0 +1,7 @@
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+ENTRY(meson_secondary_startup)
+        bl	v7_invalidate_l1
+        b       secondary_startup
+ENDPROC(meson_secondary_startup)

1.9.1

---
 arch/arm/boot/dts/meson.dtsi  | 5 +++++
 arch/arm/boot/dts/meson6.dtsi | 6 ++++++
 2 files changed, 11 insertions(+)

index e6539ea..6178756 100644
@@ -64,6 +64,11 @@
 		interrupts = <0 10 1>;
 	};
 
+	scu at c4300000 {
+		compatible = "arm,cortex-a9-scu";
+		reg = <0xc4300000 0x1000>;
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <1>;

index 4ba4912..6e7230f 100644
@@ -56,6 +56,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "amlogic,meson6-smp";
 
 		cpu at 200 {
 			device_type = "cpu";

@@ -70,6 +71,11 @@
 		};
 	};
 
+	cpuconfig at d901ff80 {
+		compatible = "amlogic,meson6-cpuconfig";
+		reg = <0xd901ff80 0x8>;
+	};
+
 	clk81: clk at 0 {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";

1.9.1

Ping

Carlo Caione

Hi Carlo,

Is this for arm-soc? I guess from the contents that it is, but you had 10 people in 'To', and you don't say in the introductory mail what you would like to happen with these patches.

When you send something for inclusion in arm-soc, please always send it 'To: arm at kernel.org' with everyone else on Cc instead of To, and be explicit with whether you think the contents are ready to be merged or whether you would like to see more review.

Arnd

Hi Arnd,
my ping was because I haven't received any feedback on the patchset. Taking the silence as an ACK I'll take the patches in my repo to pull to arm-soc within the next pull request.

Thanks,

Carlo Caione