Renesas R-Car Gen2 Common Clock Framework support
Subsystems (5)
v3 cover Renesas R-Car Gen2 Common Clock Framework support
Hello,
This is the third version of the CCF clock drivers for the Renesas R-Car R8A7790 (H2) and R8A7791 (M2) SoCs.
The patches are pretty self-explanatory and described in their respective commit message. The R8A7790 and R8A7791 datasheets are unfortunately not publicly available.
The code is available in my git tree at
git://linuxtv.org/pinchartl/fbdev.git clocks/ccf/rcar-gen2
The branch is based on the clk-prepare patches I've posted earlier on the list ("[PATCH 00/12] Prepare various SH/R Mobile/Car drivers for CCF migration"), themselves rebased on top of renesas-devel-v3.12-20131119.
Changes compared to v2:
- Fixed I2C MSTP clocks parents (hp -> p)
- Added Z and Z2 clocks
- Added r8a7791 clocks to DT
Changes compared to v1:
- The core CPG clocks driver now supports the r8a7791 SoC in addition to the r8a7790. They are collectively refered to as 'R-Car Gen2'. The driver has thus been renamed to clk-rcar-gen2.c. The DT bindings have been updated accordingly.
- Several MSTP clocks have been added to the r8a7790-clock.h header and a new header has been added for the r8a7791
- The r8a7790 dtsi patches that add and reference clocks have been added to this series.
Laurent Pinchart (8):
clk: shmobile: Add R-Car Gen2 clocks support
clk: shmobile: Add DIV6 clock support
clk: shmobile: Add MSTP clock support
ARM: shmobile: r8a7790: Add clock index macros for DT sources
ARM: shmobile: r8a7791: Add clock index macros for DT sources
ARM: shmobile: r8a7790: Add clocks
ARM: shmobile: r8a7790: Reference clocks
ARM: shmobile: r8a7791: Add clocks
.../bindings/clock/renesas,cpg-div6-clocks.txt | 28 ++ .../bindings/clock/renesas,cpg-mstp-clocks.txt | 48 +++ .../clock/renesas,rcar-gen2-cpg-clocks.txt | 32 ++ arch/arm/boot/dts/r8a7790.dtsi | 326 +++++++++++++++++++++ arch/arm/boot/dts/r8a7791.dtsi | 312 ++++++++++++++++++++ drivers/clk/shmobile/Makefile | 7 +- drivers/clk/shmobile/clk-div6.c | 185 ++++++++++++ drivers/clk/shmobile/clk-mstp.c | 229 +++++++++++++++ drivers/clk/shmobile/clk-rcar-gen2.c | 298 +++++++++++++++++++ include/dt-bindings/clock/r8a7790-clock.h | 100 +++++++ include/dt-bindings/clock/r8a7791-clock.h | 105 +++++++ include/linux/clk/shmobile.h | 19 ++ 12 files changed, 1688 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt create mode 100644 Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt create mode 100644 drivers/clk/shmobile/clk-div6.c create mode 100644 drivers/clk/shmobile/clk-mstp.c create mode 100644 drivers/clk/shmobile/clk-rcar-gen2.c create mode 100644 include/dt-bindings/clock/r8a7790-clock.h create mode 100644 include/dt-bindings/clock/r8a7791-clock.h create mode 100644 include/linux/clk/shmobile.h
Signature · 3 lines
Regards, Laurent Pinchart
PATCH v3 1/8 clk: shmobile: Add R-Car Gen2 clocks support
The R-Car Gen2 SoCs (R8A7790 and R8A7791) have several clocks that are too custom to be supported in a generic driver. Those clocks can be divided in two categories:
- Fixed rate clocks with multiplier and divisor set according to boot mode configuration
- Custom divider clocks with SoC-specific divider values
This driver supports both.
--- .../clock/renesas,rcar-gen2-cpg-clocks.txt | 32 +++ drivers/clk/shmobile/Makefile | 5 +- drivers/clk/shmobile/clk-rcar-gen2.c | 298 +++++++++++++++++++++ include/linux/clk/shmobile.h | 19 ++ 4 files changed, 353 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt create mode 100644 drivers/clk/shmobile/clk-rcar-gen2.c create mode 100644 include/linux/clk/shmobile.h
Documentation/devicetree/bindings/clock/renesas,rcar-gen2-cpg-clocks.txt new file +32 -0
@@ -0,0 +1,32 @@ +* Renesas R-Car Gen2 Clock Pulse Generator (CPG) + +The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs +and several fixed ratio dividers. + +Required Properties: + + - compatible: Must be one of + - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG + - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG + - "renesas,rcar-gen2-cpg-clocks" for the generic R-Car Gen2 CPG + + - reg: Base address and length of the memory resource used by the CPG + + - clocks: Reference to the parent clock + - #clock-cells: Must be 1 + - clock-output-names: The names of the clocks. Supported clocks are "main", + "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1" and "z" + + +Example +------- + + cpg_clocks: cpg_clocks at e6150000 { + compatible = "renesas,r8a7790-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0, "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "sd1", "z"; + };
drivers/clk/shmobile/Makefile +4 -1
@@ -1,3 +1,6 @@ -obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o +obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o +obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o +obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o + # for emply built-in.o obj-n := dummy
drivers/clk/shmobile/clk-rcar-gen2.c new file +298 -0
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include/linux/clk/shmobile.h new file +19 -0
@@ -0,0 +1,19 @@ +/* +* Copyright 2013 Ideas On Board SPRL +* +* Contact: Laurent Pinchart <[email protected]> +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +*/ + +#ifndef __LINUX_CLK_SHMOBILE_H_ +#define __LINUX_CLK_SHMOBILE_H_ + +#include <linux/types.h> + +void rcar_gen2_clocks_init (u32 mode); + +#endif
Signature · 1 line
1.8.3.2
PATCH v3 2/8 clk: shmobile: Add DIV6 clock support
In reply to Laurent PinchartDIV6 clocks are divider gate clocks controlled through a single register. The divider is expressed on 6 bits, hence the name, and can take values from 1/1 to 1/64.
Those clocks are found on Renesas ARM SoCs.
--- .../bindings/clock/renesas,cpg-div6-clocks.txt | 28 ++++ drivers/clk/shmobile/Makefile | 1 + drivers/clk/shmobile/clk-div6.c | 185 +++++++++++++++++++++ 3 files changed, 214 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt create mode 100644 drivers/clk/shmobile/clk-div6.c
Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt new file +28 -0
@@ -0,0 +1,28 @@ +* Renesas CPG DIV6 Clock + +The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse +Generator (CPG). They clock input is divided by a configurable factor from 1 +to 64. + +Required Properties: + + - compatible: Must be one of the following + - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks + - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks + - "renesas,cpg-div6-clock" for generic DIV6 clocks + - reg: Base address and length of the memory resource used by the DIV6 clock + - clocks: Reference to the parent clock + - #clock-cells: Must be 0 + - clock-output-names: The name of the clock as a free-form string + + +Example +------- + + sd2_clk: sd2_clk at e6150078 { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150078 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd2"; + };
drivers/clk/shmobile/Makefile +1 -0
@@ -1,6 +1,7 @@ obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o +obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o # for emply built-in.o obj-n := dummy
drivers/clk/shmobile/clk-div6.c new file +185 -0
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Signature · 1 line
1.8.3.2
PATCH v3 3/8 clk: shmobile: Add MSTP clock support
In reply to Laurent PinchartMSTP clocks are gate clocks controlled through a register that handles up to 32 clocks. The register is often sparsely populated.
Those clocks are found on Renesas ARM SoCs.
--- .../bindings/clock/renesas,cpg-mstp-clocks.txt | 48 +++++ drivers/clk/shmobile/Makefile | 1 + drivers/clk/shmobile/clk-mstp.c | 229 +++++++++++++++++++++ 3 files changed, 278 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt create mode 100644 drivers/clk/shmobile/clk-mstp.c
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +48 -0
@@ -0,0 +1,48 @@ +* Renesas CPG Module Stop (MSTP) Clocks + +The CPG can gate SoC device clocks. The gates are organized in groups of up to +32 gates. + +This device tree binding describes a single 32 gate clocks group per node. +Clocks are referenced by user nodes by the MSTP node phandle and the clock +index in the group, from 0 to 31. + +Required Properties: + + - compatible: Must be one of the following + - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks + - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks + - "renesas,cpg-mstp-clock" for generic MSTP gate clocks + - reg: Base address and length of the memory resource used by the MSTP + clocks + - clocks: Reference to the parent clocks + - #clock-cells: Must be 1 + - clock-output-names: The name of the clocks as free-form strings + - renesas,indices: Indices of the gate clocks into the group (0 to 31) + +The clocks, clock-output-names and renesas,indices properties contain one +entry per gate clock. The MSTP groups are sparsely populated. Unimplemented +gate clocks must not be declared. + + +Example +------- + + #include <dt-bindings/clock/r8a7790-clock.h> + + mstp3_clks: mstp3_clks at e615013c { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, + <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, + <&mmc0_clk>; + #clock-cells = <1>; + clock-output-names = + "tpu0", "mmcif1", "sdhi3", "sdhi2", + "sdhi1", "sdhi0", "mmcif0"; + renesas,clock-indices = < + R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 + R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 + R8A7790_CLK_MMCIF0 + >; + };
drivers/clk/shmobile/Makefile +1 -0
@@ -2,6 +2,7 @@ obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-div6.o +obj-$(CONFIG_ARCH_SHMOBILE_MULTI) += clk-mstp.o # for emply built-in.o obj-n := dummy
drivers/clk/shmobile/clk-mstp.c new file +229 -0
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Signature · 1 line
1.8.3.2
PATCH v3 3/8 clk: shmobile: Add MSTP clock support
Quoted 2 lines · Laurent Pinchart
MSTP clocks are gate clocks controlled through a register that handles up to 32 clocks. The register is often sparsely populated.
Does that mean some clocks aren't wired up, or that some clocks don't exist at all?
What is the behaviour of the unpopulated bits?
Quoted 26 lines
Those clocks are found on Renesas ARM SoCs.
Cc devicetree at vger.kernel.orgSigned-off-by Laurent Pinchart <[email protected]>--- .../bindings/clock/renesas,cpg-mstp-clocks.txt | 48 +++++ drivers/clk/shmobile/Makefile | 1 + drivers/clk/shmobile/clk-mstp.c | 229 +++++++++++++++++++++ 3 files changed, 278 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt create mode 100644 drivers/clk/shmobile/clk-mstp.cDocumentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +7
-0@@ -0,0 +1,48 @@ +* Renesas CPG Module Stop (MSTP) Clocks + +The CPG can gate SoC device clocks. The gates are organized in groups of up to +32 gates. + +This device tree binding describes a single 32 gate clocks group per node. +Clocks are referenced by user nodes by the MSTP node phandle and the clock
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt line 17
Quoted 10 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +10
-0+index in the group, from 0 to 31. + +Required Properties: + + - compatible: Must be one of the following + - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gate clocks + - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate clocks + - "renesas,cpg-mstp-clock" for generic MSTP gate clocks + - reg: Base address and length of the memory resource used by the MSTP + clocks
There are two entries in the example, the code seems to assume they are particular registers, but this implies one.
Are these not part of a larger bank of registers?
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt line 18
Quoted 1 line
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +1
-0+ - clocks: Reference to the parent clocks
How many, and what do they correspond to?
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt line 21
Quoted 3 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +3
-0+ - #clock-cells: Must be 1 + - clock-output-names: The name of the clocks as free-form strings + - renesas,indices: Indices of the gate clocks into the group (0 to 31)
The description of this property doesn't describe half of what it means. I believe something like the below does:
- renesas,indices: A list of clock IDs (single cells), one for each clock present. Each entry may correspond to a clock-output-names entry at the same index, and its location in the list defines the corresponding clock-specifier for the entry.
I'd imagine we have a few sparse clocks by now, and we might be able to make this more uniform. But I may be mistaken.
[...]
Quoted 18 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +18
-0+static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) +{ + struct mstp_clock *clock = to_mstp_clock(hw); + struct mstp_clock_group *group = clock->group; + u32 bitmask = BIT(clock->bit_index); + unsigned long flags; + unsigned int i; + u32 value; + + spin_lock_irqsave(&group->lock, flags); + + value = clk_readl(group->smstpcr); + if (enable) + value &= ~bitmask; + else + value |= bitmask; + clk_writel(value, group->smstpcr); +
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
Quoted 10 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +10
-0+ spin_unlock_irqrestore(&group->lock, flags); + + if (!enable || !group->mstpsr) + return 0; + + for (i = 1000; i > 0; --i) { + if (!(clk_readl(group->mstpsr) & bitmask)) + break; + cpu_relax(); + }
Any particular reason for 1000 times? Is there a known minimum time to switch a clock between disabled and enabled? A comment would be nice.
Cheers,
Mark.
PATCH v3 3/8 clk: shmobile: Add MSTP clock support
Hi Mark,
Thank you for the quick review, much appreciated.
Quoted 6 lines · On Tuesday 19 November 2013 16:28:21 Mark Rutland wrote:
Quoted 2 lines · Laurent Pinchart
MSTP clocks are gate clocks controlled through a register that handles up to 32 clocks. The register is often sparsely populated.
Does that mean some clocks aren't wired up, or that some clocks don't exist at all?
It means that some of the bits don't control anything.
Quoted 1 line
What is the behaviour of the unpopulated bits?
According to the datasheet they're reserved, read-only, and read an unspecified value that is to be written back without modification when writing the register.
Quoted 40 lines
Quoted 40 lines
Those clocks are found on Renesas ARM SoCs.
Cc: devicetree at vger.kernel.org
Signed-off-by: Laurent Pinchart
<[email protected]>
---.../bindings/clock/renesas,cpg-mstp-clocks.txt | 48 +++++ drivers/clk/shmobile/Makefile | 1 + drivers/clk/shmobile/clk-mstp.c | 229 ++++++++++++++++ 3 files changed, 278 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt create mode 100644 drivers/clk/shmobile/clk-mstp.cdiff --git
a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txtb/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txtnew file mode 100644
index 0000000..126b17eDocumentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +3
-0@@ -0,0 +1,48 @@ +* Renesas CPG Module Stop (MSTP) Clocks + +The CPG can gate SoC device clocks. The gates are organized in groups ofup to
+32 gates.Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +2
-0+ +This device tree binding describes a single 32 gate clocks group pernode.
+Clocks are referenced by user nodes by the MSTP node phandle and the clockDocumentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +6
-0+index in the group, from 0 to 31. + +Required Properties: + + - compatible: Must be one of the following + - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gateclocks
Quoted 8 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt line 17
Quoted 5 lines
+ - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate
clocksDocumentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +3
-0+ - "renesas,cpg-mstp-clock" for generic MSTP gate clocks + - reg: Base address and length of the memory resource used by the MSTP + clocksThere are two entries in the example, the code seems to assume they are particular registers, but this implies one.
There can be one or two registers, depending on the hardware. The first register is always required and controls the clocks, the second register is optional (in the sense that it's not implemented for some of the MSTP instances) and reports the clock status.
Quoted 1 line
Are these not part of a larger bank of registers?
They are. Here's the memory map for the r8a7791 for instance.
MSTPSR0 H'E615 0030
MSTPSR1 H'E615 0038
MSTPSR2 H'E615 0040
MSTPSR3 H'E615 0048
MSTPSR4 H'E615 004C
MSTPSR5 H'E615 003C
MSTPSR6 H'E615 01C0
MSTPSR7 H'E615 01C4
MSTPSR8 H'E615 09A0
MSTPSR9 H'E615 09A4
MSTPSR10 H'E615 09A8
MSTPSR11 H'E615 09AC
SMSTPCR0 H'E615 0130
SMSTPCR1 H'E615 0134
SMSTPCR2 H'E615 0138
SMSTPCR3 H'E615 013C
SMSTPCR4 H'E615 0140
SMSTPCR5 H'E615 0144
SMSTPCR6 H'E615 0148
SMSTPCR7 H'E615 014C
SMSTPCR8 H'E615 0990
SMSTPCR9 H'E615 0994
SMSTPCR10 H'E615 0998
SMSTPCR11 H'E615 099C
I've pondered whether we should use a single device node for all the MSTP clocks, but I don't think it would be very practical. Not only would we need to encode all bit positions, we also would have to encode register offsets in DT. This would become pretty messy in a single node.
Quoted 3 lines
Quoted 1 line
+ - clocks: Reference to the parent clocks
How many, and what do they correspond to?
What about
- clocks: Reference to the parent clocks, one per output clock. The parents must appear in the same order as the output clocks.
Quoted 11 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt line 21
Quoted 3 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +3
-0+ - #clock-cells: Must be 1 + - clock-output-names: The name of the clocks as free-form strings + - renesas,indices: Indices of the gate clocks into the group (0 to 31)The description of this property doesn't describe half of what it means. I believe something like the below does:
- renesas,indices: A list of clock IDs (single cells), one for each clock present. Each entry may correspond to a clock-output-names entry at the same index, and its location in the list defines the corresponding clock-specifier for the entry.
I might be mistaken, but doesn't "its location in the list defines the corresponding clock-specifier for the entry" imply that clock specifiers use the location in the list as the clock ID instead of the numerical value of the indices entry ? Each entry in the renesas,indices list corresponds to one clocks entry and one clock-output-names entry, and clock users reference an MSTP clock using the value of its indices entry, not the position of the entry.
Quoted 28 lines
I'd imagine we have a few sparse clocks by now, and we might be able to make this more uniform. But I may be mistaken.
[...]
Quoted 23 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +23
-0+static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) +{ + struct mstp_clock *clock = to_mstp_clock(hw); + struct mstp_clock_group *group = clock->group; + u32 bitmask = BIT(clock->bit_index); + unsigned long flags; + unsigned int i; + u32 value; + + spin_lock_irqsave(&group->lock, flags); + + value = clk_readl(group->smstpcr); + if (enable) + value &= ~bitmask; + else + value |= bitmask; + clk_writel(value, group->smstpcr); + + spin_unlock_irqrestore(&group->lock, flags); + + if (!enable || !group->mstpsr) + return 0; +
Quoted 8 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
Quoted 5 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +5
-0+ for (i = 1000; i > 0; --i) { + if (!(clk_readl(group->mstpsr) & bitmask)) + break; + cpu_relax(); + }Any particular reason for 1000 times? Is there a known minimum time to switch a clock between disabled and enabled? A comment would be nice.
There's no particular reason, the datasheet doesn't provide any useful information. I've just copied that value from existing C code.
Signature · 3 lines
Regards, Laurent Pinchart
PATCH v3 3/8 clk: shmobile: Add MSTP clock support
Quoted 12 lines · Laurent Pinchart
Hi Mark,
Thank you for the quick review, much appreciated.
Quoted 6 lines · On Tuesday 19 November 2013 16:28:21 Mark Rutland wrote:
Quoted 2 lines · Laurent Pinchart
MSTP clocks are gate clocks controlled through a register that handles up to 32 clocks. The register is often sparsely populated.
Does that mean some clocks aren't wired up, or that some clocks don't exist at all?
Quoted 7 lines
It means that some of the bits don't control anything.
Quoted 1 line
What is the behaviour of the unpopulated bits?
According to the datasheet they're reserved, read-only, and read an unspecified value that is to be written back without modification when writing the register.
Ok.
Quoted 50 lines
Quoted 41 lines
Quoted 41 lines
Those clocks are found on Renesas ARM SoCs.
Cc: devicetree at vger.kernel.org
Signed-off-by: Laurent Pinchart
<[email protected]>
---.../bindings/clock/renesas,cpg-mstp-clocks.txt | 48 +++++ drivers/clk/shmobile/Makefile | 1 + drivers/clk/shmobile/clk-mstp.c | 229 ++++++++++++++++ 3 files changed, 278 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt create mode 100644 drivers/clk/shmobile/clk-mstp.cdiff --git
a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txtb/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txtnew file mode 100644
index 0000000..126b17eDocumentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +3
-0@@ -0,0 +1,48 @@ +* Renesas CPG Module Stop (MSTP) Clocks + +The CPG can gate SoC device clocks. The gates are organized in groups ofup to
+32 gates.Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +2
-0+ +This device tree binding describes a single 32 gate clocks group pernode.
+Clocks are referenced by user nodes by the MSTP node phandle and the clockDocumentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +6
-0+index in the group, from 0 to 31. + +Required Properties: + + - compatible: Must be one of the following + - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gateclocks
Quoted 8 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt line 17
Quoted 5 lines
+ - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate
clocksDocumentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +3
-0+ - "renesas,cpg-mstp-clock" for generic MSTP gate clocks + - reg: Base address and length of the memory resource used by the MSTP + clocksThere are two entries in the example, the code seems to assume they are particular registers, but this implies one.
Quoted 4 lines
There can be one or two registers, depending on the hardware. The first register is always required and controls the clocks, the second register is optional (in the sense that it's not implemented for some of the MSTP instances) and reports the clock status.
Ok. The documentation should note this.
Quoted 36 lines
Quoted 2 lines
Are these not part of a larger bank of registers?
They are. Here's the memory map for the r8a7791 for instance.
MSTPSR0 H'E615 0030
MSTPSR1 H'E615 0038
MSTPSR2 H'E615 0040
MSTPSR3 H'E615 0048
MSTPSR4 H'E615 004C
MSTPSR5 H'E615 003C
MSTPSR6 H'E615 01C0
MSTPSR7 H'E615 01C4
MSTPSR8 H'E615 09A0
MSTPSR9 H'E615 09A4
MSTPSR10 H'E615 09A8
MSTPSR11 H'E615 09ACSMSTPCR0 H'E615 0130
SMSTPCR1 H'E615 0134
SMSTPCR2 H'E615 0138
SMSTPCR3 H'E615 013C
SMSTPCR4 H'E615 0140
SMSTPCR5 H'E615 0144
SMSTPCR6 H'E615 0148
SMSTPCR7 H'E615 014C
SMSTPCR8 H'E615 0990
SMSTPCR9 H'E615 0994
SMSTPCR10 H'E615 0998
SMSTPCR11 H'E615 099CI've pondered whether we should use a single device node for all the MSTP clocks, but I don't think it would be very practical. Not only would we need to encode all bit positions, we also would have to encode register offsets in DT. This would become pretty messy in a single node.
Quoted 8 lines
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+ - clocks: Reference to the parent clocks
How many, and what do they correspond to?
What about
- clocks: Reference to the parent clocks, one per output clock. The parents must appear in the same order as the output clocks.
That sounds reasonable.
Quoted 13 lines
Quoted 5 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt line 21
Quoted 4 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +3
-0+ - #clock-cells: Must be 1 + - clock-output-names: The name of the clocks as free-form strings + - renesas,indices: Indices of the gate clocks into the group (0 to 31)Quoted 7 lines
The description of this property doesn't describe half of what it means. I believe something like the below does:
- renesas,indices: A list of clock IDs (single cells), one for each clock present. Each entry may correspond to a clock-output-names entry at the same index, and its location in the list defines the corresponding clock-specifier for the entry.
Quoted 7 lines
I might be mistaken, but doesn't "its location in the list defines the corresponding clock-specifier for the entry" imply that clock specifiers use the location in the list as the clock ID instead of the numerical value of the indices entry ? Each entry in the renesas,indices list corresponds to one clocks entry and one clock-output-names entry, and clock users reference an MSTP clock using the value of its indices entry, not the position of the entry.
Sorry, the code confused me. Having read over it again, I'm even more confused.
You said the registers were sparesly populated, but the code assumes that the bits start at 0 and the set of populated bits are contiguous, which is not what I would describe that as sparse. Are the bits always contiguous?
I thought the bits in the register were truly sparse (i.e. you could have two bits which were at either end of the register), and the indices property allowed you to define the set of bits which were valid.
As far as I can see from cpg_mstp_clocks_init and cpg_mstp_clock_register, the indices property assings the set of IDs for consumers to use, and I don't see what the point of that is if we already have a well-defined linear index (the bit position in the register) which we could use instead, which also makes the binding and code simpler.
Quoted 38 lines
Quoted 29 lines
I'd imagine we have a few sparse clocks by now, and we might be able to make this more uniform. But I may be mistaken.
[...]
Quoted 23 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +23
-0+static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) +{ + struct mstp_clock *clock = to_mstp_clock(hw); + struct mstp_clock_group *group = clock->group; + u32 bitmask = BIT(clock->bit_index); + unsigned long flags; + unsigned int i; + u32 value; + + spin_lock_irqsave(&group->lock, flags); + + value = clk_readl(group->smstpcr); + if (enable) + value &= ~bitmask; + else + value |= bitmask; + clk_writel(value, group->smstpcr); + + spin_unlock_irqrestore(&group->lock, flags); + + if (!enable || !group->mstpsr) + return 0; +Quoted 8 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
Quoted 5 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +5
-0+ for (i = 1000; i > 0; --i) { + if (!(clk_readl(group->mstpsr) & bitmask)) + break; + cpu_relax(); + }Any particular reason for 1000 times? Is there a known minimum time to switch a clock between disabled and enabled? A comment would be nice.
Quoted 2 lines
There's no particular reason, the datasheet doesn't provide any useful information. I've just copied that value from existing C code.
Any chance it might work without?
Thanks,
Mark.
PATCH v3 3/8 clk: shmobile: Add MSTP clock support
Hi Mark,
Quoted 70 lines · On Tuesday 19 November 2013 18:19:36 Mark Rutland wrote:
Quoted 8 lines · Laurent Pinchart
Quoted 6 lines · On Tuesday 19 November 2013 16:28:21 Mark Rutland wrote:
Quoted 2 lines · Laurent Pinchart
MSTP clocks are gate clocks controlled through a register that handles up to 32 clocks. The register is often sparsely populated.
Does that mean some clocks aren't wired up, or that some clocks don't exist at all?
Quoted 7 lines
It means that some of the bits don't control anything.
Quoted 1 line
What is the behaviour of the unpopulated bits?
According to the datasheet they're reserved, read-only, and read an unspecified value that is to be written back without modification when writing the register.
Ok.
Quoted 51 lines
Quoted 50 lines
Quoted 45 lines
Those clocks are found on Renesas ARM SoCs.
Cc: devicetree at vger.kernel.org
Signed-off-by: Laurent Pinchart
<[email protected]>
---.../bindings/clock/renesas,cpg-mstp-clocks.txt | 48 +++++ drivers/clk/shmobile/Makefile | 1 + drivers/clk/shmobile/clk-mstp.c | 229 ++++++++++++ 3 files changed, 278 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt create mode 100644 drivers/clk/shmobile/clk-mstp.cdiff --git
a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txtb/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txtnew file mode 100644
index 0000000..126b17e
---/dev/null
+++b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txtDocumentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +3
-0@@ -0,0 +1,48 @@ +* Renesas CPG Module Stop (MSTP) Clocks + +The CPG can gate SoC device clocks. The gates are organized in groupsof up to
+32 gates.(quoted diff) +2
-0+ +This device tree binding describes a single 32 gate clocks group pernode.
+Clocks are referenced by user nodes by the MSTP node phandle and the clockDocumentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +6
-0+index in the group, from 0 to 31. + +Required Properties: + + - compatible: Must be one of the following + - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTP gateclocks
+ - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP gate
clocks(quoted diff) +2
-0+ - "renesas,cpg-mstp-clock" for generic MSTP gate clocks + - reg: Base address and length of the memory resource used by theQuoted 2 lines
MSTP
+ clocksThere are two entries in the example, the code seems to assume they are particular registers, but this implies one.
Quoted 6 lines
Quoted 4 lines
There can be one or two registers, depending on the hardware. The first register is always required and controls the clocks, the second register is optional (in the sense that it's not implemented for some of the MSTP instances) and reports the clock status.
Ok. The documentation should note this.
What about
- reg: Base address and length of the I/O mapped registers used by the MSTP clocks. The first register is the clock control register and is mandatory. The second register is the clock status register and is optional when not implemented in hardware.
Quoted 68 lines
Quoted 35 lines
Quoted 1 line
Are these not part of a larger bank of registers?
They are. Here's the memory map for the r8a7791 for instance.
MSTPSR0 H'E615 0030
MSTPSR1 H'E615 0038
MSTPSR2 H'E615 0040
MSTPSR3 H'E615 0048
MSTPSR4 H'E615 004C
MSTPSR5 H'E615 003C
MSTPSR6 H'E615 01C0
MSTPSR7 H'E615 01C4
MSTPSR8 H'E615 09A0
MSTPSR9 H'E615 09A4
MSTPSR10 H'E615 09A8
MSTPSR11 H'E615 09ACSMSTPCR0 H'E615 0130
SMSTPCR1 H'E615 0134
SMSTPCR2 H'E615 0138
SMSTPCR3 H'E615 013C
SMSTPCR4 H'E615 0140
SMSTPCR5 H'E615 0144
SMSTPCR6 H'E615 0148
SMSTPCR7 H'E615 014C
SMSTPCR8 H'E615 0990
SMSTPCR9 H'E615 0994
SMSTPCR10 H'E615 0998
SMSTPCR11 H'E615 099CI've pondered whether we should use a single device node for all the MSTP clocks, but I don't think it would be very practical. Not only would we need to encode all bit positions, we also would have to encode register offsets in DT. This would become pretty messy in a single node.
Quoted 8 lines
Quoted 3 lines
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+ - clocks: Reference to the parent clocks
How many, and what do they correspond to?
What about
- clocks: Reference to the parent clocks, one per output clock. The parents must appear in the same order as the output clocks.
That sounds reasonable.
Quoted 14 lines
Quoted 5 lines
Quoted 4 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +3
-0+ - #clock-cells: Must be 1 + - clock-output-names: The name of the clocks as free-form strings + - renesas,indices: Indices of the gate clocks into the group (0 to31)
Quoted 8 lines
The description of this property doesn't describe half of what it means. I believe something like the below does:
- renesas,indices: A list of clock IDs (single cells), one for each
clock present. Each entry may correspond to a clock-output-names entry at the same index, and its location in the list defines the corresponding clock-specifier for the entry.
Quoted 7 lines
I might be mistaken, but doesn't "its location in the list defines the corresponding clock-specifier for the entry" imply that clock specifiers use the location in the list as the clock ID instead of the numerical value of the indices entry ? Each entry in the renesas,indices list corresponds to one clocks entry and one clock-output-names entry, and clock users reference an MSTP clock using the value of its indices entry, not the position of the entry.
Quoted 7 lines
Sorry, the code confused me. Having read over it again, I'm even more confused.
You said the registers were sparesly populated, but the code assumes that the bits start at 0 and the set of populated bits are contiguous, which is not what I would describe that as sparse. Are the bits always contiguous?
They're not, and the code doesn't assume so. The driver loops over all the clocks using the position in the renesas,indices array as the loop counter i. It then retrieves the output name, the parent and the index and registers the clock. When registration succeeds, the clock is stored in the clks array at the index corresponding to the renesas,indices value. The clks array is thus sparsely populated, exactly as the MSTP register.
Quoted 48 lines
I thought the bits in the register were truly sparse (i.e. you could have two bits which were at either end of the register), and the indices property allowed you to define the set of bits which were valid.
As far as I can see from
cpg_mstp_clocks_initandcpg_mstp_clock_register, the indices property assings the set of IDs for consumers to use, and I don't see what the point of that is if we already have a well-defined linear index (the bit position in the register) which we could use instead, which also makes the binding and code simpler.Quoted 37 lines
Quoted 36 lines
I'd imagine we have a few sparse clocks by now, and we might be able to make this more uniform. But I may be mistaken.
[...]
Quoted 18 lines
drivers/clk/shmobile/clk-mstp.c new file +18
-0+static int cpg_mstp_clock_endisable (struct clk_hw *hw,bool enable) +{ +struct mstp_clock *clock =to_mstp_clock (hw); +struct mstp_clock_group *group = clock->group; +u32 bitmask =BIT (clock->bit_index); +unsigned long flags; +unsigned int i; +u32 value; + +spin_lock_irqsave (&group->lock, flags); + + value =clk_readl (group->smstpcr); +if (enable) + value &= ~bitmask; +else + value |= bitmask; +clk_writel (value, group->smstpcr); +drivers/clk/shmobile/clk-mstp.c line 83
Quoted 10 lines
drivers/clk/shmobile/clk-mstp.c new file +10
-0+spin_unlock_irqrestore (&group->lock, flags); + +if (!enable || !group->mstpsr) +return 0 ; + +for (i =1000 ; i >0 ; --i) { +if (!(clk_readl (group->mstpsr) & bitmask)) +break ; +cpu_relax (); + }Any particular reason for 1000 times? Is there a known minimum time to switch a clock between disabled and enabled? A comment would be nice.
Quoted 4 lines
Quoted 2 lines
There's no particular reason, the datasheet doesn't provide any useful information. I've just copied that value from existing C code.
Any chance it might work without?
Yes, with roughly a 75% chance :-) Without this look I get a crash around once every four times with the video processing devices. Other devices are affected as well, but delays in their respective drivers hide the problem.
Signature · 3 lines
Regards, Laurent Pinchart
PATCH v3 3/8 clk: shmobile: Add MSTP clock support
Hi Mark,
I'd like to send v4 of this series soon, hopefully for the last time. Would you be able to reply to the two issues that are still left and discussed below ? That would be really appreciated.
Quoted 226 lines · On Wednesday 20 November 2013 22:54:58 Laurent Pinchart wrote:
Quoted 73 lines · On Tuesday 19 November 2013 18:19:36 Mark Rutland wrote:
Quoted 8 lines · Laurent Pinchart
Quoted 6 lines · On Tuesday 19 November 2013 16:28:21 Mark Rutland wrote:
Quoted 2 lines · Laurent Pinchart
MSTP clocks are gate clocks controlled through a register that handles up to 32 clocks. The register is often sparsely populated.
Does that mean some clocks aren't wired up, or that some clocks don't exist at all?
Quoted 7 lines
It means that some of the bits don't control anything.
Quoted 1 line
What is the behaviour of the unpopulated bits?
According to the datasheet they're reserved, read-only, and read an unspecified value that is to be written back without modification when writing the register.
Ok.
Quoted 54 lines
Quoted 53 lines
Quoted 48 lines
Those clocks are found on Renesas ARM SoCs.
Cc: devicetree at vger.kernel.org
Signed-off-by: Laurent Pinchart
<[email protected]>
---.../bindings/clock/renesas,cpg-mstp-clocks.txt | 48 +++++ drivers/clk/shmobile/Makefile | 1 + drivers/clk/shmobile/clk-mstp.c | 229 ++++++++++ 3 files changed, 278 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt create mode 100644 drivers/clk/shmobile/clk-mstp.cdiff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp- clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp- clocks.txt
new file mode 100644
index 0000000..126b17e
---/dev/null
+++
b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp- clocks.txtDocumentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +3
-0@@ -0,0 +1,48 @@ +* Renesas CPG Module Stop (MSTP) Clocks + +The CPG can gate SoC device clocks. The gates are organized ingroups of up to
+32 gates.(quoted diff) +2
-0+ +This device tree binding describes a single 32 gate clocks groupper node.
+Clocks are referenced by user nodes by the MSTP node phandle and the clockDocumentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +6
-0+index in the group, from 0 to 31. + +Required Properties: + + - compatible: Must be one of the following + - "renesas,r8a7790-mstp-clocks" for R8A7790 (R-Car H2) MSTPgate clocks
+ - "renesas,r8a7791-mstp-clocks" for R8A7791 (R-Car M2) MSTP
gate clocks(quoted diff) +2
-0+ - "renesas,cpg-mstp-clock" for generic MSTP gate clocks + - reg: Base address and length of the memory resource used by theQuoted 2 lines
MSTP
+ clocksThere are two entries in the example, the code seems to assume they are particular registers, but this implies one.
Quoted 6 lines
Quoted 4 lines
There can be one or two registers, depending on the hardware. The first register is always required and controls the clocks, the second register is optional (in the sense that it's not implemented for some of the MSTP instances) and reports the clock status.
Ok. The documentation should note this.
What about
- reg: Base address and length of the I/O mapped registers used by the
MSTP clocks. The first register is the clock control register and is mandatory. The second register is the clock status register and is optional when not implemented in hardware.Quoted 67 lines
Quoted 35 lines
Quoted 1 line
Are these not part of a larger bank of registers?
They are. Here's the memory map for the r8a7791 for instance.
MSTPSR0 H'E615 0030
MSTPSR1 H'E615 0038
MSTPSR2 H'E615 0040
MSTPSR3 H'E615 0048
MSTPSR4 H'E615 004C
MSTPSR5 H'E615 003C
MSTPSR6 H'E615 01C0
MSTPSR7 H'E615 01C4
MSTPSR8 H'E615 09A0
MSTPSR9 H'E615 09A4
MSTPSR10 H'E615 09A8
MSTPSR11 H'E615 09ACSMSTPCR0 H'E615 0130
SMSTPCR1 H'E615 0134
SMSTPCR2 H'E615 0138
SMSTPCR3 H'E615 013C
SMSTPCR4 H'E615 0140
SMSTPCR5 H'E615 0144
SMSTPCR6 H'E615 0148
SMSTPCR7 H'E615 014C
SMSTPCR8 H'E615 0990
SMSTPCR9 H'E615 0994
SMSTPCR10 H'E615 0998
SMSTPCR11 H'E615 099CI've pondered whether we should use a single device node for all the MSTP clocks, but I don't think it would be very practical. Not only would we need to encode all bit positions, we also would have to encode register offsets in DT. This would become pretty messy in a single node.
Quoted 8 lines
Quoted 3 lines
Quoted 1 line
+ - clocks: Reference to the parent clocks
How many, and what do they correspond to?
What about
- clocks: Reference to the parent clocks, one per output clock. The parents must appear in the same order as the output clocks.
That sounds reasonable.
Quoted 13 lines
Quoted 5 lines
Quoted 4 lines
Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt new file +3
-0+ - #clock-cells: Must be 1 + - clock-output-names: The name of the clocks as free-form strings + - renesas,indices: Indices of the gate clocks into the group (0to 31)
Quoted 7 lines
The description of this property doesn't describe half of what it means. I believe something like the below does:
- renesas,indices: A list of clock IDs (single cells), one for each clock present. Each entry may correspond to a clock-output-names entry at the same index, and its location in the list defines the corresponding clock-specifier for the entry.
Quoted 7 lines
I might be mistaken, but doesn't "its location in the list defines the corresponding clock-specifier for the entry" imply that clock specifiers use the location in the list as the clock ID instead of the numerical value of the indices entry ? Each entry in the renesas,indices list corresponds to one clocks entry and one clock-output-names entry, and clock users reference an MSTP clock using the value of its indices entry, not the position of the entry.
Quoted 7 lines
Sorry, the code confused me. Having read over it again, I'm even more confused.
You said the registers were sparesly populated, but the code assumes that the bits start at 0 and the set of populated bits are contiguous, which is not what I would describe that as sparse. Are the bits always contiguous?
They're not, and the code doesn't assume so. The driver loops over all the clocks using the position in the renesas,indices array as the loop counter i. It then retrieves the output name, the parent and the index and registers the clock. When registration succeeds, the clock is stored in the clks array at the index corresponding to the renesas,indices value. The clks array is thus sparsely populated, exactly as the MSTP register.
Quoted 48 lines
I thought the bits in the register were truly sparse (i.e. you could have two bits which were at either end of the register), and the indices property allowed you to define the set of bits which were valid.
As far as I can see from
cpg_mstp_clocks_initandcpg_mstp_clock_register, the indices property assings the set of IDs for consumers to use, and I don't see what the point of that is if we already have a well-defined linear index (the bit position in the register) which we could use instead, which also makes the binding and code simpler.Quoted 37 lines
Quoted 36 lines
I'd imagine we have a few sparse clocks by now, and we might be able to make this more uniform. But I may be mistaken.
[...]
Quoted 18 lines
drivers/clk/shmobile/clk-mstp.c new file +18
-0+static int cpg_mstp_clock_endisable (struct clk_hw *hw,bool enable) +{ +struct mstp_clock *clock =to_mstp_clock (hw); +struct mstp_clock_group *group = clock->group; +u32 bitmask =BIT (clock->bit_index); +unsigned long flags; +unsigned int i; +u32 value; + +spin_lock_irqsave (&group->lock, flags); + + value =clk_readl (group->smstpcr); +if (enable) + value &= ~bitmask; +else + value |= bitmask; +clk_writel (value, group->smstpcr); +drivers/clk/shmobile/clk-mstp.c line 83
Quoted 10 lines
drivers/clk/shmobile/clk-mstp.c new file +10
-0+spin_unlock_irqrestore (&group->lock, flags); + +if (!enable || !group->mstpsr) +return 0 ; + +for (i =1000 ; i >0 ; --i) { +if (!(clk_readl (group->mstpsr) & bitmask)) +break ; +cpu_relax (); + }Any particular reason for 1000 times? Is there a known minimum time to switch a clock between disabled and enabled? A comment would be nice.
Quoted 4 lines
Quoted 2 lines
There's no particular reason, the datasheet doesn't provide any useful information. I've just copied that value from existing C code.
Any chance it might work without?
Yes, with roughly a 75% chance :-) Without this look I get a crash around once every four times with the video processing devices. Other devices are affected as well, but delays in their respective drivers hide the problem.
Signature · 3 lines
Regards, Laurent Pinchart
PATCH v3 4/8 ARM: shmobile: r8a7790: Add clock index macros for DT sources
In reply to Laurent PinchartAdd macros usable by device tree sources to reference r8a7790 clocks by index.
--- include/dt-bindings/clock/r8a7790-clock.h | 100 ++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 include/dt-bindings/clock/r8a7790-clock.h
include/dt-bindings/clock/r8a7790-clock.h new file +100 -0
@@ -0,0 +1,100 @@ +/* +* Copyright 2013 Ideas On Board SPRL +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +*/ + +#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__ +#define __DT_BINDINGS_CLOCK_R8A7790_H__ + +/* CPG */ +#define R8A7790_CLK_MAIN 0 +#define R8A7790_CLK_PLL0 1 +#define R8A7790_CLK_PLL1 2 +#define R8A7790_CLK_PLL3 3 +#define R8A7790_CLK_LB 4 +#define R8A7790_CLK_QSPI 5 +#define R8A7790_CLK_SDH 6 +#define R8A7790_CLK_SD0 7 +#define R8A7790_CLK_SD1 8 +#define R8A7790_CLK_Z 9 + +/* MSTP1 */ +#define R8A7790_CLK_TMU1 11 +#define R8A7790_CLK_TMU3 21 +#define R8A7790_CLK_TMU2 22 +#define R8A7790_CLK_CMT0 24 +#define R8A7790_CLK_TMU0 25 +#define R8A7790_CLK_VSP1_DU1 27 +#define R8A7790_CLK_VSP1_DU0 28 +#define R8A7790_CLK_VSP1_RT 30 +#define R8A7790_CLK_VSP1_SY 31 + +/* MSTP2 */ +#define R8A7790_CLK_SCIFA2 2 +#define R8A7790_CLK_SCIFA1 3 +#define R8A7790_CLK_SCIFA0 4 +#define R8A7790_CLK_SCIFB0 6 +#define R8A7790_CLK_SCIFB1 7 +#define R8A7790_CLK_SCIFB2 16 +#define R8A7790_CLK_SYS_DMAC0 18 +#define R8A7790_CLK_SYS_DMAC1 19 + +/* MSTP3 */ +#define R8A7790_CLK_TPU0 4 +#define R8A7790_CLK_MMCIF1 5 +#define R8A7790_CLK_SDHI3 11 +#define R8A7790_CLK_SDHI2 12 +#define R8A7790_CLK_SDHI1 13 +#define R8A7790_CLK_SDHI0 14 +#define R8A7790_CLK_MMCIF0 15 +#define R8A7790_CLK_SSUSB 28 +#define R8A7790_CLK_CMT1 29 +#define R8A7790_CLK_USBDMAC0 30 +#define R8A7790_CLK_USBDMAC1 31 + +/* MSTP5 */ +#define R8A7790_CLK_THERMAL 22 +#define R8A7790_CLK_PWM 23 + +/* MSTP7 */ +#define R8A7790_CLK_EHCI 3 +#define R8A7790_CLK_HSUSB 4 +#define R8A7790_CLK_HSCIF1 16 +#define R8A7790_CLK_HSCIF0 17 +#define R8A7790_CLK_SCIF1 20 +#define R8A7790_CLK_SCIF0 21 +#define R8A7790_CLK_DU2 22 +#define R8A7790_CLK_DU1 23 +#define R8A7790_CLK_DU0 24 +#define R8A7790_CLK_LVDS1 25 +#define R8A7790_CLK_LVDS0 26 + +/* MSTP8 */ +#define R8A7790_CLK_VIN3 8 +#define R8A7790_CLK_VIN2 9 +#define R8A7790_CLK_VIN1 10 +#define R8A7790_CLK_VIN0 11 +#define R8A7790_CLK_ETHER 13 +#define R8A7790_CLK_SATA1 14 +#define R8A7790_CLK_SATA0 15 + +/* MSTP9 */ +#define R8A7790_CLK_GPIO5 7 +#define R8A7790_CLK_GPIO4 8 +#define R8A7790_CLK_GPIO3 9 +#define R8A7790_CLK_GPIO2 10 +#define R8A7790_CLK_GPIO1 11 +#define R8A7790_CLK_GPIO0 12 +#define R8A7790_CLK_RCAN1 15 +#define R8A7790_CLK_RCAN0 16 +#define R8A7790_CLK_IICDVFS 26 +#define R8A7790_CLK_I2C3 28 +#define R8A7790_CLK_I2C2 29 +#define R8A7790_CLK_I2C1 30 +#define R8A7790_CLK_I2C0 31 + +#endif /* __DT_BINDINGS_CLOCK_R8A7790_H__ */
Signature · 1 line
1.8.3.2
PATCH v3 5/8 ARM: shmobile: r8a7791: Add clock index macros for DT sources
In reply to Laurent PinchartAdd macros usable by device tree sources to reference r8a7791 clocks by index.
--- include/dt-bindings/clock/r8a7791-clock.h | 105 ++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 include/dt-bindings/clock/r8a7791-clock.h
include/dt-bindings/clock/r8a7791-clock.h new file +105 -0
@@ -0,0 +1,105 @@ +/* +* Copyright 2013 Ideas On Board SPRL +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +*/ + +#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__ +#define __DT_BINDINGS_CLOCK_R8A7791_H__ + +/* CPG */ +#define R8A7791_CLK_MAIN 0 +#define R8A7791_CLK_PLL0 1 +#define R8A7791_CLK_PLL1 2 +#define R8A7791_CLK_PLL3 3 +#define R8A7791_CLK_LB 4 +#define R8A7791_CLK_QSPI 5 +#define R8A7791_CLK_SDH 6 +#define R8A7791_CLK_SD0 7 +#define R8A7791_CLK_Z 8 + +/* MSTP1 */ +#define R8A7791_CLK_TMU1 11 +#define R8A7791_CLK_TMU3 21 +#define R8A7791_CLK_TMU2 22 +#define R8A7791_CLK_CMT0 24 +#define R8A7791_CLK_TMU0 25 +#define R8A7791_CLK_VSP1_DU1 27 +#define R8A7791_CLK_VSP1_DU0 28 +#define R8A7791_CLK_VSP1_SY 31 + +/* MSTP2 */ +#define R8A7791_CLK_SCIFA2 2 +#define R8A7791_CLK_SCIFA1 3 +#define R8A7791_CLK_SCIFA0 4 +#define R8A7791_CLK_SCIFB0 6 +#define R8A7791_CLK_SCIFB1 7 +#define R8A7791_CLK_SCIFB2 16 +#define R8A7791_CLK_DMAC 18 + +/* MSTP3 */ +#define R8A7791_CLK_TPU0 4 +#define R8A7791_CLK_SDHI2 11 +#define R8A7791_CLK_SDHI1 12 +#define R8A7791_CLK_SDHI0 14 +#define R8A7791_CLK_MMCIF0 15 +#define R8A7791_CLK_SSUSB 28 +#define R8A7791_CLK_CMT1 29 +#define R8A7791_CLK_USBDMAC0 30 +#define R8A7791_CLK_USBDMAC1 31 + +/* MSTP5 */ +#define R8A7791_CLK_THERMAL 22 +#define R8A7791_CLK_PWM 23 + +/* MSTP7 */ +#define R8A7791_CLK_HSUSB 4 +#define R8A7791_CLK_HSCIF2 13 +#define R8A7791_CLK_SCIF5 14 +#define R8A7791_CLK_SCIF4 15 +#define R8A7791_CLK_HSCIF1 16 +#define R8A7791_CLK_HSCIF0 17 +#define R8A7791_CLK_SCIF3 18 +#define R8A7791_CLK_SCIF2 19 +#define R8A7791_CLK_SCIF1 20 +#define R8A7791_CLK_SCIF0 21 +#define R8A7791_CLK_DU1 23 +#define R8A7791_CLK_DU0 24 +#define R8A7791_CLK_LVDS0 26 + +/* MSTP8 */ +#define R8A7791_CLK_VIN2 9 +#define R8A7791_CLK_VIN1 10 +#define R8A7791_CLK_VIN0 11 +#define R8A7791_CLK_ETHER 13 +#define R8A7791_CLK_SATA1 14 +#define R8A7791_CLK_SATA0 15 + +/* MSTP9 */ +#define R8A7791_CLK_GPIO7 4 +#define R8A7791_CLK_GPIO6 5 +#define R8A7791_CLK_GPIO5 7 +#define R8A7791_CLK_GPIO4 8 +#define R8A7791_CLK_GPIO3 9 +#define R8A7791_CLK_GPIO2 10 +#define R8A7791_CLK_GPIO1 11 +#define R8A7791_CLK_GPIO0 12 +#define R8A7791_CLK_RCAN1 15 +#define R8A7791_CLK_RCAN0 16 +#define R8A7791_CLK_I2C5 25 +#define R8A7791_CLK_IICDVFS 26 +#define R8A7791_CLK_I2C4 27 +#define R8A7791_CLK_I2C3 28 +#define R8A7791_CLK_I2C2 29 +#define R8A7791_CLK_I2C1 30 +#define R8A7791_CLK_I2C0 31 + +/* MSTP11 */ +#define R8A7791_CLK_SCIFA3 6 +#define R8A7791_CLK_SCIFA4 7 +#define R8A7791_CLK_SCIFA5 8 + +#endif /* __DT_BINDINGS_CLOCK_R8A7791_H__ */
Signature · 1 line
1.8.3.2
PATCH v3 5/8 ARM: shmobile: r8a7791: Add default PCIe bus clock
This patch adds a default PCIe bus clock node.
---
v3:
- By default, disable the PCIe bus clock
v2:
- Use a default PCIe bus clock in the device's dtsi
arch/arm/boot/dts/r8a7791.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/arm/boot/dts/r8a7791.dtsi +9 -0
@@ -532,6 +532,15 @@ clock-output-names = "extal"; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie_bus"; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7791-cpg-clocks",
Signature · 1 line
2.0.0
Re: [PATCH v3 5/8] ARM: shmobile: r8a7791: Add default PCIe bus clock
In reply to Laurent PinchartHi Phil,
Thank you for the patch.
Quoted 3 lines · On Friday 13 June 2014 10:37:19 Phil Edworthy wrote:
This patch adds a default PCIe bus clock node.
Signed-off-by Phil Edworthy <[email protected]>
Quoted 30 lines
---
v3:
- By default, disable the PCIe bus clockv2:
- Use a default PCIe bus clock in the device's dtsiarch/arm/boot/dts/r8a7791.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)arch/arm/boot/dts/r8a7791.dtsi +9
-0@@ -532,6 +532,15 @@ clock-output-names = "extal"; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie_bus"; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7791-cpg-clocks",
Signature · 3 lines
Regards, Laurent Pinchart
Re: [PATCH v3 5/8] ARM: shmobile: r8a7791: Add default PCIe bus clock
In reply to Laurent PinchartQuoted 36 lines · Phil Edworthy
This patch adds a default PCIe bus clock node.
Signed-off-by Phil Edworthy <[email protected]>---
v3:
- By default, disable the PCIe bus clockv2:
- Use a default PCIe bus clock in the device's dtsiarch/arm/boot/dts/r8a7791.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)arch/arm/boot/dts/r8a7791.dtsi +9
-0@@ -532,6 +532,15 @@ clock-output-names = "extal"; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie_bus"; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7791-cpg-clocks",Signature · 1 line
2.0.0
Hi Phil,
I encountered a minor conflict when applying this patch.
The version that I have queued-up is below, please check that it is correct.
From: Phil Edworthy <[email protected]>
[PATCH] ARM: shmobile: r8a7791: Add default PCIe bus clock
This patch adds a default PCIe bus clock node.
--- arch/arm/boot/dts/r8a7791.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/arm/boot/dts/r8a7791.dtsi +9 -0
@@ -555,6 +555,15 @@ clock-output-names = "audio_clk_c"; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie_bus"; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7791-cpg-clocks",
Signature · 1 line
2.0.0.rc2
RE: [PATCH v3 5/8] ARM: shmobile: r8a7791: Add default PCIe bus clock
In reply to Laurent PinchartHi Simon,
Quoted 42 lines · Simon
Quoted 7 lines · Phil Edworthy
This patch adds a default PCIe bus clock node.
Signed-off-by Phil Edworthy <[email protected]>---
v3:
- By default, disable the PCIe bus clockReview
Quoted 7 lines
v2:
- Use a default PCIe bus clock in the device's dtsiarch/arm/boot/dts/r8a7791.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)(quoted diff) +0
-0
b/arch/arm/boot/dts/r8a7791.dtsiQuoted 20 lines
index 1e644eb..7c4f7c7 100644
arch/arm/boot/dts/r8a7791.dtsi +9
-1@@ -532,6 +532,15 @@ clock-output-names = "extal"; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie_bus"; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7791-cpg-clocks", --Quoted 2 lines
2.0.0
Hi Phil,
Quoted 2 lines
I encountered a minor conflict when applying this patch.
The version that I have queued-up is below, please check that it is correct.
Yes, that's fine.
Thanks
Phil
Quoted 37 lines
From: Phil Edworthy <[email protected]>
[PATCH] ARM: shmobile: r8a7791: Add default PCIe bus clock
This patch adds a default PCIe bus clock node.
Signed-off-by Phil Edworthy <[email protected]>Acked-by Laurent Pinchart <[email protected]>[[email protected]: resolved conflict]Signed-off-by Simon Horman <[email protected]>--- arch/arm/boot/dts/r8a7791.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)arch/arm/boot/dts/r8a7791.dtsi +9
-1@@ -555,6 +555,15 @@ clock-output-names = "audio_clk_c"; }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "pcie_bus"; + status = "disabled"; + }; + /* Special CPG clocks */ cpg_clocks: cpg_clocks@e6150000 { compatible = "renesas,r8a7791-cpg-clocks", --2.0.0.rc2
PATCH v3 6/8 ARM: shmobile: r8a7790: Add clocks
In reply to Laurent PinchartDeclare all core clocks and DIV6 clocks, as well as all MSTP clocks currently used by r8a7790 boards.
--- arch/arm/boot/dts/r8a7790.dtsi | 316 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 316 insertions(+)
arch/arm/boot/dts/r8a7790.dtsi +316 -0
@@ -8,6 +8,7 @@ * kind, whether express or implied. */ +#include <dt-bindings/clock/r8a7790-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h>
@@ -280,4 +281,319 @@ cap-sd-highspeed; status = "disabled"; }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* External root clock */ + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overriden by the board. */ + clock-frequency = <0>; + clock-output-names = "extal"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks at e6150000 { + compatible = "renesas,r8a7790-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "sd1", + "z"; + }; + + /* Variable factor clocks */ + sd2_clk: sd2_clk at e6150078 { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150078 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd2"; + }; + sd3_clk: sd3_clk at e615007c { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615007c 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd3"; + }; + mmc0_clk: mmc0_clk at e6150240 { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150240 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc0"; + }; + mmc1_clk: mmc1_clk at e6150244 { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150244 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc1"; + }; + ssp_clk: ssp_clk at e6150248 { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150248 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "ssp"; + }; + ssprs_clk: ssprs_clk at e615024c { + compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615024c 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "ssprs"; + }; + + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll1_div2"; + }; + z2_clk: z2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "z2"; + }; + zg_clk: zg_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zg"; + }; + zx_clk: zx_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zx"; + }; + zs_clk: zs_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "zs"; + }; + hp_clk: hp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "hp"; + }; + i_clk: i_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "i"; + }; + b_clk: b_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "b"; + }; + p_clk: p_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "p"; + }; + cl_clk: cl_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + clock-output-names = "cl"; + }; + m2_clk: m2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "m2"; + }; + imp_clk: imp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "imp"; + }; + rclk_clk: rclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(48 * 1024)>; + clock-mult = <1>; + clock-output-names = "rclk"; + }; + oscclk_clk: oscclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(12 * 1024)>; + clock-mult = <1>; + clock-output-names = "oscclk"; + }; + zb3_clk: zb3_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "zb3"; + }; + zb3d2_clk: zb3d2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "zb3d2"; + }; + ddr_clk: ddr_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7790_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "ddr"; + }; + mp_clk: mp_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + clock-output-names = "mp"; + }; + cp_clk: cp_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "cp"; + }; + + /* Gate clocks */ + mstp1_clks: mstp1_clks at e6150134 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, + <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, + <&zs_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 + R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 + R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY + >; + clock-output-names = + "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", + "vsp1-du0", "vsp1-rt", "vsp1-sy"; + }; + mstp2_clks: mstp2_clks at e6150138 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 + R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 R8A7790_CLK_SCIFB2 + >; + clock-output-names = + "scifa2", "scifa1", "scifa0", "scifb0", "scifb1", + "scifb2"; + }; + mstp3_clks: mstp3_clks at e615013c { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, + <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, + <&mmc0_clk>, <&rclk_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 + R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 + R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1 + >; + clock-output-names = + "tpu0", "mmcif1", "sdhi3", "sdhi2", + "sdhi1", "sdhi0", "mmcif0", "cmt1"; + }; + mstp5_clks: mstp5_clks at e6150144 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; + clocks = <&extal_clk>, <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; + clock-output-names = "thermal", "pwm"; + }; + mstp7_clks: mstp7_clks at e615014c { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, + <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_HSCIF1 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 + R8A7790_CLK_SCIF0 R8A7790_CLK_DU2 R8A7790_CLK_DU1 + R8A7790_CLK_DU0 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 + >; + clock-output-names = + "hscif1", "hscif0", "scif1", "scif0", "du2", "du1", + "du0", "lvds1", "lvds0"; + }; + mstp8_clks: mstp8_clks at e6150990 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = <R8A7790_CLK_ETHER>; + clock-output-names = "ether"; + }; + mstp9_clks: mstp9_clks at e6150994 { + compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; + clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_I2C3 + R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 + >; + clock-output-names = "rcan1", "rcan0", "i2c3", "i2c2", "i2c1", "i2c0"; + }; + }; };
Signature · 1 line
1.8.3.2
PATCH v3 7/8 ARM: shmobile: r8a7790: Reference clocks
In reply to Laurent PinchartReference clocks using a "clocks" property in all nodes corresponding to devices that require a clock.
--- arch/arm/boot/dts/r8a7790.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
arch/arm/boot/dts/r8a7790.dtsi +10 -0
@@ -190,6 +190,7 @@ reg = <0 0xe6508000 0 0x40>; interrupt-parent = <&gic>; interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_I2C0>; status = "disabled"; };
@@ -200,6 +201,7 @@ reg = <0 0xe6518000 0 0x40>; interrupt-parent = <&gic>; interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_I2C1>; status = "disabled"; };
@@ -210,6 +212,7 @@ reg = <0 0xe6530000 0 0x40>; interrupt-parent = <&gic>; interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_I2C2>; status = "disabled"; };
@@ -220,6 +223,7 @@ reg = <0 0xe6540000 0 0x40>; interrupt-parent = <&gic>; interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_I2C3>; status = "disabled"; };
@@ -228,6 +232,7 @@ reg = <0 0xee200000 0 0x80>; interrupt-parent = <&gic>; interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; reg-io-width = <4>; status = "disabled"; };
@@ -237,6 +242,7 @@ reg = <0 0xee220000 0 0x80>; interrupt-parent = <&gic>; interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; reg-io-width = <4>; status = "disabled"; };
@@ -251,6 +257,7 @@ reg = <0 0xee100000 0 0x100>; interrupt-parent = <&gic>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; cap-sd-highspeed; status = "disabled"; };
@@ -260,6 +267,7 @@ reg = <0 0xee120000 0 0x100>; interrupt-parent = <&gic>; interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; cap-sd-highspeed; status = "disabled"; };
@@ -269,6 +277,7 @@ reg = <0 0xee140000 0 0x100>; interrupt-parent = <&gic>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; cap-sd-highspeed; status = "disabled"; };
@@ -278,6 +287,7 @@ reg = <0 0xee160000 0 0x100>; interrupt-parent = <&gic>; interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; cap-sd-highspeed; status = "disabled"; };
Signature · 1 line
1.8.3.2
PATCH v3 8/8 ARM: shmobile: r8a7791: Add clocks
In reply to Laurent PinchartDeclare all core clocks and DIV6 clocks, as well as all MSTP clocks currently used by r8a7791 boards.
--- arch/arm/boot/dts/r8a7791.dtsi | 312 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 312 insertions(+)
arch/arm/boot/dts/r8a7791.dtsi +312 -0
@@ -9,6 +9,7 @@ * kind, whether express or implied. */ +#include <dt-bindings/clock/r8a7791-clock.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h>
@@ -176,4 +177,315 @@ reg = <0 0xe6060000 0 0x250>; #gpio-range-cells = <3>; }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* External root clock */ + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overriden by the board. */ + clock-frequency = <0>; + clock-output-names = "extal"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks at e6150000 { + compatible = "renesas,r8a7791-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "z"; + }; + + /* Variable factor clocks */ + sd1_clk: sd2_clk at e6150078 { + compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150078 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd1"; + }; + sd2_clk: sd3_clk at e615007c { + compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615007c 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sd2"; + }; + mmc0_clk: mmc0_clk at e6150240 { + compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150240 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "mmc0"; + }; + ssp_clk: ssp_clk at e6150248 { + compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe6150248 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "ssp"; + }; + ssprs_clk: ssprs_clk at e615024c { + compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; + reg = <0 0xe615024c 0 4>; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "ssprs"; + }; + + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll1_div2"; + }; + zg_clk: zg_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zg"; + }; + zx_clk: zx_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zx"; + }; + zs_clk: zs_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "zs"; + }; + hp_clk: hp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "hp"; + }; + i_clk: i_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "i"; + }; + b_clk: b_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "b"; + }; + p_clk: p_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "p"; + }; + cl_clk: cl_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + clock-output-names = "cl"; + }; + m2_clk: m2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "m2"; + }; + imp_clk: imp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "imp"; + }; + rclk_clk: rclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(48 * 1024)>; + clock-mult = <1>; + clock-output-names = "rclk"; + }; + oscclk_clk: oscclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(12 * 1024)>; + clock-mult = <1>; + clock-output-names = "oscclk"; + }; + zb3_clk: zb3_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "zb3"; + }; + zb3d2_clk: zb3d2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "zb3d2"; + }; + ddr_clk: ddr_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7791_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "ddr"; + }; + mp_clk: mp_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + clock-output-names = "mp"; + }; + cp_clk: cp_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "cp"; + }; + + /* Gate clocks */ + mstp1_clks: mstp1_clks at e6150134 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, + <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 + R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 + R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY + >; + clock-output-names = + "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", + "vsp1-du0", "vsp1-sy"; + }; + mstp2_clks: mstp2_clks at e6150138 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 + R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 R8A7791_CLK_SCIFB2 + >; + clock-output-names = + "scifa2", "scifa1", "scifa0", "scifb0", "scifb1", + "scifb2"; + }; + mstp3_clks: mstp3_clks at e615013c { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, + <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 + R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1 + >; + clock-output-names = + "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1"; + }; + mstp5_clks: mstp5_clks at e6150144 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; + clocks = <&extal_clk>, <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; + clock-output-names = "thermal", "pwm"; + }; + mstp7_clks: mstp7_clks at e615014c { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>, + <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, + <&zx_clk>, <&zx_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 R8A7791_CLK_SCIF4 + R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 R8A7791_CLK_SCIF3 + R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 R8A7791_CLK_SCIF0 + R8A7791_CLK_DU1 R8A7791_CLK_DU0 R8A7791_CLK_LVDS0 + >; + clock-output-names = + "hscif2", "scif5", "scif4", "hscif1", "hscif0", "scif3", + "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; + }; + mstp8_clks: mstp8_clks at e6150990 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = <R8A7791_CLK_ETHER>; + clock-output-names = "ether"; + }; + mstp9_clks: mstp9_clks at e6150994 { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; + clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, + <&p_clk>, <&p_clk>, <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_I2C4 + R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 + R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 + >; + clock-output-names = + "rcan1", "rcan0", "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", + "i2c0"; + }; + mstp11_clks: mstp11_clks at e615099c { + compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 + >; + clock-output-names = "scifa3", "scifa4", "scifa5"; + }; + }; };
Signature · 1 line
1.8.3.2